KR20090077195A - Semiconductor device and manufacturing method - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided, which can reduce the number of bit line by forming the bit line between the active areas. The semiconductor substrate(200) is arranged in the zigzag type so that the active areas can face with each other. The gate(220) is formed on the semiconductor substrate having the active area. The bit line contact(260) is formed in the corner of the active area of triangle and overhang. The bit line contact connects the active area and bit line.

Description

Semiconductor device and method of manufacturing the same {Semiconductor device and method of maufacturing the same}

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same that can reduce the number of bit lines.

As high integration of semiconductor devices proceeds, technology for using bit lines, which provide input / output paths of data in the devices, as low-resistance and high melting point metals such as tungsten (W) in order to facilitate the electrical signal transmission of the devices It's going on.

Since the high melting point metal, such as tungsten, has a relatively low resistivity compared to the conventional bit line material tungsten silicide (WSix), the bit line of the high melting point metal material may satisfy the operation speed required for the highly integrated device. .

Hereinafter, a bit line forming method of a semiconductor device according to the prior art will be briefly described with reference to FIGS. 1A to 1C.

Referring to FIG. 1A, after a gate 120 is formed on a semiconductor substrate 100 having a plurality of active regions 110 having an I-type, a subsequent bit line contact forming region and a storage node of the semiconductor substrate are formed. The junction region 130 is formed in the contact formation region.

Referring to FIG. 1B, after forming an interlayer insulating film on the semiconductor substrate 100 on which the gate 120 and the junction region 130 are formed, the active region is adjacent to the active region 110 on the interlayer insulating film. To form a photoresist pattern of the same form as.

Thereafter, using the photoresist pattern as an etch mask, the interlayer insulating layer is etched to form a contact hole defining a landing plug contact, and then the photoresist pattern is removed according to a known process.

Next, after the polysilicon film for landing plug contact is deposited on the interlayer insulating layer including the contact hole, the polysilicon film is etched to form a landing plug contact 150 in the contact hole.

Referring to FIG. 1C, after the bit line contact 160 is formed on the landing plug contact 150 formed on the bit line formation region, all the bit line contacts are formed along the direction perpendicular to the direction of the gate 120. The bit line 170 is formed between each of the active regions 110 to contact the fields 160.

However, as the size of the semiconductor device is getting smaller, the size of the bit lines is becoming smaller and smaller.

As described above, as the size of the bit line progresses in size, the process of forming the bit line becomes more difficult.

As a result, during the process of forming a large number of bit lines, often failed bit lines are generated, and as the number of bit lines gradually increases, the number of failed bit lines will increase.

As a result, it is difficult to secure the process margin of the bit line as the process of forming the bit line becomes difficult due to the high integration of the semiconductor device.

An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can reduce the number of bit lines.

The present invention provides a semiconductor substrate comprising a semiconductor substrate arranged in a zigzag form so that the active regions of a triangle and an inverted triangle face each other apart from each other; A gate formed on the semiconductor substrate having the active region; And a bit line overlapping the pair of active regions between the pair of active regions facing each other apart from each other in a direction perpendicular to the direction of the gate.

The method may further include a bit line contact formed at a vertex of the active area of the triangle and the inverted triangle and connecting the active area and the bit line.

In addition, the present invention comprises the steps of forming a gate on a semiconductor substrate arranged in a zigzag form facing each other spaced apart from the active areas of the triangle and inverted triangle; Forming a source / drain region in the active region on both sides of the gate; Forming a landing plug contact on the semiconductor substrate at both sides of the gate to contact the source / drain region; Forming a bit line contact on the landing plug contact formed in the drain region; Forming a bit line overlapping the pair of active regions between the pair of active regions spaced apart from each other to connect all the bit line contacts formed along the direction perpendicular to the gate direction; It provides a method for manufacturing a semiconductor device.

The bit line may be formed on an upper portion of the landing plug contact formed at a vertex of the active area of the triangle and the inverted triangle.

According to the present invention, by forming a bit line between a pair of active regions spaced apart from each other, it is possible to reduce the number of bit lines compared to a conventional bit line formed between the active regions.

Accordingly, the present invention can secure the process margin of the bit line by reducing the number of bit lines at the time when the process of forming the bit line becomes difficult due to the high integration of the semiconductor device.

According to the present invention, the pair is disposed between the pair of active regions facing each other in a direction perpendicular to the gate direction on a semiconductor substrate in which triangular and inverted triangular active regions are spaced apart and face each other in a zigzag form. A bit line overlapping with the active regions of is formed.

In this case, the bit lines are formed between a pair of active regions facing each other at a distance, thereby reducing the number of bit lines by half compared to the conventional technology in which bit lines are formed between the active regions. .

Therefore, the present invention can achieve a process margin by reducing the number of bit lines at a time when the bit line forming process becomes difficult due to high integration of semiconductor devices.

2 is a plan view showing a semiconductor device according to an embodiment of the present invention.

As shown, the gate 220 is formed on the semiconductor substrate 200 arranged in a zigzag form so that the active regions 210 of the triangle and the inverted triangle face each other, and the active region of the triangle and the inverted triangle is formed. The bit line contact 260 is formed at a vertex portion of the 210, and the pair of active regions facing and spaced apart from each other to connect all the bit line contacts 260 formed along the direction perpendicular to the gate 220 direction. A bit line 270 overlapping the pair of active regions is formed between 210.

Unexplained reference numeral 250 denotes a landing plug contact.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In detail, FIGS. 3A to 3D are plan views according to processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, a gate 220 is formed on a semiconductor substrate 200 including active regions 210 of triangles and inverted triangles.

Preferably, the triangular and inverted triangular active regions 210 are spaced apart from each other in a zigzag form to form a stacked layer of a gate insulating film, a polysilicon and a gate metal film, and a gate hard mask film. A gate 220 is formed.

Then, source / drain regions 230 and 240 are formed in the semiconductor substrate active region 210 at both sides of the gate 220.

Referring to FIG. 3B, a first interlayer insulating layer is formed on the semiconductor substrate 200 on which the gate 220 and the source / drain regions 230 and 240 are formed.

Next, a mask pattern (not shown) of a photosensitive material is formed on the first interlayer insulating layer to expose the landing plug contact forming region. Preferably, a space between the active regions 210 and the drain region 240 that are not spaced apart from each other in a direction perpendicular to the gate 220 direction on the first interlayer insulating layer is formed. A mask bar type mask pattern is formed.

Next, the first interlayer insulating layer is etched to form a landing plug contact hole exposing the source / drain regions 230 and 240 of the semiconductor substrate, and then the mask pattern is removed according to a known process.

Then, after depositing a landing plug contact conductive layer on the first interlayer insulating layer including the landing plug contact hole, the conductive layer is etched to contact the source / drain regions 230 and 240 in the landing plug contact hole. The landing plug contact 250 is formed.

Referring to FIG. 3C, after the second interlayer insulating layer is formed on the landing plug contact 250 and the first interlayer insulating layer, the landing plug contact formed in the drain region 240 by etching the second interlayer insulating layer. A contact hole for bit line contact exposing the portion 250 is formed.

Preferably, a contact hole for a bit line contact is formed to expose a portion of the landing plug contact 250 formed at a vertex of the triangular and inverted triangular active regions 210.

Then, after depositing the bit line contact metal film on the second interlayer insulating layer including the contact hole, the bit line contact metal film is etched to form the triangle and inverted triangle active regions in the bit line contact hole. A bit line contact 260 is formed to contact a portion of the landing plug contact 250 formed at a vertex of 210.

Referring to FIG. 3D, after depositing the bit line metal layer on the second interlayer dielectric layer on which the bit line contact 260 is formed, the bit line metal layer is etched to be in a direction perpendicular to the gate 220 direction. Bit lines 270 are formed to connect all the formed bit line contacts 260.

Preferably, the bit line 270 overlaps the pair of active regions 210 between the pair of active regions 210 facing each other apart from each other in a direction perpendicular to the direction of the gate 220. ).

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to manufacture a semiconductor device according to an exemplary embodiment of the present invention.

As such, the bit lines are not formed between the active regions, but are formed between the pair of active regions facing each other at a distance, thereby reducing the number of bit lines.

Accordingly, the present invention can secure the process margin of the bit line by reducing the number of bit lines at the time when the process of forming the bit line becomes difficult due to the high integration of the semiconductor device.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1A to 1C are plan views illustrating processes for forming a bit line of a semiconductor device according to the related art.

2 is a plan view for explaining a semiconductor device according to an embodiment of the present invention.

3A to 3D are plan views for each process for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200: semiconductor substrate 210: active region

220: gate 230: source region

240: drain region 250: landing plug contact

260: bit line contact 270: bit line

200M: photoresist pattern

Claims (4)

A semiconductor substrate arranged in a zigzag form in which triangular and inverted triangular active regions face each other apart from each other; A gate formed on the semiconductor substrate having the active region; And A bit line overlapping the pair of active regions between the pair of active regions facing each other in the direction perpendicular to the direction of the gate; A semiconductor device comprising a. The method of claim 1, And a bit line contact formed at a vertex of the active region of the triangle and the inverted triangle and connecting the active region and the bit line. Forming a gate on a semiconductor substrate arranged in a zigzag form so that triangular and inverted triangular active regions face each other apart from each other; Forming a source / drain region in the active region on both sides of the gate; Forming a landing plug contact on the semiconductor substrate at both sides of the gate to contact the source / drain region; Forming a bit line contact on a landing plug contact formed in the drain region; Forming a bit line while overlapping the pair of active regions between the pair of active regions spaced apart from each other so as to connect all the bit line contacts formed along the direction perpendicular to the gate direction; Method of manufacturing a semiconductor device comprising a. The method of claim 3, wherein And the bit line contact is formed on a landing plug contact formed at a vertex of an active region of the triangle and the inverted triangle.

Images