KR101103774B1 - A nitride semiconductor device having a recess gate edge structure and a method of manufacturing the same - Google Patents

Abstract

According to the present invention, a nitride based semiconductor device includes a nitride based semiconductor layer, a source electrode formed on one side of an upper surface of the nitride based semiconductor layer, a drain electrode spaced apart from the source electrode on the other side of the nitride based semiconductor layer, and the nitride A gate electrode formed between the source electrode and the drain electrode on an upper surface of the semiconductor layer, and a recess is formed between the gate electrode and the drain electrode in the nitride-based semiconductor layer below one side of the gate electrode According to the present invention, the electron trap is reduced, the leakage current is reduced due to the surface electric field reduction effect, the breakdown voltage is increased, and at the same time, the forward current-voltage characteristics are maintained.

Description

Nitride-based semiconductor device having a recess gate edge structure and a method of manufacturing the same {NITRIDE BASED SEMICONDUCTOR DEVICE EMPLOYING RECESSED GATE EDGE STRUCTURE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of increasing the breakdown voltage of a nitride semiconductor device and a method of manufacturing the same.

Recently, wide band-gap materials, such as gallium nitride (GaN) and silicon carbide (SiC), have been in the spotlight in electric power systems. GaN, in particular, has excellent physical properties compared to other semiconductor materials such as excellent forward characteristics, high breakdown electric field, and low intrinsic carrier density.

GaN material-based semiconductor devices include Schottky barrier diodes, metal oxide semiconductor field effect transistors (MOSFETs), metal semiconductor field effect transistors (MSFETs), high Electron Mobility Transistors (HEMTs).

Meanwhile, the AlGaN / GaN heterostructure has a high 2-Dimensional Electron Gas (2DEG) concentration due to the discontinuity of the conduction band between the AlGaN and GaN and the piezoelectric effect. Accordingly, high electron mobility transistors and Schottky barrier diodes fabricated on AlGaN / GaN heterostructures have high two-dimensional electron gas concentrations (10 ¹³ cm ^-2 ) and high critical electric fields, making them widely used in high voltage switch and high frequency amplifier applications. Is being studied.

However, a high electron mobility transistor or a Schottky barrier diode fabricated on an AlGaN / GaN heterostructure has a problem in that electrical characteristics of the device are degraded due to an electron trap. In other words, when electrons are injected into an electron trap of an AlGaN / GaN hetero structure by an electric field, 2DEG channel depletion, forward current decrease, surface leakage current increase, and trapping effect occur. Electron traps on the device adversely affect the electrical properties of the device.

Conventionally, as a method for suppressing leakage current of GaN devices, there are passivation, high temperature annealing, and field relaxation structures such as field plates and floating gates.

The passivation method is to prevent the injection of electrons by the deposited insulating film, the high temperature annealing process is to heat treatment in an inert gas atmosphere to heal the damage of the GaN surface. The field mitigation structure mitigates field concentrations occurring at the edges of Schottky contacts, reducing leakage currents.

On the other hand, a recess gate structure is a structure in which a recess such as a groove is formed in a semiconductor layer between a source electrode and a drain electrode in a transistor.

In recent years, in forming semiconductor devices according to the trend of miniaturization and high integration, various problems have occurred such that the channel length of transistors becomes shorter and the refresh characteristics deteriorate as the channel length becomes shorter. In order to solve this problem, a transistor structure having a recess channel in which a gate is formed through a recess formed in a semiconductor substrate has been proposed. This is a structure that increases the effective channel length by forming a recess in a region where a channel of the transistor is to be formed, thereby substantially increasing the distance between the source and the drain, thereby contributing to high integration of the semiconductor device.

An object of the present invention is to form a recess in the nitride-based semiconductor layer abuts the lower edge of the gate electrode, that is, the edge, so as to reduce the leakage current of the nitride-based semiconductor device, increase the breakdown voltage, and at the same time maintain the forward current-voltage characteristics. The present invention provides a nitride based semiconductor device employing a recess gate edge structure and a method of manufacturing the same.

In the nitride-based semiconductor device according to an embodiment of the present invention, a nitride-based semiconductor layer, a source electrode formed on one side of the upper surface of the nitride-based semiconductor layer, the drain formed spaced apart from the source electrode on the other side of the upper surface of the nitride-based semiconductor layer An electrode, and a gate electrode formed between the source electrode and the drain electrode on an upper surface of the nitride based semiconductor layer, and between the gate electrode and the drain electrode, a recess in the nitride based semiconductor layer below one side of the gate electrode (recess) is formed.

In the embodiment, the nitride-based semiconductor layer is formed on an insulating substrate, an upper surface of the substrate and a crystal nucleation layer formed to grow an epi structure of the first nitride-based semiconductor, and formed on the crystal nucleation layer. A buffer layer, which is a first nitride semiconductor, and a barrier layer, which is formed on an upper surface of the buffer layer, forms a two-dimensional electron gas layer between the buffer layer, and a second nitride semiconductor.

In the method of manufacturing a nitride-based semiconductor device according to an embodiment of the present invention, forming a nitride-based semiconductor layer, forming a source electrode on one side of the upper surface of the nitride-based semiconductor layer, the other surface of the nitride-based semiconductor layer Forming a drain electrode spaced apart from the source electrode on the side, forming a gate electrode between the source electrode and the drain electrode on an upper surface of the nitride based semiconductor layer, and between the gate electrode and the drain electrode Forming a recess (recess) in the nitride-based semiconductor layer on the lower side of one side.

In the above embodiment, the forming of the nitride based semiconductor layer may include forming a crystal nucleation layer for growing an epitaxial structure of the first nitride based semiconductor on an insulating substrate. Forming a buffer layer that is the first nitride semiconductor, forming a two-dimensional electron gas layer between the buffer layer and a barrier layer that is a second nitride semiconductor on the upper surface of the buffer layer, and an upper surface of the barrier layer Forming an unintentionally doped cap layer.

The nitride-based semiconductor device and the method of manufacturing the same according to the present invention reduce the electron trap by applying the recess gate edge structure, reduce the leakage current due to the surface electric field reduction effect, increase the breakdown voltage, and at the same time, the forward current-voltage There is an advantage that the property is maintained.

1 is a cross-sectional view of a nitride based semiconductor device having a recess gate edge structure according to an embodiment of the present invention;
2 and 3 are flowcharts illustrating respective steps of a method of manufacturing a nitride-based semiconductor device having a recess gate edge structure according to the present invention;
4 is a cross-sectional view showing the distribution of depletion regions in reverse bias application;
5 is a chart showing breakdown voltage characteristics;
6 is a diagram showing forward current-voltage characteristics;
7 is a diagram showing current-voltage characteristics;
8 is a table showing surface electric field characteristics.

In the following description of the present invention, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention.

Hereinafter, a nitride based semiconductor device and a method of a recess gate edge structure according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a nitride based semiconductor device having a recess gate edge structure according to an embodiment of the present invention.

The nitride based semiconductor device having the recess gate edge structure according to the exemplary embodiment of the present invention includes a nitride based semiconductor layer 101, a source electrode 16, a drain electrode 17, and a gate electrode 18. In addition, in the above embodiment, the nitride based semiconductor layer 101 may include an insulating substrate 11, a crystal nucleation layer 12, a buffer layer 13, and a barrier layer 14. As in the embodiment shown in Figure 1 may further include a cap layer (15).

In the embodiments, a recess is formed in the nitride based semiconductor layer 101 from an edge of the gate electrode 18 in a first direction from the gate electrode 18 to the drain electrode 17. The recess is formed in the nitride based semiconductor layer 101 below one side of the gate electrode 18 between the gate electrode 18 and the drain electrode 17.

1, the insulating substrate 11 may be an insulating substrate, but may have a high resistance or be doped with an n-type or p-type. For example, the material constituting the substrate 11 may be 4H semi-insulating silicon carbide. In addition, the material of the substrate 11 may be formed using silicon, sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, GaAs, ZnO or InP.

The crystal nucleation layer 12 is used to minimize defects due to crystal lattice mismatch between the substrate 11 and the nitride semiconductor formed on the upper surface of the substrate, and according to the type of substrate and semiconductor used. Appropriate seed generation layer may be applied. According to an embodiment of the present invention, the crystal nucleation layer 12 may be formed of AlN.

The first nitride-based semiconductor buffer layer 13 and the second nitride-based semiconductor barrier layer 14 may be formed through a metal organic chemical vapor deposition (MOCVD) as a heterostructure of an AlGaN / GaN layer. have. The buffer layer 13 may be made of GaN doped with iron (Fe), and may have a thickness of 3 μm. In addition, the barrier layer 14 may be made of AlGaN, each element may be formed of (Al, Ga, and N) it is in different ratio, preferably may be the Al _{0 .26} Ga _{0 .74} N, thickness May be 30 nm. The GaN buffer layer 13 and the AlGaN barrier layer 14 may be formed through various deposition methods, and may be formed using, for example, a metal organic chemical vapor deposition method.

AlGaN has a larger band-gap than GaN, and a channel having a two-dimensional electron gas concentration is formed between the GaN buffer layer 13 and the AlGaN barrier layer 14 according to the embodiment. The two-dimensional electron gas layer 13-1 has high electron mobility and provides very high mutual conductance at high frequencies. AlGaN / GaN wafers can form mesas using Inductively Coupled Plasma-Reactive Ion Etching (ICP-RIE), which serves to separate devices.

The cap layer 15 is an epitaxial layer for improving breakdown voltage and surface leakage current characteristics, and is undoped when the buffer layer 13 and the barrier layer 14 are undoped. The breakdown voltage of the device can be further increased. Although the cap layer 15 may be formed on the top surface of the barrier layer 14 according to an embodiment of the present invention, the cap layer 15 may not be designed according to the device application.

Patterns of the source electrode 16 and the drain electrode 17 may be formed using a photolithography process. According to one embodiment of the present invention, after forming the pattern, the GaN wafer is immersed in NH ₄ F: HF 30: 1 solution for 30 seconds to remove the native oxide. According to the pattern, 20/80/20 of Ti / Al / Ni / Au, which is an ohmic metal, is formed by using an electron beam evaporator at a position where the natural oxide film of the barrier layer 14 or the cap layer 15 is removed and exposed. Deposit in 100 nm increments. After depositing the ohmic metal, the ohmic junction is formed using a lift-off. After forming the ohmic junction, the source electrode 16 and the drain electrode 17 can be formed by annealing using an RTA process, preferably by annealing for 30 seconds at a temperature of 870 ° C. and a nitrogen atmosphere. The source electrode 16 and the drain electrode 17 can be formed.

The pattern of the gate electrode 18 may be formed using a photolithography process. According to an embodiment of the present invention, after forming the pattern, Ni / Au / Ni is deposited by Schottky junction by an electron-beam evaporator in the same manner as the ohmic junction by 30/150/30 nm, respectively, by a lift-off process. Schottky junctions can be formed. According to one embodiment of the present invention, the Schottky junction may be implemented with other metals such as Pt, Ir, Pd, Mo or Au in addition to Ni. During Schottky junction, Pt has high breakdown voltage and low gate leakage current due to high metal work function, and Mo has the advantage of allowing stable operation at high temperature due to high melting point.

The recess is formed in the nitride based semiconductor layer 101 below one side of the gate electrode 18 between the gate electrode 18 and the drain electrode 17. The depth Dr of the recess represents a distance from the upper end of the nitride based semiconductor layer 101 in the thickness direction of the nitride based semiconductor layer 101. The length Lr of the recess represents the width of the recess formed in the nitride based semiconductor layer 101 from the edge of the gate electrode 18 toward the drain electrode 17.

Here, an edge of the gate electrode 18 refers to an edge of the gate electrode 18 at a surface where the gate electrode 18 and the nitride based semiconductor layer 101 contact each other.

According to one embodiment of the present invention, the length Lr of the recess is 9% or more and 11% or less of the distance between the gate electrode 18 and the drain electrode 17, preferably 10%. . The depth Dr of the recess exceeds the thickness of the cap layer 15 to be less than the sum of the thickness of the cap layer 15 and the thickness of the barrier layer 14. That is, when the distance between the gate electrode 18 and the drain electrode 17 is Lgd, the thickness of the cap layer 15 is Dc and the thickness of the barrier layer 14 is Db. The length Lr and the depth Dr of the recess are 0.09 × Lgd ≦ Lr ≦ 0.11 × Lgd and Dc <Dr <Dc + Db.

According to an embodiment of the present invention, specifically, the distance Lgd = 20 μm between the gate electrode 18 and the drain electrode 17, the thickness Dc of the cap layer 15 = 3 nm, and the barrier layer 14. When the thickness Db is 30 nm, the length Lr of the recess is 2 m and the depth Dr is 22 nm.

The cross-sectional shape of the recess may be variously formed. For example, the length and depth of the recess may be constant to form a rectangular shape, and the cross-sectional shape may be formed as a slated recess having a shape such as "V".

The recess may be formed through an etching process, and various kinds of etching processes may be used. For example, the etching process may be formed through a wet etching process using KOH or AZ400K, or a plasma etching process using BCl / Cl ₂ gas. In addition, an etching process using KOH may be used after damaging the surface of the nitride based semiconductor layer 101.

In the present invention, the effect of the formation of the recess will be described in Figures 4 to 8 below.

According to an embodiment of the present disclosure, the source electrode 16, the drain electrode 17, and the gate electrode 18 are formed on the nitride based semiconductor layer 101, and then oxygen annealed. Alternatively, according to another embodiment of the present invention, oxygen annealing is performed before forming the gate electrode 18. The oxygen annealing process may be performed using a furnace equipment, and may be performed in an oxygen atmosphere at 250 to 600 ° C. for 3 to 7 minutes, preferably at 300 ° C. for 5 minutes in an oxygen atmosphere. have.

The oxygen annealing process is performed on the nitride-based semiconductor device of the recess gate edge structure according to the present invention to reduce the leakage current and increase the breakdown voltage.

According to an exemplary embodiment, the nitride-based semiconductor device having the recess gate edge structure may be applied to an AlGaN / GaN high electron mobility transistor, but may be applied to various GaN-based high electron mobility transistors. For example, the present invention can be applied to various GaN-based devices such as a metal semiconductor field effect transistor, a horizontal GaN Schottky barrier diode and a vertical GaN bulk Schottky barrier diode formed on an upper surface of an AlGaN / GaN heterojunction wafer.

2 and 3 are flowcharts illustrating respective steps of a method of manufacturing a nitride-based semiconductor device having a recess gate edge structure according to the present invention.

First, as shown in FIG. 2, the nitride-based semiconductor device manufacturing method of the recess gate edge structure according to the embodiment of the present invention, the nitride-based semiconductor layer forming step (S21), source electrode forming step (S22), drain An electrode forming step S23, a gate electrode forming step S24, and a recess forming step S25 are included.

In addition, according to another embodiment of the present invention illustrated in FIG. 3, in the embodiment according to FIG. 2, the nitride-based semiconductor layer forming step S21 may include a crystal nucleation layer forming step S21-1 and a buffer layer forming. Step S21-2, barrier layer forming step S21-3, and cap layer forming step S21-4 are included.

Specifically, each step (S21-1 to S21-4) of the nitride-based semiconductor layer forming step (S21) will be described first.

In the crystal nucleation layer forming step (S21-1), the crystal nucleation layer is formed on an insulating substrate. The insulating substrate is an insulating substrate but may have high resistance or be doped with n-type or p-type. For example, the material constituting the substrate may be 4H semi-insulating silicon carbide. In addition, the material of the substrate may be formed using silicon, sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, GaAs, ZnO or InP.

The crystal nucleation layer is used to minimize defects due to crystal lattice mismatch between the substrate and the nitride semiconductor formed on the upper surface of the substrate. Can be applied. According to an embodiment of the present invention, the crystal nucleation layer may be formed of AlN.

In the buffer layer forming step (S21-2) and the barrier layer forming step (S21-3), the first nitride-based semiconductor buffer layer and the second nitride-based semiconductor barrier layer are MOCVD as a heterojunction structure of AlGaN / GaN layer. It can be formed through. The buffer layer may be formed of GaN doped with iron, and may have a thickness of 3 μm. In addition, the barrier layer may be formed of AlGaN, each element may be formed of (Al, Ga, and N) are in different ratio, preferably it may be the Al _{0 .26} Ga _{0 .74} N, thickness 30㎚ Can be The GaN buffer layer and the AlGaN barrier layer may be formed through various deposition methods, for example, by using a metal organic chemical vapor deposition method.

AlGaN has a larger band gap than GaN, and according to the embodiment, a channel having a two-dimensional electron gas concentration is formed between the GaN buffer layer and the AlGaN barrier layer. The two-dimensional electron gas layer has high electron mobility and provides very high interconductance at high frequencies. AlGaN / GaN wafers can form mesa structures using ICP-RIE, which serves to separate the devices.

In the cap layer forming step (S21-4), the cap layer is an epitaxial layer for improving breakdown voltage and surface leakage current characteristics, and may further increase breakdown voltage of the device when the buffer layer and the barrier layer are not doped. . According to an embodiment of the present invention, the cap layer may be formed on the top surface of the barrier layer, but the cap layer may not be designed according to a device application.

In the source electrode forming step (S22) and the drain electrode forming step (S23), the pattern of the source electrode and the drain electrode may be formed using a photo process. According to one embodiment of the present invention, after forming the pattern, the GaN wafer is immersed in NH ₄ F: HF 30: 1 solution for 30 seconds to remove the native oxide film. According to the pattern, 20/80/20/100 nm of Ti / Al / Ni / Au, which is an ohmic metal, is deposited using an electron-beam evaporator in the exposed position by removing the natural oxide film of the barrier layer or the cap layer. . After depositing the ohmic metal, the lift-off is used to form the ohmic junction. After forming the ohmic junction, the source electrode and the drain electrode may be formed by annealing using an RTA process, and preferably, the source electrode and the drain electrode are annealed at a temperature of 870 ° C. and a nitrogen atmosphere for 30 seconds. Can be formed.

In the gate electrode forming step (S24), the pattern of the gate electrode may be formed using a photo process. According to an embodiment of the present invention, after forming the pattern, Ni / Au / Ni is deposited by Schottky junction by an electron-beam evaporator in the same manner as the ohmic junction by 30/150/30 nm, respectively, by a lift-off process. Schottky junctions can be formed. According to one embodiment of the present invention, the Schottky junction may be implemented with other metals such as Pt, Ir, Pd, Mo or Au in addition to Ni. During Schottky junction, Pt has high breakdown voltage and low gate leakage current due to high metal work function, and Mo has the advantage of allowing stable operation at high temperature due to high melting point.

In the recess forming step S25, the recess is formed in the nitride based semiconductor layer below one side of the gate electrode between the gate electrode and the drain electrode. The depth Dr of the recess represents a distance from an upper end of the nitride based semiconductor layer in the thickness direction of the nitride based semiconductor layer. The length Lr of the recess represents the width of the recess formed in the nitride based semiconductor layer from the edge of the gate electrode toward the drain electrode.

Here, an edge of the gate electrode refers to an edge of the gate electrode at a surface where the gate electrode and the nitride based semiconductor layer contact.

According to an embodiment of the present invention, the length Lr of the recess is 9% or more and 11% or less of the distance between the gate electrode and the drain electrode, preferably 10%. The depth Dr of the recess exceeds the thickness of the cap layer to be less than the sum of the thickness of the cap layer and the thickness of the barrier layer. That is, when the distance between the gate electrode and the drain electrode is Lgd, the thickness of the cap layer is Dc, and the thickness of the barrier layer is Db, the first length Lr and the first depth Dr. Is 0.09 × Lgd ≦ Lr ≦ 0.11 × Lgd and Dc <Dr <Dc + Db.

According to one embodiment of the present invention, the recess Lgd is equal to 20 μm between the gate electrode and the drain electrode, the thickness Dc of the cap layer is 3 nm, and the thickness Db of the barrier layer is 30 nm. The length Lr is 2 µm and the depth Dr is 22 nm.

The cross-sectional shape of the recess may be variously formed. For example, the length and depth of the recess may be constant, and may be formed in a rectangular shape, and the cross-sectional shape may be formed as a slit recess of a shape such as "V".

The recess may be formed through an etching process, and various kinds of etching processes may be used. For example, the etching process may be formed through a wet etching process using KOH or AZ400K, or a plasma etching process using BCl / Cl ₂ gas. In addition, an etching process using KOH may be used after damaging the surface of the nitride based semiconductor layer.

In the present invention, the effect of the formation of the recess will be described in Figures 4 to 8 below.

According to an embodiment of the present disclosure, the source electrode, the drain electrode, and the gate electrode are formed on the nitride-based semiconductor layer, followed by oxygen annealing. Alternatively, according to another embodiment of the present invention, oxygen annealing is performed before forming the gate electrode. The oxygen annealing process may be performed using a furnace equipment, and may be performed at 250 to 600 ° C. for 3 to 7 minutes in an oxygen atmosphere, and preferably at 300 ° C. for 5 minutes in an oxygen atmosphere.

The oxygen annealing process of the method for manufacturing the nitride-based semiconductor device having the recess gate edge structure according to the present invention has the advantage of reducing the leakage current and increasing the breakdown voltage.

According to an exemplary embodiment, the nitride-based semiconductor device having the recess gate edge structure may be applied to an AlGaN / GaN high electron mobility transistor, but may be applied to various GaN-based high electron mobility transistors. For example, the present invention can be applied to various GaN-based devices such as a metal semiconductor field effect transistor, a horizontal GaN Schottky barrier diode and a vertical GaN bulk Schottky barrier diode formed on an upper surface of an AlGaN / GaN heterojunction wafer.

4 is a cross-sectional view illustrating a distribution of a depletion region when applying reverse bias.

Figure 4 (a) shows a nitride based semiconductor device according to the prior art, Figure 4 (b) shows a nitride based semiconductor device according to the present invention. As shown in FIG. 4, in the nitride semiconductor device according to the related art and the present invention, the gate electrode has a width of 3 μm, the distance Lgd between the gate electrode and the drain electrode is 20 μm, and the thickness of the cap layer is 3 μm. Nm, the thickness of the barrier layer is 30 nm, the thickness of the buffer layer is 3 mu m, the depth Dr of the recess is 22 nm, and the length Lr of the recess is set to 2 mu m, and the results are compared.

Comparing the nitride semiconductor devices shown in Figs. 4A and 4B, the depletion region is smaller than that of the present invention (Fig. 4A). It can be seen that the distribution is more uniformly (uniformly). Therefore, in the nitride-based semiconductor device according to the present invention, the electric field concentration phenomenon is reduced. Since the field concentration at the gate edge is reduced, the maximum electric field is reduced and thus the breakdown voltage is reduced.

5 is a chart showing breakdown voltage characteristics of a nitride semiconductor device.

As shown in FIG. 5, the breakdown voltage of the semiconductor device according to the prior art 51 is 962V, and the breakdown voltage of the semiconductor device 52 according to the present invention is 1160V, which is about 20.58%. have.

In the application of reverse bias, the semiconductor device according to the related art is known that electron trapping occurring from the gate to the surface-state of the barrier layer is the cause of the virtual gate effect. do. The hypothetical gate effect worsens the breakdown voltage and leakage current characteristics. In the nitride-based semiconductor device according to the present invention, since the nitride-based semiconductor layer at the gate edge portion is removed, the electron trapping phenomenon occurring on the surface of the nitride-based semiconductor layer from the gate is reduced, thus solving the virtual gate effect problem. do. This increases the breakdown voltage of the nitride semiconductor device according to the present invention.

In addition, because the barrier layer is partially thinned, the polarization field is mitigated in the etched area, i.e., under the recess, and the electron trapping from the surface-state to the 2DEG is reduced, resulting in a reverse direction. Leakage current is reduced. When the blocking voltage is 850 V, the nitride semiconductor device according to the prior art is 10 mA / mm, but the nitride semiconductor device according to the present invention is 1 mA / mm, thereby showing excellent characteristics.

FIG. 6 is a diagram comparing forward current-voltage characteristics before and after formation of a recess in the gate edge portion of a nitride based semiconductor device.

As shown in FIG. 6, when the gate bias is 1 V, the maximum drain current is 503.37 mA / mm in the case of the nitride semiconductor device according to the prior art, whereas the maximum drain current is in the case of the nitride semiconductor device according to the present invention. You can see the decrease to 463.17 mA / mm. The partially etched barrier layer reduces drain current by about 90% in the case of the present invention compared to the prior art. The reduced thickness of the barrier layer reduces the 2DEG density, thereby improving reverse leakage current characteristics.

7 is a diagram showing current-voltage characteristics before and after forming recesses of a nitride-based semiconductor device.

As shown in FIG. 7, the maximum transconductance is 105.1 mS / mm in the prior art, whereas the maximum transconductance is reduced to 101.93 mS / mm in the present invention. In addition, in the case of the threshold voltage measured by the g _m max method, the conventional technique is -3.9V, whereas the present invention has a voltage shift of about 0.2V as -4.1V. By etched regions, the depletion regions of the present invention can easily access 2DEG on the same gate bias.

8 is a diagram illustrating a simulation of surface electric field characteristics.

8 is a diagram showing the results of a two-dimensional simulation of electric field relaxation using the ISE-TCAD software for the same structure as the nitride-based semiconductor device according to the present invention. The simulation results are shown in Table 1 below.

In the simulation, a recess was set to a depth of 20 nm in the barrier layer with a length corresponding to 10% of the length between the gate and drain electrodes for the recessed barrier layer. In consideration of the polarization effect, the density of the 2DEG may be changed under the recess region. If the depth of the recess is 20 nm, the surface electric field of the present invention is relaxed when applying reverse bias, and the maximum electric field strength is reduced as shown in FIG.

On the other hand, the above has been described with respect to specific embodiments of the present invention, of course, various modifications are possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the claims below, but also by those equivalent to the claims.

Claims (9)

A nitride based semiconductor layer comprising a barrier layer which is a nitride based semiconductor and a cap layer formed of GaN on an upper surface of the barrier layer;
A source electrode formed on one side of an upper surface of the nitride based semiconductor layer;
A drain electrode spaced apart from the source electrode on the other side of the nitride-based semiconductor layer; And
A gate electrode formed between the source electrode and the drain electrode on an upper surface of the nitride based semiconductor layer,
Between the gate electrode and the drain electrode, a recess is formed in the nitride based semiconductor layer below one side of the gate electrode,
And the depth of the recess is greater than the thickness of the cap layer and less than the sum of the thickness of the cap layer and the thickness of the barrier layer.
The method of claim 1,
The nitride-based semiconductor layer,
An insulating substrate;
A crystal nucleation layer formed on an upper surface of the substrate and formed to grow an epi structure of the first nitride semiconductor;
A buffer layer formed on an upper surface of the crystal nucleation layer, the buffer layer being the first nitride semiconductor; And
And a barrier layer formed on an upper surface of the buffer layer and forming a two-dimensional electron gas layer between the buffer layer and a second nitride semiconductor layer.
The method of claim 2,
The crystal nucleation layer is formed of AlN, the buffer layer is formed of GaN, the barrier layer is formed of AlGaN,
The nitride-based semiconductor device further comprises a cap layer formed of GaN on the upper surface of the barrier layer.
delete Forming a nitride based semiconductor layer including a barrier layer which is a nitride based semiconductor and a cap layer formed of GaN on an upper surface of the barrier layer;
Forming a source electrode on one side of an upper surface of the nitride based semiconductor layer;
Forming a drain electrode spaced apart from the source electrode on the other side of the upper surface of the nitride based semiconductor layer;
Forming a gate electrode on the upper surface of the nitride based semiconductor layer between the source electrode and the drain electrode; And
Forming a recess between the gate electrode and the drain electrode in the nitride based semiconductor layer below one side of the gate electrode,
The forming of the recess may include forming the recess such that the depth of the recess exceeds the thickness of the cap layer to be less than the sum of the thickness of the cap layer and the thickness of the barrier layer.
The method of claim 5,
Forming the nitride-based semiconductor layer,
Forming a crystal nucleation layer for growing an epi structure of the first nitride-based semiconductor on an insulating substrate;
Forming a buffer layer, which is the first nitride-based semiconductor, on the top surface of the crystal nucleation layer;
Forming a two-dimensional electron gas layer on the upper surface of the buffer layer between the buffer layer and forming a barrier layer which is a second nitride-based semiconductor; And
And forming a cap layer on the top surface of the barrier layer.
The method according to claim 5 or 6,
After forming the recess,
Nitride-based semiconductor device manufacturing method comprising the step of annealing oxygen.
The method of claim 6,
Wherein the crystal nucleation layer is formed of AlN, the buffer layer is formed of GaN, the barrier layer is formed of AlGaN, and the cap layer is formed of GaN.
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