KR101059625B1 - Wafer level chip scale package and its manufacturing method - Google Patents

Abstract

A wafer level chip scale package according to the present invention includes a semiconductor chip portion including a plurality of semiconductor chips separated by a scribing region at a wafer level, and an edge portion formed outside the semiconductor chip portion, It is characterized in that the alignment key formed by the provided, and provides a wafer level chip scale package and a method of manufacturing the wafer formed with the alignment key by a simple process.

Wafer, semiconductor chip, bonding pad, redistribution layer, identification mark, alignment key, resin sealing part, semiconductor chip part, corner part, laser

Description

Wafer level chip scale package and fabrication method of the same

The present invention relates to a wafer level chip scale package and a method of manufacturing the same, and more particularly, to a wafer level chip scale package and a method of manufacturing the wafer level chip scale package which can prevent a dicing error by providing an alignment key formed by a laser at a corner of the wafer. It is about.

The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more powerful and more reliable. One of the technologies enabling this is package technology, and thus, a type of package developed in recent years, a so-called wafer level chip using redistribution or rerouting of a bonding pad of a semiconductor chip. There is a Wafer Level Chip Scale Package (WLCSP).

In the wafer level chip scale package according to the related art, a plurality of semiconductor chips are scribed after performing a redistribution layer forming process and a connection terminal forming process at a wafer level before cutting to an individual chip level. It was prepared by dicing the boundary between. The wafer level chip scale package thus prepared was flip chip bonded onto a mother board, and then a resin encapsulation portion was formed by underfill between the mother substrate and the wafer level chip scale package.

However, the process of forming the resin encapsulation by the underfill as described above is low in productivity and high in manufacturing cost. In recent years, the resin encapsulation is formed in a batch at the wafer level, and a dicing process is performed to manufacture the wafer level chip scale package. As the resin sealing portion is formed before the dicing process, the boundary line between the scribing regions is obscured so that an additional alignment mark is formed at the edge of the wafer through the plating process to prevent the error of dicing.

However, when the alignment mark is formed at the edge of the wafer by the plating process, not only the process is complicated but also the manufacturing time and manufacturing cost increase as the plating is performed over a predetermined thickness.

Accordingly, the present invention has been made to solve the above problems, to provide a wafer-level chip scale package and a method of manufacturing the same, which can prevent dicing errors by providing an alignment key formed by a laser at the edge of the wafer. It is for.

A wafer level chip scale package according to a preferred embodiment of the present invention includes a semiconductor chip portion including a plurality of semiconductor chips separated by scribing regions at a wafer level, and an edge portion formed outside the semiconductor chip portion. The edge portion is characterized in that the alignment key formed by the laser is provided.

Here, the alignment key may be a step shape formed in the corner portion or a groove shape penetrating the corner portion.

Also, the semiconductor chip unit may include a semiconductor chip having a bonding pad formed on an upper surface thereof, an insulating layer formed on an upper surface of the semiconductor chip except for the bonding pad, and one end connected to the bonding pad on the insulating layer and a connection pad connected to the other end thereof. And a resin encapsulation portion formed to seal the redistribution layer and the insulating layer, including a redistribution layer having a connection terminal, a connection terminal formed on the connection pad, and the connection terminal.

In the method of manufacturing a wafer level chip scale package according to a preferred embodiment of the present invention, (A) forming an insulating layer having an opening for exposing a bonding pad on a semiconductor chip at the wafer level, (B) on the insulating layer Forming a redistribution layer having one end connected to the bonding pad and having a connection pad at the other end thereof, (C) forming a connection terminal at the connection pad, and (D) arranging an alignment key with a laser at an edge of the wafer. Forming, and (E) forming a resin encapsulation in the semiconductor chip portion, the steps (A), (B), (C), and (E) are performed sequentially, the (D) Step (E) is characterized in that it is carried out before or after any one of the steps before the step (E).

In this case, after the step (E), (F) further comprises the step of dicing the plurality of the semiconductor chip along the scribing region.

In addition, the alignment key may be a step shape formed in the corner portion or a groove shape penetrating the corner portion.

In the wafer level chip scale package according to the present invention, an alignment key formed by a laser is formed at the edge of the wafer where the resin seal is not formed, thereby reducing the dicing error.

In addition, the method of manufacturing a wafer level chip scale package according to the present invention can be performed by a simple process by forming an alignment key with a laser.

 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a wafer level chip size package according to a preferred embodiment of the present invention, FIG. 2 is a cross-sectional view of a wafer level chip size package according to a preferred embodiment of the present invention, and FIGS. 3 to 7 are preferred embodiments of the present invention. It is sectional drawing for each process for demonstrating the manufacturing method of the wafer level chip scale package which concerns on an Example.

1 and 2 are a plan view and a cross-sectional view of a wafer level chip scale package according to a preferred embodiment of the present invention. Referring to this, a wafer level chip scale package 100 according to a preferred embodiment of the present invention will be described below. same.

The wafer level package 100 according to the preferred embodiment of the present invention is formed outside the semiconductor chip portion A and the semiconductor chip portion A including a plurality of semiconductor chips separated by scribing regions at the wafer level. It characterized in that it comprises a corner portion (B) is formed by the alignment key 111 by the laser.

The semiconductor chip portion A is formed in the first wafer region 101a (see FIG. 3) of the wafer, and has a semiconductor chip 102, an insulating layer 105, a redistribution layer 107, a connection terminal 110, and a resin encapsulation. It characterized in that it comprises a part (112).

The semiconductor chip 101 has a bonding pad 103 electrically connected to the integrated circuit on an upper surface of a chip body of silicon material having an integrated circuit (not shown), and exposes the bonding pad 103 to the chip body. It has a structure in which the passivation layer 104 is formed on the top surface.

Here, the passivation layer 104 is composed of, for example, a thin insulating film, that is, a first insulating film (not shown) made of silicon dioxide (SiO 2), a second insulating film (not shown), and silicon nitride (SiN). It is comprised by the lamination of the 3rd insulating film (not shown) which becomes, and has high heat resistance and high electrical insulation. The surface of the passivation layer 103 serves as the surface of the semiconductor chip 101.

On the other hand, the bonding pad 102 is made of a metal such as aluminum.

The insulating layer 105 is used to protect the passivation layer 104 or the active surface of the semiconductor chip 102 from heat or mechanical stress generated during the regeneration process. The bonding pad 103 is formed on the upper surface of the semiconductor chip 102. ) Is formed to be exposed. Here, the insulating layer 105 is made of polyimide, epoxy, or the like.

The redistribution layer 107 is for guiding the wiring from the bonding pad 103 formed on the semiconductor chip 102 to a larger connection pad at another position, and extends from the bonding pad 103 on the insulating layer 105.

Here, one end of the redistribution layer 107 is connected to the bonding pad 103, and the other end of the redistribution layer 107 is formed with a connection pad 108 connected to a solder ball or an external connection terminal. In addition, the redistribution layer 107 is made of a conductive metal such as aluminum (Al), copper (Cu), nickel (Ni), and gold (Au).

The connection terminal 110 serves to serve as an electrically conductive connection terminal that connects the semiconductor chip 102 connected to the redistribution layer 107 to an external system or an external connection terminal or another solder ball. It is formed on the connection pad 108 of the wiring layer 107.

The resin encapsulation part 112 is to protect the layers formed on the semiconductor chip, and is formed to seal the redistribution layer 107 and the insulating layer 105 including the connection terminal 110.

Here, the resin encapsulation part 112 serves to maintain the shape of the connection terminal 110 as well as protecting the layer formed on the semiconductor chip, for example, the redistribution layer 107.

The corner portion B is formed on the outside of the semiconductor chip portion A, and is provided with an alignment key 111 formed by a laser, and the resin sealing portion 112 is not formed.

Here, the alignment key 111 has a step shape formed by processing the insulating layer 105 of the corner portion B with a laser or has a groove shape penetrating the corner portion B.

3 to 7 are cross-sectional views for each process for explaining a method of manufacturing a wafer level chip scale package according to a preferred embodiment of the present invention, with reference to this, of the wafer level package 100 according to a preferred embodiment of the present invention. The manufacturing method is as follows.

First, as shown in FIG. 3, the wafer 101 is prepared. The wafer 101 is manufactured through a conventional wafer manufacturing process, and includes a plurality of semiconductor chips 102 and a first wafer region 101a on which a scribing region S is formed, and the first wafer region 101a. It is divided into the 2nd wafer area | region 101b formed in the outer side.

At this time, the semiconductor chip 102 is formed with a bonding pad 103 electrically connected to the integrated circuit on the upper surface of the chip body of the silicon material in which the integrated circuit (not shown) is formed, so that the bonding pad 103 is exposed. The passivation layer 104 is formed on the upper surface of the chip body.

In addition, the scribing region S has a structure in which the passivation layer 104 is formed on the upper surface of the semiconductor chip 102 of silicon material, in which the integrated circuit is not embedded, and serves to distinguish neighboring semiconductor chips 102. do.

On the other hand, the second wafer region 101b has a structure in which a passivation layer 104 is formed on the upper surface of the semiconductor chip 102 of silicon material, in which the integrated circuit is not inherent, and the clamp is used when the wafer 101 is moved by a clamp or the like. It provides a place to be clamped by.

Next, as shown in FIG. 4, an insulating layer 105 having an opening 106 is formed on the passivation layer 104 so that the bonding pads 103 of the semiconductor chip 102 are exposed.

Here, the opening 106 is formed by forming a photosensitive resin layer on the insulating layer 105, and patterning the photosensitive resin layer so that a portion of the bonding pad 103 is exposed using photolithography technology. Of course, it is also within the scope of the present invention to form the openings 106 in other known ways.

Meanwhile, although the insulating layer 105 is formed in the entire wafer region in FIG. 4, the insulating layer 105 is formed on the second wafer region 101b (see FIG. 3) to facilitate formation of the alignment key. It will also be included that does not form within the scope of the present invention.

Next, as shown in FIG. 5, the redistribution layer 107 and the recognition mark 109 are formed.

In this case, the redistribution layer 107 is connected to the bonding pad 103 to extend on the insulating layer 105, and the connection pad 108 is formed on the extended portion. However, although FIG. 4 shows that the connection pad 108 is formed on the redistribution layer 107, the end of the redistribution layer 107 may function as a connection pad without a separate connection pad. will be.

In addition, the recognition mark 109 is formed on the insulating layer 105 in the scribing area S defined by the boundary line BL.

Next, as shown in FIG. 6, a connection terminal 110 for connecting the semiconductor chip 102 to an external system is formed on the connection pad 108, and the alignment key 111 is lasered at the edge of the wafer 101. Form.

In this case, the alignment key 111 may include a groove shape penetrating including the insulating layer 105 formed on the second wafer region 101a or a step shape formed in the insulating layer 105, which is an x and y table. It is desirable to be precisely processed through a laser facility using.

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Next, as shown in FIG. 7, the resin sealing part 112 is formed to seal the upper surface of the redistribution layer 107 including the connection terminal 110.

In this case, the resin encapsulation part 112 is not formed at the corner portion B on which the alignment key 111 is formed, but includes a plurality of semiconductor chips 102 and a scribing region S. Only formed. This is to prevent the alignment key 111 formed at the corner portion B from being blocked by the resin sealing portion 112.

In addition, the resin encapsulation unit 112 may be formed in any one selected from a printing method, a molding method, and a spin coating method, and may include an epoxy molding compound (EMC). It can be made of).

By this manufacturing process, the wafer level chip scale package 100 as shown in FIGS. 1 and 2 is manufactured.

Although the present invention has been described in detail through specific embodiments, this is for explaining the present invention in detail, and a wafer level chip scale package and a method of manufacturing the same according to the present invention are not limited thereto. It will be apparent to those skilled in the art that modifications and improvements are possible.

All simple modifications and variations of the present invention fall within the scope of the present invention, and the specific scope of protection of the present invention will be apparent from the appended claims.

1 is a plan view of a wafer level chip size package according to a preferred embodiment of the present invention.

2 is a cross-sectional view of a wafer level chip size package according to a preferred embodiment of the present invention.

3 to 7 are cross-sectional views of respective processes for explaining a method of manufacturing a wafer level chip scale package according to a preferred embodiment of the present invention.

<Description of main parts of drawing>

101: wafer 102: semiconductor chip

103: bonding pad 105: insulating layer

107: redistribution layer 109: recognition mark

110: connection terminal 111: alignment key

112: resin sealing portion A: semiconductor chip portion

B: corner S: scribing area

Claims (6)

delete delete delete (A) forming an insulating layer having an opening in the passivation layer to expose the bonding pads of the semiconductor chip at the wafer level; (B) forming a redistribution layer having one end connected to the bonding pad and having a connection pad at the other end on the insulating layer; (C) forming a connection terminal on the connection pad, (D) forming an alignment key with a laser at an edge of the wafer; And (E) forming a resin sealing portion to seal the upper surface of the redistribution layer without forming the corner portion; Method of manufacturing a wafer level chip scale package comprising a. The method according to claim 4, After step (E), (F) dicing a plurality of said semiconductor chips along a scribing region. The method according to claim 4, The alignment key is a wafer level chip scale package manufacturing method, characterized in that the step shape formed in the corner portion or the groove shape penetrating the corner portion.

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