CN104051429B - Method and apparatus for wafer-level packaging - Google Patents

Abstract

The invention discloses the method and apparatus for wafer-level packaging; one of which semiconductor device, including: substrate, the bond pad above substrate, the protection ring above substrate, between bond pad and protection ring, it is positioned at the alignment mark above substrate.This device interconnects (PPI) layer and the connector being positioned in PPI layer after can including the passivation that the passivation layer being positioned on substrate, polymeric layer contact with bond pad; wherein connector is between bond pad and protection ring, and alignment mark is between connector and protection ring.Alignment mark may be located in PPI layer.Can have multiple alignment mark in the different layers.Can be at the multiple alignment marks that be there is device by the adjacent corner in the region of protection ring cincture or edge.

Description

Method and apparatus for wafer level packaging

Related Application Cross Reference

This application claims priority to U.S. Provisional Patent Application No. 61/776,629, entitled "Methods and Apparatus for Wafer Level Packaging," filed March 11, 2013, the entire contents of which are incorporated herein by reference.

technical field

The present invention relates generally to integrated circuits and, more particularly, to methods and apparatus for wafer level packaging.

Background technique

Since the invention of the integrated circuit (IC), the semiconductor industry has experienced rapid development due to the continuous increase in the integration density of various electronic components. To a large extent, this increase in integration density stems from the continuous shrinking of the minimum feature size, which allows more components to be integrated into a given area. As the demand for smaller electronic devices increases, so does the need for smaller and more innovative packaging techniques for semiconductor die.

Traditional packaging techniques divide the wafer into individual dies and package each individual die, and then place the single die on the packaging substrate, usually by wire bonding or flip chip to form the first level of interconnection, packaging , test, verify, and form second-level interconnects to the board in the final assembly. These techniques and processes are time-consuming.

Wafer-level packaging (WLP) technology is a technology for packaging dies at the wafer level. WLP technology can produce dies with small size and good electrical performance, and is currently widely used due to its low cost and relatively simple process. WLP technology basically extends the wafer manufacturing process to include device interconnection and device protection processes. In WLP technology, the back-end-of-line (BEOL) process involves some masking layers, redistribution layers, under-bump metallization layers and wafer bumps starting from the polymer dielectric layer before dicing. Packaging is also sometimes performed at the wafer level before dicing the entire wafer in the dicing process.

Dicing is the process of separating the die from the wafer. The cutting process can be done by scoring and severing, mechanical sawing (often by a machine called a dicing saw), or laser cutting. In WLP technology, encapsulation materials such as molding compounds can cover the scribe lines of the wafer and reduce the accuracy of die dicing. There is a need for methods and apparatus for improving die sawing accuracy for WLP packaging in a die sawing process.

Contents of the invention

According to one aspect of the present invention, a semiconductor device is provided, including: a substrate; a first bonding pad positioned above the substrate; a guard ring positioned above the substrate; a first alignment mark positioned on the first bonding pad and guard ring above the substrate.

Preferably, the shape of the first alignment mark is selected from the group consisting essentially of a circle, a square, a rhombus, an L shape or a hollow shape.

Preferably, the first alignment mark is on the same layer as the first bonding pad above the substrate.

Preferably, the device further comprises: a passivation layer on the substrate covering a first portion of the first bonding pad while exposing a second portion of the first bonding pad; a first polymer layer on the passivation layer and partially exposing the first bonding pad; a post-passivation interconnect (PPI) layer over the first polymer layer and in contact with the first bonding pad; and wherein the first alignment mark is over the first polymer layer in the PPI layer.

Preferably, the device further comprises a second alignment mark at a different layer from the PPI layer.

Preferably, the device further includes: a connector on the PPI layer, the connector is located between the first bonding pad and the guard ring, and the first alignment mark is located between the connector and the guard ring.

Preferably, the device further comprises: a second polymer layer on the first polymer layer and on the PPI layer, the second polymer layer having an opening to expose the PPI layer; an under bump metallization (UBM) layer on the first polymer layer On the second polymer layer, covering the opening of the second polymer layer and electrically connected to the PPI layer; and a connector, located on the UBM layer, the connector is located between the first bonding pad and the guard ring, and the first alignment mark Located between the connector and the guard ring.

Preferably, the device further includes: a second bonding pad located above the substrate, the first bonding pad and the second bonding pad are located in an area surrounded by the guard ring; and a second alignment mark on the second bonding pad Between the pad and the guard ring is on the substrate.

Preferably, the first alignment mark is located at a corner of the area surrounded by the guard ring, and the first bonding pad is located within the area.

Preferably, the first alignment mark is close to an edge of the area surrounded by the guard ring, and the first bonding pad is located within the area.

According to another aspect of the present invention, there is provided a method of forming a packaged device, comprising: providing a wafer having a substrate; forming a first device, the first device comprising: a plurality of first bond pads positioned over the substrate , a guard ring surrounding the plurality of first bonding pads located above the substrate, a plurality of first alignment marks located above the substrate between the plurality of first bonding pads and the guard ring; placing the first connector on Over the first bonding pad and electrically connecting the first connector to the first bonding pad, the connector is located between the first alignment mark of the first device and the first bonding pad; and forming a molding compound layer, the molding compound A layer covers the first bond pad, the first alignment mark and the connector.

Preferably, the first device further includes: a second bonding pad located above the substrate, and the first bonding pad and the second bonding pad are located in an area surrounded by the guard ring; a second alignment mark located on the second bonding pad Between the pad and the guard ring is on the substrate. The method further includes placing a second connector over the second bonding pad and electrically connecting the second connector to the second bonding pad, wherein the second connector is located between the second alignment mark and the second bonding pad. between; and forming a molding compound layer to cover the first alignment mark, the second alignment mark, the first connector and the second connector.

According to still another aspect of the present invention, a semiconductor device is provided, comprising: a substrate; a first bonding pad located above the substrate; a guard ring located above the substrate; a passivation layer located on the substrate covering the first A portion of a bond pad while exposing the first bond pad; a first polymer layer on the passivation layer and partially exposing the first bond pad; a post-passivation interconnect (PPI) layer on the first polymer layer over and in contact with the first bond pad; and a first alignment mark over the substrate between the first bond pad and the guard ring.

Preferably, the first alignment mark is located in the PPI layer above the first polymer layer.

Preferably, the device further includes: a second alignment mark on a different layer from the first alignment mark.

Preferably, the device further includes: a connecting piece located on the PPI layer, the connecting piece is located between the first bonding pad and the guard ring, and the first alignment mark is located between the connecting piece and the guard ring.

Preferably, the device further comprises: a second polymer layer on the first polymer layer and on the PPI layer, the second polymer layer having an opening to expose the PPI layer; an under bump metallization (UBM) layer on the first polymer layer Above the second polymer layer, covering the opening of the second polymer layer and electrically connected to the PPI layer; and a connector, located on the UBM layer, the connector is located between the first bonding pad and the guard ring, and the first alignment mark is located Between the connector and the protection ring.

According to yet another aspect of the present invention, there is provided a method of forming a packaged device, comprising: receiving a substrate having a plurality of dies, each of the plurality of dies having a guard ring and located at a position surrounded by the guard ring. alignment marks within the area of the alignment marks; aligning the dicing saw with reference to the alignment marks; and dicing the substrate to separate the plurality of dies.

Preferably, the substrate with the plurality of dies is covered by a molding compound; and the alignment marks are aligned with the dicing saw through the molding compound.

Preferably, the method further comprises: each of the plurality of dies having a second alignment mark located within an area surrounded by the guard ring; aligning the dicing saw with reference to the alignment mark and the second alignment mark; and The substrate is diced to separate the dies.

Description of drawings

For a fuller understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

1( a ) and FIG. 1( b ) illustrate top views of a wafer level package (WLP) including a plurality of dies covered by molding compound, according to some embodiments;

2(a) to 2(e) illustrate cross-sectional views of alignment marks on dies for assisting in dicing of WLP packages, according to some embodiments;

3(a) to 3(e) illustrate top views of a plurality of alignment marks on a die according to some embodiments; and

4( a ) to 4( d ) illustrate a process of forming a wafer level package (WLP) with on-die alignment marks, according to some embodiments.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate relevant aspects of the various embodiments and are not necessarily drawn to scale.

detailed description

The making and using of embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments of the present invention provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative specific ways to make and use the embodiments, and do not limit the scope of the embodiments.

The making and using of the Examples are discussed in detail below. A semiconductor device includes: a substrate, a bond pad over the substrate, a guard ring over the substrate, and an alignment mark over the substrate between the bond pad and the guard ring. The device may further include a passivation layer on the substrate, a polymer layer on the passivation layer, a post-passivation interconnect (PPI) layer on the polymer layer and in contact with the bond pad, and a post-passivation interconnect (PPI) layer on the PPI layer. , where the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. Alignment marks may be located in the PPI layer above the polymer layer. There can be multiple alignment marks on different layers. There may be multiple alignment marks for the device around the corners and at the edges of the area surrounded by the guard ring. Alignment marks can be used to improve accuracy during a sawing process that separates dies from wafer level packages (WLPs).

In the following description, embodiments of the invention are disclosed under the condition that contacts for metal gate transistors are formed so that the metal gate has less resistance. The device may include an active region including a source, a drain, and a channel between the source and drain, an isolation region surrounding the active region, a metal gate over the isolation region and over the channel, wherein the metal gate The pole includes a conductive layer. The device further includes a contact, wherein the contact includes a first contact portion formed in the conductive layer of the metal gate over the isolation region that does not vertically overlap the active region, and over the first contact portion connected to the first contact portion. The contact portion is substantially vertically contained within the second contact portion within the first contact portion. The resistance of the metal gate is reduced due to the removal of a larger portion of the conductive layer of the metal gate to form a larger first contact portion.

It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, this element or layer can be directly on the other element or layer. A layer may be present on or connected or coupled to other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present.

It should be understood that although the terms "first", "second", "third" etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

Spatially relative terms such as "under", "beneath", "under", "above", "on", etc. may be used herein for convenience to describe an element or component as shown in the drawings A relationship to another (or other) elements or parts. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "above" or "beneath" can encompass both an orientation of "above" and "below". The device may be orientated in other orientations (rotated 90 degrees or at other orientations), and spatially relative terms used herein are interpreted accordingly.

The terms used herein are for describing particular example embodiments only and are not intended to limit the inventive concept of the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should be further understood that when the terms "comprising" and/or "comprises" are used in this specification, it specifically indicates the presence of listed components, integers, steps, operations, elements and/or components, but does not exclude one or more other components. , integers, steps, operations, elements, parts and/or groups exist or add.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular component, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one implementation" or "in an embodiment" in various places in this specification are not necessarily referring to the same embodiment. Furthermore, the particular components, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that the drawings described below are not drawn to scale; instead, these drawings are for illustration purposes only.

FIG. 1( a ) illustrates a top view of a wafer level package (WLP) including a plurality of dies 11 fabricated on a wafer 20 and covered by a molding compound 52 , according to some embodiments. Figure 1(b) shows more details of the die 11 and its surrounding area.

FIG. 1( a ) shows a WLP package 25 . WLP package 25 may be Wafer Level Chip Scale Package (WLCSP), Fan Out Wafer Level Package (FO-WLP), Embedded Wafer Level Package (Embedded WLP), 3D Wafer Level Package (3DWLP) or wafer-level MEMS (WLP MEMS). The WLP package 25 may be any other WLP package developed in various other technologies and used in various applications.

Die 11 may be formed by various technologies such as CMOS chip, GaAs chip, SiGe chip or integrated passive device (IPD). Die 11 may be used for any function, such as a processor, a memory chip, a power amplifier, an optoelectronic device such as an image sensor, or an A/D converter.

Package 25 includes a plurality of dies 11 formed on wafer 20 and separated by scribe lines 37 . Wafer 20 serves as a fabrication carrier during production of dies. After the semiconductor fabrication process, a plurality of dies 11 are formed. These dies 11 are then separated by a die dicing or singulation process, typically using mechanical dicing or laser dicing to cut the wafer between the individual dies 11 . In order to facilitate the die dicing process, a relatively narrow sacrificial scribe line 37 is provided on the wafer 20 , along which dicing is performed to separate the die 11 . Scribe line 37 is the area between the two dies. Scribe 37 may include a number of test pads (not shown) for testing purposes. FIG. 1( b ) shows the die 11 and the scribe line 37 surrounding the die 11 .

Molding compound 52 covers the top of die 11 and scribe lines 37 . In one embodiment, molding compound 52 may be a non-conductive material such as epoxy, resin, moldable polymer, or the like. Molding compound 52 may be formed to provide lateral support for structures formed on die 11 , such as connectors. Molding or molding molding compound 52 may be used. A release agent may optionally be applied to the mold to prevent the molding compound 52 from adhering to the mold.

Figure 1(b) shows more details of the die 11 and its surrounding area. As shown in FIG. 1( b ), the scribe line 37 surrounds the die 11 , wherein the scribe line 37 is located outside the edge of the die 11 . Die 11 includes guard ring 34 . A plurality of bond pads 32 are located within the area surrounded by guard ring 34 . Bond pad 32 surrounds active region 12 . Alignment marks 36 may be located between bond pad 32 and guard ring 34 . There may be multiple alignment marks (not shown).

As shown in FIG. 1( b ), a guard ring 34 surrounds the die 11 . Guard ring 34 may generally be formed of a conductive material similar to bond pad 32 , such as aluminum (Al), aluminum-copper (Al-Cu) alloy, or aluminum-copper-silicon (Al-Cu-Si) alloy. Guard ring 34 is placed outside bond pad 32 and protects die 11 . The protective ring 34 may also be referred to as a sealing ring. In some embodiments, guard ring 34 may have an edge-to-edge dimension of about 10 μm.

Active region 12 may be composed of millions of components, such as active and passive devices on the substrate. Active region 12 includes most of the high-density active circuitry of die 11 . These components formed on the underlying substrate may be initially isolated from each other and then interconnected together by metal interconnect lines to form functional circuits. Typical interconnect structures include lateral interconnects, such as metal lines or wires, and vertical interconnects, such as vias and contacts. The side of the substrate on which the devices are formed may be referred to as the top side of the die.

Bond pads 32 may be used to provide voltage signals to circuitry within active region 12 . These voltage signals are provided to bond pads 32 through the package to which integrated circuit device 11 is attached. Generally, after fabrication of the device, the bond pads 32 lie beneath the dielectric layer and must be exposed for testing and bonding to a suitable package. Depending on the function of the semiconductor device, electrical signals from the active region 12 are routed through the network of metal layers to one or more bond pads 32 , and the bond pads 32 are further connected to solder bumps or other connections.

Alignment mark 36 is located between bond pad 32 and guard ring 34 . A plurality of alignment marks (not shown) may be formed. Alignment marks 36 may be formed at the same layer as bond pads 32 and over a substrate (not shown). Alignment marks 36 may be used to improve accuracy during the sawing process of separating die 11 from WLP 25 . In WLP technology, the molding compound 52 shown in FIG. 1( a ) may cover the scribe line 37 and reduce the accuracy of die cutting. The use of alignment marks 36 can improve the accuracy of die cutting of WLP package 25 . Alignment marks 36 may not be functional blocks of die 11 for performing any function of die 11 . Instead, alignment marks 36 may be formed to aid in die dicing and be electrically isolated from any other functional blocks of die 11 .

2( a ) to 2( e ) illustrate cross-sectional views of alignment marks 36 on die 11 between bond pad 32 and guard ring 34 , according to some embodiments. 2(a) to 2(e) may be cross-sectional views taken along line C-C' of FIG. 1(b), in which only one bonding pad 32 is shown. A plurality of alignment marks 36 (to be shown in FIGS. 3( a ) to 3 ( e )) may be formed on the die 11 .

As shown in FIGS. 2( a ) to 2 ( c ), die 11 includes bond pads 32 and guard rings 34 formed on substrate 30 . Alignment marks 36 are formed over substrate 30 between bond pad 32 and guard ring 34 . Devices such as active devices and passive devices 301 may be formed within substrate 30 . Die 11 further includes a passivation layer 40 on substrate 30 that covers a portion of bond pad 32 while exposing bond pad 32 . Die 11 further includes polymer layer 45 on passivation layer 40 and partially exposing bond pad 32 . Die 11 further includes a post-passivation interconnect (PPI) layer 47 over polymer layer 45 and in contact with bond pad 32 . Die 11 further includes a connection 49 on PPI layer 47 , wherein connection 49 is located between bond pad 32 and guard ring 34 , and alignment mark 36 is located between connection 49 and guard ring 34 . Further details of each element are given below.

Substrate 30 may comprise doped or undoped bulk silicon, or an active layer of a silicon-on-insulator (SOI) substrate. In general, SOI substrates include layers of semiconductor materials such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used for substrate 30 include multilayer substrates, gradient substrates, or hybrid orientation substrates.

Devices such as active devices and passive devices 301 may be formed on substrate 30 . Those skilled in the art will recognize that various active and passive devices such as capacitors, resistors, inductors, etc. may be used to form the desired structural and functional requirements for the design of die 11 . Device 301 may be formed in substrate 30 or on a surface of the substrate using any suitable method.

Multiple metallization layers (not shown) may be formed over substrate 30 and device 301 and are designed to connect device 301 to form functional circuitry. The metallization layers may be formed from alternating layers of dielectric and conductive material, such as copper, and may be formed by any suitable process, such as deposition, damascene, dual damascene, etc.

Bond pad 32 may be formed over device 301 and electrically connected to device 301 through a metallization layer. Bond pad 32 may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other conductive material. Bond pads 32 may be formed by forming a layer of material (not shown), which may be formed using a deposition process such as sputtering, and then removing portions of this material layer by a suitable process such as photolithographic masking and etching to form bond pads. Disk 32. However, any other suitable method may be used to form bond pad 32 . The bond pad 32 may be formed to have a thickness between about 0.5 μm to about 4 μm, such as 1.45 μm. The size, shape and location of bond pads 32 are for illustration purposes only and not for limitation. The multiple bond pads 32 (not shown) may have the same size or different sizes.

A passivation layer 40 is formed over the surface of the substrate 30 and on top of the bond pads 32 for structural support and physical isolation. In some embodiments, passivation layer 40 stops before guard ring 34 as shown in FIGS. 2( a ) to 2( c ). In some alternative embodiments, passivation layer 40 may be formed over guard ring 34 and the active region but not over scribe line 37 . Can be made of silicon nitride (SiN), silicon dioxide (SiO ₂ ), silicon oxynitride (SiON), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO) or Other insulating materials form passivation layer 40 . The opening of passivation layer 40 may be formed by removing a portion of passivation layer 40 using a mask-defined photoresist etch process, thereby exposing bond pad 32 . The size, shape and location of the openings are for illustration purposes only and not for limitation. As shown in FIGS. 2( a ) to 2 ( c ), it is preferable to expose part of the top surface of the bonding pad 32 .

A polymer layer 45 is formed over the passivation layer 40 and over the opening of the passivation layer 40 to cover the bond pad 32 . In some embodiments, polymer layer 45 is stopped before guard ring 34 as shown in FIGS. 2( a ) to 2( c ). In some alternative embodiments, polymer layer 45 may be formed over guard ring 34 and the active region but not over scribe line 37 . Polymer layer 45 may be formed from polymers such as epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), etc., although other relatively soft, usually organic, materials may also be used. dielectric material. Forming methods include spin coating or other commonly used methods. The thickness of polymer layer 45 is preferably between about 5 μm and about 30 μm. Dimensions recited throughout this specification are examples only and will vary as integrated circuits are scaled down.

A post-passivation interconnect (PPI) layer 47 is formed over polymer layer 45 and contacts bond pad 32 . The PPI layer 47 may also be called a redistribution layer. PPI layer 47 may be formed from alternating layers of dielectric and conductive materials, and may be formed by any suitable process, such as deposition, damascene, dual damascene, etc. The PPI layer 47 may be formed of, for example, Al, Cu, or a Cu alloy. The PPI layer 47 can be formed by electroplating, sputtering, PVD or electroless plating process. Depending on the functionality of die 11 , die 11 may include a plurality of PPI layers 47 to form an interlayer interconnect network that may be electrically connected to bond pads 32 .

Connectors 49 are formed and brought into contact with the PPI layer 47 . Connectors 49 may be solder bumps, solder balls, or any other similar connection devices that effect an electrical connection between two objects. Any of those connecting devices may simply be referred to as a connector. Connector 49 may be a solder ball including an alloy of tin, lead, silver, copper, nickel, bismuth, or the like. Alternatively, the connectors 49 may be copper bumps formed by, for example, plating, printing, or the like. Connector 49 is located between bond pad 32 and guard ring 34 , and alignment mark 36 is located between connector 49 and guard ring 34 .

Alignment marks 36 are located above substrate 30 and between bond pads 32 and guard ring 34 . Connector 49 is located between bond pad 32 and alignment mark 36 . Alignment marks 36 may be located at various layers of die 11 , such as passivation layer 40 or PPI layer 47 . As shown in FIG. 2( a ), the alignment mark 36 may be at the same layer as the bond pad 32 covered by a passivation layer 40 which is further covered by a polymer layer 45 . Optionally, as shown in FIG. 2( b ), the alignment mark 36 may be at the same layer as the PPI layer 47 above the polymer layer 45 . There may be multiple alignment marks in multiple layers. In the embodiment shown in FIG. 2( c ), the first alignment mark 361 is at the same layer as the bonding pad 32 covered by the passivation layer 40 . The second alignment mark 363 is located on the PPI layer 47 . The first alignment mark 361 and the second alignment mark 363 may be at different positions in the longitudinal direction.

FIG. 2( d ) shows an alternative embodiment of die 11 with alignment marks 36 located between bond pads 32 and guard ring 34 . As shown in FIG. 2( d ), in addition to the layers shown in FIGS. 2( a ) to 2 ( c ), the die 11 further includes a second polymer layer 46 covering the PPI layer 47 and the first polymer layer 45 , The second polymer layer 46 has openings to expose the PPI layer 47 . An under bump metal (UBM) layer 43 overlies the second polymer layer 46 , covers the opening of the second polymer layer 46 , and may be electrically connected to the PPI layer 47 , which is further connected to the bond pad 32 . Connectors 49 are placed on the UBM layer 43 . Connector 49 is located between bond pad 32 and guard ring 34 , and alignment mark 36 is located between connector 49 and guard ring 34 . Alignment marks 36 are on the same layer as PPI layer 47 . The second polymer layer 46 further covers the alignment marks 36 . More details of each component are basically the same as described in Fig. 2(a) to 2(c).

As shown in FIG. 2( d ), the UBM layer 43 may be formed around the opening of the second polymer layer 46 . UBM layer 43 may be formed of copper or copper alloys, which may include silver, chromium, nickel, tin, gold, and combinations thereof. Additional layers such as nickel layers, lead-free pre-solder layers, or combinations thereof may be formed over the copper layer. The UBM layer 43 may have a thickness between about 1 μm and 20 μm.

FIG. 2( e ) shows an embodiment of placing a molding compound layer 52 on the die 11 shown in FIG. 2( d ). Molding compound 52 covers second polymer layer 46 , UBM layer 43 , connectors 49 , alignment marks 36 , guard ring 34 and scribe line 37 . In one embodiment, molding compound 52 may be a non-conductive material such as epoxy, resin, moldable polymer, or the like. Molding compound 52 may be formed to provide lateral support for structures formed on die 11 , such as connectors. A mold may be used to shape or mold the molding compound 52 . A release agent may optionally be applied to the mold to prevent the molding compound 52 from adhering to the mold. Similarly, a molding compound layer 52 may be placed on the die 11 shown in FIGS. 2( a ) to 2 ( c ).

3( a ) to 3( b ) show top views of multiple alignment marks 36 on die 11 according to some embodiments, while FIGS. 2( a ) to 2( e ) show only one bond pad Disk 32.

As shown in FIG. 3( a ), a plurality of alignment marks 36 are formed near the corners of the area surrounded by the guard ring 34 . A plurality of connectors 49 are further placed in this area. The alignment mark 36 is located between the connector 49 and the guard ring 34 . As shown in FIGS. 2( a ) to 2 ( e ), connectors 49 may be connected to the bonding pads through the PPI layer and the UBM layer.

As shown in FIG. 3( b ), a plurality of alignment marks 38 are formed near the edge of the area surrounded by the guard ring 34 . A plurality of connectors 49 are further placed in this area. The alignment mark 38 is located between the connector 49 and the guard ring 34 . As shown in FIGS. 2( a ) to 2 ( e ), connectors 49 may be connected to the bonding pads through the PPI layer and the UBM layer.

As shown in FIG. 3( c ), the alignment mark 36 may be at a distance Q from the edge of the guard ring. The distance Q may be in the range of about 80 μm to about 100 μm. The connector 49 may be at a distance P from the alignment mark 36 . The distance P may be in the range of about 80 μm to about 120 μm.

As shown in FIGS. 3( d ) to 3 ( e ), the alignment mark 36 may have various shapes. As shown in FIG. 3( d ), the alignment mark 36 may be "L" shaped. The length of the top side of the alignment mark 36 is W3, the length of the bottom side is W2, the height of the long side is W1, and the height of the short side is W4. The length W3 may be in the range of about 10 μm to about 15 μm. The length W2 may be in the range of about 20 μm to about 25 μm. The height W1 may be in the range of about 20 μm to about 25 μm. The height W4 may be in the range of about 2 μm to about 5 μm.

As shown in FIG. 3( e ), the alignment mark 36 may have a hollow shape. The outer shape of the alignment mark 36 may be a rectangle with a width W1 and a length W2. The hollow part may be a square with side length W3. The width W2 and the length W1 may be in a range of about 20 μm to about 25 μm. The length W3 may be in the range of about 10 μm to about 15 μm. Dimensions and shapes are for illustrative purposes only and not limitations. For example, alignment marks 36 may be square, circular, rectangular, diamond, and many other types of shapes and sizes.

4( a ) to 4( d ) illustrate a process of forming a wafer level package (WLP) with alignment marks on a die, according to some embodiments.

As shown in FIG. 4( a ), a wafer comprising dies 11 is provided. Die 11 includes substrate 30 , bond pads 32 over substrate 30 , guard ring 34 over substrate 30 . Alignment marks 36 are located above substrate 30 and between bond pad 32 and guard ring 34 . The die 11 may be any one of the die 11 shown in FIGS. 2( a ) to 2 ( d ). Die 11 may further include a passivation layer 40 on substrate 30, a polymer layer 45 on passivation layer 40, a post-passivation interconnect (PPI) over polymer layer 45 and in contact with bond pad 32. ) layer 47. Alignment marks 36 may be located at PPI layer 47 over polymer layer 45 .

As shown in FIG. 4(b), the connector 49 is placed over the bonding pad 32 and electrically connected to the bonding pad 32 through the PPI layer 47, wherein the connector 49 is located between the alignment mark 36 and the bonding pad. Between 32. After the dies 11 have been prepared over the wafer, the connectors 49 can be placed in a bumping process for the wafer.

As shown in FIG. 4( c ), a molding compound layer 52 is formed to cover the second polymer layer 46 , the UBM layer 43 , the connector 49 , the alignment mark 36 , the guard ring 34 and the scribe line 37 . In one embodiment, molding compound 52 may be a non-conductive material such as epoxy, resin, moldable polymer, or the like. Molding compound 52 may be formed to provide lateral support for structures formed on die 11 , such as connectors. A mold may be used to shape or mold the molding compound 52 . A release agent may optionally be applied to the mold to prevent the molding compound 52 from adhering to the mold.

FIG. 4( d ) shows an embodiment in which a plurality of alignment marks 36 are formed on the die 11 covered by the molding compound 52 . Die 11 includes a plurality of bond pads connected to a plurality of connectors 49 placed in the area surrounded by guard ring 34 . A plurality of alignment marks 36 are formed on the substrate between the connector 49 and the guard ring 34 . A molding compound layer 52 is formed to cover the alignment mark 36 , the connector 49 , the guard ring 34 and the scribe line 37 .

As shown in FIG. 4( d ), dicing is a process for cutting a wafer containing dies 11 . The dicing process separates the die 11 from the wafer. The cutting process can be done by scoring and cutting off, by mechanical sawing (often by a machine called a dicing saw), or by laser cutting. The molding compound 52 may be transparent so that the alignment marks 36 are visible from above the molding compound 52 . Alignment marks 36 formed on the same layer as the bond pads or PPI layer are closer to the surface of die 11 and are thus easier to see. Alternatively, some other technique, such as a laser, can be used to detect the position of the alignment marks 36, which will be used as reference points for dicing the wafer. Alignment marks 36 and other alignment marks formed in other regions at different times may be used to further improve the accuracy of the alignment.

Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As a person of ordinary skill in the art, according to the present invention, it should be easy to understand that according to the present invention, existing or future developed devices can be used to perform substantially the same functions as the corresponding embodiments described herein or to obtain substantially the same results. process, machine, manufacture, composition of matter, means, method or steps. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (19)

1. A semiconductor device, comprising: Substrate; a first bonding pad located over the substrate; a passivation layer on the substrate covering a first portion of the first bond pad while exposing a second portion of the first bond pad; a guard ring over the substrate; A first alignment mark is located over the substrate between the first bond pad and the guard ring. 2. The device of claim 1, wherein a shape of the first alignment mark is selected from the group consisting of a circle, a square, a rhombus, an L shape, or a hollow shape. 3. The device of claim 1, further comprising: a first polymer layer on the passivation layer and partially exposing the first bond pad; a post-passivation interconnect layer overlying the first polymer layer and in contact with the first bond pad; and Wherein, the first alignment mark is on the same layer as the first bonding pad above the substrate. 4. The device of claim 3, further comprising a second alignment mark at a different layer than the post-passivation interconnect layer. 5. The device of claim 3, further comprising: a connector on the post-passivation interconnection layer, the connector is located between the first bonding pad and the guard ring, and the first alignment mark is located between the connector and the between the protection rings. 6. The device of claim 3, further comprising: a second polymer layer on the first polymer layer and on the post-passivation interconnect layer, the second polymer layer having openings to expose the post-passivation interconnect layer; an under bump metallization layer on the second polymer layer, covering the opening of the second polymer layer and electrically connected to the post-passivation interconnect layer; and a connector on the UBM layer, the connector is located between the first bonding pad and the guard ring, and the first alignment mark is located between the connector and the between the protection rings. 7. The device of claim 1, further comprising: a second bond pad located above the substrate, the first bond pad and the second bond pad located within an area surrounded by the guard ring; and A second alignment mark is on the substrate between the second bond pad and the guard ring. 8. The device of claim 1, wherein the first alignment mark is located at a corner of an area surrounded by the guard ring, and the first bonding pad is located within the area. 9. The device of claim 1, wherein the first alignment mark is near an edge of an area surrounded by the guard ring, and the first bonding pad is located within the area. 10. A method of forming a packaged device comprising: providing a wafer with a substrate; forming a first device, the first device comprising: a plurality of first bonding pads located over the substrate; a guard ring surrounding the plurality of first bond pads over the substrate; a plurality of first alignment marks over the substrate between the first plurality of bond pads and the guard ring; placing a first connector over and electrically connecting the first connector to the first bond pad, the connector being located on the first pair of the first device between the alignment mark and the first bonding pad; and A molding compound layer is formed, the molding compound layer covering the first bonding pad, the first alignment mark and the connector. 11. The method of claim 10, further comprising: The first device further includes: a second bond pad located above the substrate, the first bond pad and the second bond pad located within an area surrounded by the guard ring; a second alignment mark on the substrate between the second bond pad and the guard ring; placing a second connector over and electrically connecting the second connector to the second bond pad, wherein the second connector is located between the second alignment mark and between the second bonding pads; and The molding compound layer is formed to cover the first alignment mark, the second alignment mark, the first connector, and the second connector. 12. A semiconductor device comprising: Substrate; a first bonding pad located over the substrate; a guard ring over the substrate; a passivation layer on the substrate covering a portion of the first bonding pad while exposing the first bonding pad; a first polymer layer on the passivation layer and partially exposing the first bond pad; a post-passivation interconnect layer overlying the first polymer layer and in contact with the first bond pad; and A first alignment mark is located over the substrate between the first bond pad and the guard ring. 13. The device of claim 12, wherein the first alignment mark is located in the post-passivation interconnect layer above the first polymer layer. 14. The device of claim 12, further comprising: a second alignment mark at a different layer from the first alignment mark. 15. The device of claim 12, further comprising: a connecting piece located on the passivated interconnection layer, the connecting piece is located between the first bonding pad and the guard ring, the first alignment mark is located between the connecting piece and the guard ring between rings. 16. The device of claim 12, further comprising: a second polymer layer on the first polymer layer and on the post-passivation interconnect layer, the second polymer layer having openings to expose the post-passivation interconnect layer; an under bump metallization layer overlying the second polymer layer, covering the opening of the second polymer layer and electrically connected to the post-passivation interconnect layer; and a connecting piece located on the UBM layer, the connecting piece is located between the first bonding pad and the guard ring, the first alignment mark is located between the connecting piece and the guard ring between rings. 17. A method of forming a packaged device comprising: receiving a substrate having a plurality of dies each having a guard ring and alignment marks in an area surrounded by the guard ring, wherein the substrate is disposed over There is a first bond pad, and a passivation layer is on the substrate and covers a first portion of the first bond pad while exposing a second portion of the first bond pad; aligning the dicing saw with reference to the alignment marks; and The substrate is diced to separate the plurality of dies. 18. The method of claim 17, wherein, the substrate having the plurality of dies is covered by a molding compound; and The alignment mark is aligned with the dicing saw by the molding compound. 19. The method of claim 17, further comprising: each of the plurality of dies has a second alignment mark located within an area surrounded by the guard ring; aligning the dicing saw with reference to the alignment mark and the second alignment mark; and The substrate is diced to separate the dies.