KR101050142B1 - Method for manufacturing nanowire multichannel FET device - Google Patents

Abstract

The present invention relates to a method for manufacturing a nanowire multichannel FET device, and to overcome the limitations of existing nanomaterial FET devices, a nanowire multichannel FET device that simultaneously realizes high current transfer capability and fast charge mobility can be mass-produced at low cost. It relates to a manufacturing method that can be. The present invention provides a method of manufacturing a nanowire multichannel FET device, comprising: forming a V groove nanowire array on a substrate or a thin film on the substrate through photolithography and wet etching processes; Self-assembling nanomaterials into the V grooves of the V groove nanowire array through a solution process; And manufacturing a multichannel FET device using the V groove nanowire array in which the nanomaterial is self-assembled.

Nanomaterials, nanotubes, nanowires, V-grooves, nanowire arrays, multichannels, photolithography, wet etching, solution processes, semiconductor processes, FETs, field effect transistors

Description

Fabrication method of nanowire multichannel FET device

The present invention relates to a method for manufacturing a nanowire multichannel FET device, and to overcome the limitations of existing nanomaterial FET devices, a nanowire multichannel FET device that simultaneously realizes high current transfer capability and fast charge mobility can be mass-produced at low cost. It relates to a manufacturing method that can be.

Single-Walled Carborn Nanotubes (SWNTs) among nanomaterials are highly applicable to field effect transistor (FET) devices due to their high electron mobility and have large surface area to volume ratios. Therefore, it is very applicable to chemical sensor and biosensor.

However, an important obstacle currently preventing the commercialization of SWNT devices is the absence of mass assembly technology in which SWNTs fabricate structures arranged in specific directions at specific locations. In addition, in order to fabricate thin film transistors (TFTs) or FETs on various substrate materials without exposing the device substrate to high temperature, a solution process technology for depositing grown SWNTs on the substrate must be secured instead of the conventional CVD growth method.

In order to overcome the above problem, a single channel device in which one SWNT forms a channel between a source and a drain electrode has been studied.

Single channel FET devices have a very high electron mobility (μ> 10000 cm 2 / Vs), while the drawback is that the amount of current that can be carried by one SWNT is very small.

In order to avoid the above problem, FET devices in which a channel uses a random SWNT network instead of one SWNT have been studied.

The charge mobility (μ) of the SWNT network FET device is approximately 1000 times lower than that of a single channel FET device since it is ~ 10 cm 2 / Vs. Thus, in order to obtain greater electron mobility than SWNT networks, channels in which nanomaterials are arranged in one direction in a constant region must be manufactured. In addition, in order to obtain improved current carrying capability than the single channel FET device, a nanowire FET device having a multichannel instead of a single channel must be manufactured.

Recently, scientific exploration and engineering applications have been extended to nanometers, so the necessity of fabricating nanostructures not only with good regularity but also with good control of pattern, size and shape is rapidly increasing. In many applications, nanostructures must be fabricated in a fairly large area, and nanostructures will be widely used only if the manufacturing costs are within an acceptable range.

Photolithography, which is widely used in the semiconductor process, is not suitable for the production of complex sub-micron (µm) patterns, and thus is commonly used for the production of complex patterns consisting of lines having a width of 1 µm or more. Sometimes line widths of sub-micron (> 500 nm) are used, but the manufacturing cost of photomasks for sub-μm patterns is very expensive.

Recently, an assembly pattern of nanomaterials having a line width of 3 to 4 μm has been reported by using self-assembly of photolithography and carbon nanotubes in order to make the aligned nanomaterial pattern large.

However, since the carbon nanotubes used in the solution process are several nm in diameter and 1 to 2 μm in length, it is practically impossible to manufacture a pattern arranged with one nanotube in the width direction.

Thus, in order to simultaneously obtain greater current carrying capability than single channel FET devices and greater charge mobility than random network FET devices, the line width at which nanomaterials are assembled must be smaller than sub-micron.

(Reference)

[1] J. Kong, N. Franklin, C. Zhou, M. Chapline, S. Peng, K. Choi, H. Dai, “Nanotube Molecular Wires as Chemical Sensors,” Science, Vol. 287, p. 622 (2000).

[2] Xinjian Zhou, Ji-Yong Park, Shaoming Huang, Jie Liu, and Paul L. McEuen, “Band Structure, Phonon Scattering, and the Performance Limit of Single-Walled Carbon Nanotube Transistors,” Phys. Rev. Lett., 95, p. 146805 (2005).

[3] E. S. Snow, J. P. Novak, P. M. Campbell, and D. Park, "Random networks of carbon nanotubes as an electronic material," Appl. Phys. Lett., Vol. 82, No. 13, pp. 2145 (2003).

[Reference 4] M. Lee, J. Im, BY Lee, S. Myung, J. Kang, L. Huang, Y.-K. Kwon & S. Hong, “Linker-free directed assembly of high-performance integrated devices based on nanotubes and nanowires” Nanotechnology , Vol. 1, p.66 (2006).

An object of the present invention is to provide a means for solving the problems appearing in the FET device using nanomaterials that have been developed to meet the intellectual curiosity at the laboratory level and the chemical and biosensors using the same.

Conventional single-channel SWNT FET devices have very high charge mobility (μ> 10000 cm 2 / Vs), while the amount of current they can carry in one SWNT channel is very small. SWNT's random network FET devices, on the other hand, have very low mobility (μ) (˜10 cm 2 / Vs) without significant improvement in current carrying capacity. On the other hand, the FET device using a single pattern with a line width of 3 to 4 µm as a channel by photolithography and self-assembly processes has a channel width that is reduced by about one-tenth of that of a random network FET (channel width = 35 µm). Nanomaterials are distributed in random directions. Therefore, there is an advantage that the large area can be manufactured using the semiconductor process, but the improvement of the charge mobility and the current density is not significant.

In order to commercialize FET devices using nanostructured materials that have been developed to satisfy intellectual curiosity at the laboratory level, low-cost and large-scale production processes must be built using technology compatible with the current semiconductor industry. In addition, nanomaterial FET devices with this technology must meet both high charge mobility and large current carrying capability. Accordingly, the present invention is to provide a method that can simultaneously meet the high charge mobility and current carrying capacity, and can produce a nanomaterial FET device with low cost and large area.

In order to achieve the above object, the present invention provides a method for manufacturing a nanowire multi-channel FET device, comprising the steps of: forming a V groove nanowire array on a substrate or a thin film on the substrate through photolithography and wet etching process; Self-assembling nanomaterials into the V grooves of the V groove nanowire array through a solution process; It provides a method for manufacturing a nanowire multi-channel FET device comprising the step of manufacturing a multi-channel FET device using the V groove nanowire array self-assembled the nanomaterial.

In a preferred embodiment, the substrate or thin film material on the substrate forming the V-groove nanowire array is Si, Silicon-On Insulator (SOI), GaAs-On Insulator (GOI), InP-On Insulator (IOI), GaAs, InP, and the III-V compound grown on the basis of the single crystal semiconductor is characterized in that it is selected.

In addition, in the step of forming the V groove nanowire array through the photolithography and wet etching process,

The width of the repetitive photoresist linear pattern produced by the photolithography process is 2 µm or less and the spacing between the linear patterns is 2 µm or less,

In the photolithography process, the number of repetitive straight line patterns can be arbitrarily controlled.

In addition, in the step of forming the V groove nanowire array through the photolithography and wet etching process,

Repetitive photoresist linear array prepared by the photolithography process is characterized in that the V groove is formed by anisotropic etching through the chemical wet etching solution.

In addition, the material of the etching mask used in the wet etching process is characterized in that selected from photoresist, SiO ₂ , Si ₃ N ₄ , a polymer (polymer), and a metal thin film.

In addition, the etching depth of the V groove manufactured by the wet etching process is characterized in that less than 3 ㎛.

In addition, a substrate containing repetitive photoresist linear patterns prepared through a photolithography process is immersed in an octadecyltrichlorosilane (OTS) solution to deposit an OTS thin film,

The photoresist is then removed to form a repeating OTS pattern that exposes the substrate between the OTS patterns,

Subsequently, a V groove nanowire array is formed on the substrate through a wet etching process using an OTS thin film as an etching mask.

Dipping the substrate on which the V-groove nanowire array is formed in a nanomaterial solution is performed to align the nanomaterial within the V groove.

In addition, when the V substrate is formed when the silicon substrate is used, the etching rate in the depth direction with respect to the width direction is increased by 400 times or more, and the etching is stopped.

In addition, when the silicon substrate is used to measure the etching time to form the V groove is characterized in that the line width of the bottom surface before the V groove is formed by adjusting the etching time.

In addition, in the process of depositing the OTS thin film by immersing the substrate containing the photoresist linear patterns in an OTS solution,

The time for immersing the substrate in the OTS solution is characterized in that the thickness of the deposited OTS thin film is in the range of 0.5 ~ 1.5 ㎛.

In addition, a substrate containing repetitive photoresist linear patterns manufactured through a photolithography process is immersed in an OTS solution to deposit an OTS thin film,

The photoresist is then removed to form a repeating OTS pattern that exposes the substrate between the OTS patterns,

Subsequently, a V groove nanowire array is formed on the substrate through a wet etching process using an OTS thin film as an etching mask.

Subsequently, the substrate on which the V-groove nanowire array is formed is immersed in an APTES (3-aminopropyl trimethoxysilane) solution to deposit an APTES thin film on the V groove, and then the substrate on which the APTES thin film is deposited is immersed in a nanomaterial solution to deposit the nanomaterial. It is characterized by performing a solution process to align the inside.

In addition, after forming an APTES thin film having a different APTES concentration according to the height inside the V groove of the substrate, the substrate is immersed in a nanomaterial solution so that one nanomaterial is aligned in the width direction of the V groove.

In addition, in the process of depositing the APTES thin film in the V-groove, the substrate is removed from the APTES solution and placed on a flat bottom so that the APTES solution flows along the inner wall of the V-groove, so that the concentration of APTES decreases downward from the V-groove. It is characterized by that.

In addition, the substrate material for fabricating the multichannel FET device is an SOI wafer, the Si thin film in which the V groove nanowire array is formed in the SOI wafer is undoped Si, and the Si substrate under SiO ₂ is a back-gate. It is characterized in that the doped (doped) to form a (back-gate) electrode.

In addition, the width of the bottom of the SiO ₂ is formed so as to be exposed, wherein the exposure to SiO ₂ within the V-groove to the V-groove is used for the etching solution is not more than 100 etch rate in the width direction of the depth direction is formed on the SOI wafer It is characterized by adjusting the etching time.

A bottom portion of the nanomaterial aligned inside the V-groove is also in contact with the exposed SiO ₂ , and both side portions of the aligned nanomaterial are in contact with the undoped Si such that neighboringly aligned nanomaterials are in contact with each other. It is characterized in that it is electrically isolated.

Accordingly, according to the present invention, the nanowire array is formed on the substrate using the photolithography and the wet etching semiconductor process technology, and then one nanomaterial is aligned in the width direction of the unit nanowire using the solution process to fuse the nanotechnology. Nanowire multichannels can be configured, which enables nanowire multichannel FET devices to be fabricated.

As a result, the FET device manufactured by the present invention can simultaneously realize high current transfer capability and fast charge mobility, which are limitations of conventional nanomaterial FET devices, and in particular, the number of nanochannels can be controlled by a semiconductor process. The current magnitude of the drain can be arbitrarily adjusted, eliminating the need for a current amplifier in external circuitry.

In addition, the photolithography and wet etching processes used in the present invention are advantageous in that they can be mass-produced at low cost because they are compatible with the existing silicon semiconductor industry. In addition, the solution process is inexpensive because it can be easily processed in a large area without special expensive equipment. Therefore, the present invention mass-produces a V-groove nanowire multichannel FET device or a nanowire multichannel FET array device based on the FET device and a system on chip (SOC) chip in which the devices and the driving circuit are integrated. It provides a method that can be manufactured in a manner, and is very industrially applicable.

The nanowire multi-channel FET device manufactured by the present invention can be usefully applied to electronic devices, logic devices, chemical sensors and biosensors that require high speed and high output, and array devices based on them.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention utilizes a well-established semiconductor process in the conventional silicon semiconductor industry to overcome the problems of conventional single channel SWNT FET devices and random network FET devices. Provided are methods for manufacturing a device.

In particular, in the present invention, photolithography and anisotropic etching techniques are used to fabricate the repetitive arrangement of the V-groove nanowires at a large area and at low cost.

In addition, the present invention provides a method of manufacturing a nanowire array and a method of self-assembling nanomaterials in the manufactured nanowire, and provides a method of manufacturing a V-groove nanowire multichannel FET device using the same.

First, a method of forming a V groove nanowire array using photolithography and anisotropic etching and a method of aligning nanomaterials to the nanowire array will be described.

In the FET device fabricated using conventional photolithography and self-assembly of nanomaterials, since the width of the channel is 3 to 4 μm, the self-assembled SWNTs are arranged one or more per channel width. As a result, high current carrying capacity and large charge mobility were not improved at the same time. To solve this problem, there is a need for a technique capable of producing sub-micron line widths of 1 μm or less using photolithography. However, the photomask for photolithography has a problem in commercialization because the manufacturing cost increases rapidly when the line width becomes 1 탆 or less.

In order to solve the above problem, the present invention provides an etching process capable of manufacturing nanowire width after the photolithography process of the micron pattern. Single crystal semiconductors Si, GaAs, InP and compound semiconductors based on them become anisotropic because the etching speed varies depending on the crystal direction during chemical wet etching.

In the present invention, a V groove nanowire array is formed on a substrate or a thin film on the substrate through photolithography and a wet etching process. As the substrate or thin film material forming the V groove nanowire array, Si, Silicon-On Insulator (SOI), GaAs-On Insulator (GOI), InP-On Insulator (IOI), GaAs, InP, and III-V compound single crystal semiconductors grown based thereon.

1 shows an example of anisotropic etching of GaAs and Si single crystals. In FIG. 1 (a), PR having a width of 2 μm was used as an etching mask in a phosphate etching solution (H ₃ PO ₄ : H ₂ O ₂ : H ₂ O = 19: 6: 25). At this time, since the adjacent GaAs under the PR mask is etched, the upper straight line width (0.8 μm) becomes narrower than the lower width (3.5 μm) when the etching depth is 2 μm. That is, the etching in the depth direction and the width direction proceeds at different etching speeds, resulting in anisotropic etching. Figure 1 (b) shows the crystal direction and the shape of the etching surface to form a silicon V groove (reference numeral 11). In the chemical wet etching process for anisotropic etching, a material of an etch mask may be a photoresist, SiO ₂ , Si ₃ N ₄ , a polymer, a metal thin film, or the like.

). 따라서, 식각된 하단면의 폭이 식각깊이로 조절된다. 이것은 포토리소그라피의 한계 분해능을 극복할 수 있는 수단을 제공한다. 만일 반복적으로 식각된 하단면 위에 나노물질(나노튜브나 나노와이어)이 정렬된다면 나노선을 이용한 다중채널 FET 소자가 제조될 수 있다. 둘째, KOH의 식각률이 (111) 면에 대해 매우 느리기 때문에 일단 V 홈이 실리콘에서 만들어지면 식각이 거의 멈춘다. 그 이유는 (100) 면과 (111) 면 사이의 식각비율이 400:1이기 때문이다[문헌 5].A KOH solution can be used to anisotropically etch silicon, which has two advantages. First, the spacing between the masks can be wider depending on the depth of etching (

). Thus, the width of the etched bottom surface is adjusted to the etching depth. This provides a means to overcome the limit resolution of photolithography. If nanomaterials (nanotubes or nanowires) are aligned on the repeatedly etched bottom surface, multichannel FET devices using nanowires can be fabricated. Second, since the etch rate of KOH is very slow with respect to the (111) plane, the etch almost stops once the V groove is made from silicon. The reason is that the etching ratio between the (100) plane and the (111) plane is 400: 1 [Document 5].

2 is a flowchart illustrating a process of fabricating a V-groove nanowire array using photolithography and anisotropic etching. First, the PR (2) is spin-coated on the single crystal silicon substrate 1, and then soft baked at 90 to 95 ° C for several minutes (Fig. 2 (a)). Thereafter, ultraviolet (UV) is irradiated onto the photoresist 2 through the photomask 3 using a mask aligner for a photolithography process (FIG. 2B). When the sample (substrate) irradiated with UV is developed, straight lines having a constant width and spacing are formed in the PR pattern 2a as shown in FIG. After that, the sample (substrate) is etched in the KOH solution using the PR pattern (2a) as an etching mask (Fig. 2 (d)). At this time, the interval between the repetitive linear pattern is determined by the etching depth, when the etching depth is limited to 3 ㎛ or less, the interval between the straight lines that can be produced by the photolithography process is set to 1 ~ 2 ㎛.

FIG. 3 is an example in which nanomaterials are aligned in a solution process to the V-groove arrangement obtained as a result of FIG. 2. The number of V grooves 11 can be adjusted from one to several hundreds or thousands as needed by a photomask for photolithography. For example, in a repetitive pattern, when the width of the straight line and the distance between the straight lines are both 1 μm, the array of straight lines required to make 1000 V grooves is only 2 mm.

There are two ways to align the nanomaterial 12 to the silicon V groove 11. First, the self-assembly method of [4] should be improved. That is, the sample of step (c) of FIG. 2 is immersed in an octadecyltrichlorosilane (OTS) solution to be deposited in a region without PR. At this time, in order for the thickness of the OTS thin film to be about 0.5 to 1.5 µm, the immersion of [Document 4] needs a much longer time than the time. After that, the PR pattern on the sample surface is removed with acetone, and silicon is etched in the KOH solution using an OTS thin film as an etching mask. Subsequently, the V groove is placed in a solution in which the nano material is dispersed so that the nano material is aligned with the V groove of the sample.

Second, in the first process, the thin film is deposited by immersing the sample having V groove nanowire array into the APTES (3-aminopropyl trimethoxysilane) solution by using the OTS thin film as an etching mask, and then using SWNT having a negatively charged functional group as the solution process. It is a process method to arrange on a thin film. In this process method, after forming an APTES thin film having a different APTES concentration according to the height inside the V groove of the sample, the sample is immersed in the nanomaterial solution so that one nanomaterial is aligned in the width direction of the V groove. To this end, the sample taken from the APTES solution is placed on a flat bottom before immersing in the SWNT solution, which thickens as the APTES goes down because the APTES solution flows down the inner wall of the V groove. As a result, SWNTs are arranged below the higher APTES concentration, so that a single SWNT can be arranged. After immersing in the APTES solution in the above process to deposit the APTES thin film in the V groove, it is taken out and dried with nitrogen (N ₂ ).

The method proposed in the present invention is a concept opposite to the method used in [Document 6]. In Document 6, the time for stamping is increased after the polymer is buried in the stamp. The nanomaterials were arranged one by one in a pattern where the polymer concentration in the center was darker and weaker toward the periphery using the polymer diffusion property. On the other hand, the present invention is a method of aligning the nanomaterials at the bottom after making the V grooves and make the concentration of APTES down along the grooves thickened.

Next, a method of fabricating a nanowire multichannel FET using photolithography and anisotropic etching will be described.

In the embodiment described above, there is no longer a post process that can produce a nanowire FET device when the substrate is a silicon single crystal. In contrast, the embodiments described below are examples in which a SOI (Si-On-Insulator) wafer is used as a substrate to fabricate a nanowire multichannel FET. 4 is a process chart for manufacturing the V groove 11 on the SOI substrate 4. Referring to the process diagram of FIG. 4, the substrate 4 is identical except that SOI is used instead of Si. However, in the SOI substrate 4, the Si thin film 4c over SiO ₂ 4b is undoped Si and the Si substrate 4a under SiO ₂ 4b is a back-gate electrode. Doped Si is used to make. When the KOH solution is etched at 80 ° C. with a concentration of 30%, the etching rate of the (111) plane is 0.015 μm / min, and the etching rate of the (100) plane is 1.12 μm / min. In this case, if the etching time is increased after the V groove is made, etching of the (111) plane proceeds to increase the line width of the SiO ₂ on the lower surface. As such, in the present invention, the etching time at which the V groove 11 is formed may be measured to adjust the line width of the bottom surface to the etching time before the V groove is formed. Preferably, in the case of using an SOI wafer, the V groove formed in the substrate is formed such that SiO ₂ at the bottom thereof is exposed inside the V groove by using an etching solution having an etch ratio of 100 or less in the width direction with respect to the depth direction. At this time, the width of the exposed SiO ₂ is controlled by the etching time.

5 is a structural diagram in which the nanomaterial 12 is aligned with the V groove 11 in the same manner as in FIG. 3 by changing the condition of the etching solution to the condition described in FIG. 4. Of course, the substrate 4 was changed to SOI instead of Si.

6 is a conceptual diagram of a nanowire multichannel FET device in which nanomaterials are aligned in a V groove. The nanomaterials 12 are arranged in the plurality of V-groove 11 nanowires, respectively, to form a multichannel, and the source electrode 5 and the drain electrode 6 are formed with the multichannel interposed therebetween, and the substrate 4 The back-gate electrode 7 is formed on the back side of the), so that the V groove FET device can be manufactured. Referring to FIG. 6, the bottom portion of the nanomaterial 12 is in contact over SiO ₂ 4b and both side portions are in contact with the undoped Si thin film 4c. Thus, the adjacently aligned nanomaterials 12 are electrically isolated.

In Figure 6 there are three channels of the FET device, the number of channels as shown in Figure 5 can be fabricated a multi-channel V-wire nanowire multi-channel FET device. Each channel is aligned with one nanomaterial in the width direction. Therefore, the V-groove nanowire multichannel FET devices can carry larger currents than single channel FET devices made from just one nanotube, as well as larger charge transfer than FET devices using SWNT's random network. You can also get As a result, the present invention provides a technique in which the shortcomings of the existing single channel FET device and the network FET device can be solved simultaneously.

In this way, the present invention aligns one nanomaterial in the width direction of the unit nanowires constituting the nanowire array by a photolithography and etching technique capable of producing nanowire arrays at a large area and low cost and a solution process. The nanotechnology can be used to provide a method for manufacturing a fused V-groove nanowire multichannel FET device. In particular, since photolithography and etching techniques are compatible with the existing silicon semiconductor industry, they can be mass-produced at low cost. In addition, the solution process is inexpensive because it can be easily processed in large area without special expensive equipment. Therefore, the present invention mass-produces a V-groove nanowire multichannel FET device or a nanowire multichannel FET array device based on the FET device and a system on chip (SOC) chip in which the devices and the driving circuit are integrated. It provides a method that can be manufactured in a manner, and is very industrially applicable.

(Reference)

H. Seidel, L. Csepregi, A. Heuberger, and H. Baumgartel, “Anisotropic Etching of Crystalline Silicon in Alkaline Solutions,” J. Electrochem . Soc , Vol. 137, No. 11, pp. 3612-3626 (1990).

[6] Sung Myung, Jiwoon Im, Ling Huang, Saleem G. Rao, Taekyeong Kim, Dong Joon Lee, and Seunghun Hong, ““ Lens ”Effect in Directed Assembly of Nanowires on Gradient Molecular Patterns,” J. Phys. Chem . B, Vol. 110, no. 21, pp 10217-10219 (2006).

1 is a view showing anisotropic etching of GaAs and Si single crystal in the present invention,

2 is a process flow diagram of fabricating a V groove nanowire array on a Si substrate using photolithography and anisotropic etching in the present invention;

FIG. 3 is a view illustrating nanomaterials aligned in a solution process on a V-groove nanowire array prepared on a Si substrate.

4 is a process diagram in which a V groove is fabricated on an SOI substrate;

5 is a structural diagram in which nanomaterials are arranged in a multi-V groove;

6 is a structural diagram of a V groove nanowire FET device fabricated on an SOI substrate.

<Explanation of symbols for the main parts of the drawings>

1, 4: substrate 11: V groove

12: nanomaterial

Claims (16)

In the method of manufacturing a nanowire multichannel FET device, (a) forming a V-groove nanowire array in a substrate or a thin film on the substrate using a photolithography and a wet etching process together; (b) immersing the substrate on which the V groove nanowire array is formed in a nanomaterial solution to self-assemble the nanomaterial inside the V groove; (c) fabricating a multichannel FET device using the V groove nanowire array in which the nanomaterial is self-assembled; Nanowire multi-channel FET device manufacturing method comprising a. The method according to claim 1, The substrate or the thin film material on the substrate forming the V-groove nanowire array may be Si, Silicon-On Insulator (SOI), GaAs-On Insulator (GOI), InP-On Insulator (IOI), GaAs, InP, and the base material. Method of manufacturing a nanowire multi-channel FET device, characterized in that selected from among the III-V compound single crystal semiconductor grown. The method according to claim 1, In the step (a), The width of the repetitive photoresist linear pattern produced by the photolithography process is 2 µm or less and the spacing between the linear patterns is 2 µm or less, A method for manufacturing a nanowire multichannel FET device, characterized in that the number of repeating linear patterns can be arbitrarily controlled in a photolithography process. The method according to claim 1, In the step (a), A method of fabricating a nanowire multichannel FET device, wherein a repeating photoresist linear array prepared by a photolithography process is anisotropically etched through a chemical wet etching solution to form V grooves. The method according to claim 4, The material of the etching mask used in the wet etching process is a method of manufacturing a nanowire multi-channel FET device, characterized in that selected from photoresist, SiO ₂ , Si ₃ N ₄ , a polymer, and a metal thin film. The method according to claim 4, The method of manufacturing a nanowire multi-channel FET device characterized in that the etching depth of the V groove manufactured by the wet etching process is 3 ㎛ or less. The method according to claim 1, In step (a), (a1) immersing a substrate including repetitive photoresist linear patterns prepared by a photolithography process in an octadecyltrichlorosilane (OTS) solution to deposit an OTS thin film on the substrate surface; (a2) removing the photoresist to form a repeating OTS pattern, thereby exposing the substrate between the OTS patterns; (a3) forming a V-groove nanowire array on the substrate through a wet etching process using an OTS thin film as an etching mask; Nanowire multi-channel FET device manufacturing method comprising a. The method of claim 7, The method of manufacturing a nanowire multichannel FET device, characterized in that when the silicon substrate is used, the etching is stopped while the etching rate in the depth direction with respect to the width direction becomes greater than 400 times when the V groove is formed. The method of claim 7, The method of manufacturing a nanowire multichannel FET device, characterized in that by measuring the etching time when the V groove is formed when the silicon substrate is used to adjust the line width of the bottom surface to the etching time before the V groove is formed. The method of claim 7, In the step (a1), The time for immersing the substrate in the OTS solution is characterized in that the thickness of the deposited OTS thin film is determined to be in the range of 0.5 ~ 1.5 ㎛ the nanowire multi-channel FET device. The method of claim 7, After the step (a3), (a4) depositing an APTES thin film inside the V groove by dipping the substrate having the V groove nanowire array formed therein into a 3-aminopropyl trimethoxysilane (APTES) solution; Nanowire multi-channel FET device characterized in that it further comprises. The method of claim 11, Step (a4) is, In the V groove of the substrate to form an APTES thin film having a different concentration of APTES according to the height, And dipping the substrate in a nanomaterial solution so that one nanomaterial is aligned in the width direction of the V groove. The method according to claim 11 or 12, In the process of depositing the APTES thin film in the V-groove, the substrate is removed from the APTES solution and placed on a flat bottom so that the APTES solution flows along the inner wall of the V-groove so that the concentration of APTES increases downward from the V-groove. Method of manufacturing a nanowire multi-channel FET device, characterized in that. The method according to claim 1, The substrate material for fabricating the multichannel FET device is an SOI wafer, and the Si thin film in which the V groove nanowire array is formed in the SOI wafer is undoped Si, and the Si substrate under SiO ₂ is a back-gate ( A method for fabricating a nanowire multichannel FET device, comprising doped Si to form a back-gate electrode. The method according to claim 14, When forming the V groove nanowire array on the Si thin film in the SOI wafer, An etching solution having an etch ratio in the width direction with respect to the depth direction of the V groove is 100 or less so that SiO ₂ at the bottom thereof is exposed inside the V groove, and the width of the exposed SiO ₂ is controlled by the etching time. A method for manufacturing a nanowire multichannel FET device. 16. The method of claim 15, A lower surface portion of the nanomaterial aligned inside the V groove contacts the exposed SiO ₂ , and both side portions of the aligned nanomaterial contact the undoped Si such that adjacently aligned nanomaterials are electrically connected to each other. Method of manufacturing a nanowire multi-channel FET device characterized in that it is isolated by.

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