KR101046006B1 - 무수축 다층 세라믹 기판의 제조방법 - Google Patents
무수축 다층 세라믹 기판의 제조방법 Download PDFInfo
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- KR101046006B1 KR101046006B1 KR1020080104467A KR20080104467A KR101046006B1 KR 101046006 B1 KR101046006 B1 KR 101046006B1 KR 1020080104467 A KR1020080104467 A KR 1020080104467A KR 20080104467 A KR20080104467 A KR 20080104467A KR 101046006 B1 KR101046006 B1 KR 101046006B1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0209—Inorganic, non-metallic particles
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1126—Firing, i.e. heating a powder or paste above the melting temperature of at least one of its constituents
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- H—ELECTRICITY
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1333—Deposition techniques, e.g. coating
- H05K2203/1366—Spraying coating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
- H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
- H05K3/1283—After-treatment of the printed patterns, e.g. sintering or curing methods
- H05K3/1291—Firing or sintering at relative high temperatures for patterns on inorganic boards, e.g. co-firing of circuits on green ceramic sheets
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (14)
- 복수의 세라믹 그린 시트 중 일부 세라믹 그린시트에 적어도 하나 이상의 비아 홀 및 전극 패턴을 형성하는 단계;상기 세라믹 그린 시트들을 적층하여 세라믹 적층체를 형성하는 단계;상기 세라믹 적층체의 일면 또는 양면 중 상기 비아 홀 및 상기 비아 홀 주변을 포함하는 영역에 에어로졸 증착법을 이용하여 난소결성 분말로 이루어지며 상기 비아 홀 및 비아 홀 주변에 강한 수축 구속력을 가할 수 있는 수축억제용 박막을 선택적으로 형성하는 단계;상기 수축억제용 박막이 형성된 세라믹 적층체의 상면 및 하면 중 적어도 일면에 상기 세라믹 적층체의 수축을 억제하기 위한 수축억제용 그린 시트를 배치시켜 미소결 다층 세라믹 기판을 형성하는 단계; 및상기 미소결 다층 세라믹 기판을 소성하는 단계;를 포함하는 무수축 다층 세라믹 기판의 제조 방법.
- 제1항에 있어서,상기 미소결 다층 세라믹 기판을 형성하는 단계는, 상기 수축억제용 박막이 형성된 세라믹 적층체의 양면에 수축억제용 그린 시트를 배치시키는 단계인 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
- 제1항에 있어서,상기 소성하는 단계 후에, 상기 소성된 다층 세라믹 기판으로부터 상기 수축억제용 박막 및 상기 수축억제용 그린 시트들을 제거하는 단계;를 더 포함하는 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
- 제3항에 있어서,상기 소성하는 단계 후에, 상기 소성된 다층 세라믹 기판으로부터 상기 수축억제용 박막 및 상기 수축억제용 그린 시트들을 제거하는 단계는, 래핑, 샌드 블러스팅, 수세 및 고압 분무 중 어느 하나에 의해 수행되는 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
- 제1항에 있어서,상기 세라믹 적층체를 형성하는 단계는, 상기 비아 홀 및 전극 패턴이 형성된 세라믹 그린 시트들을 적층한 후, 30 ~ 50 MPa의 압력으로 열압착하는 단계;를 더 포함하는 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
- 제1항에 있어서,상기 적어도 하나 이상의 비아 홀 및 전극 패턴을 형성하는 단계는, 펀치에 의한 펀칭 가공, 레이저빔에 의한 레이저 가공 및 드릴에 의한 드릴링 가공 중 어느 하나에 의하여 상기 비아 홀을 형성하는 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
- 제1항에 있어서,상기 난소결성 분말은 알루미나(Al2O3), 이산화세륨(CeO2), 아연화(ZnO2), 지르코니아(ZrO2), 마그네시아(MgO) 및 질화붕소(BN) 중 어느 하나인 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
- 제7항에 있어서,상기 난소결성 분말의 평균 입경은 0.3 ~ 1 ㎛ 인 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
- 제1항에 있어서,상기 수축억제용 박막을 선택적으로 형성하는 단계는, 상기 세라믹 적층체의 일면 또는 양면상에 상기 비아 홀 및 상기 비아 홀 주변을 포함하는 영역이 개방되도록 패턴 마스크를 배치하고, 상기 세라믹 적층체의 일면 또는 양면 중 상기 패턴 마스크에 의해 개방된 영역에만 수축억제용 박막을 증착하는 단계인 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
- 제9항에 있어서,상기 개방된 영역은 적어도 상기 비아 홀을 포함한 영역인 것을 특징으로 하 는 무수축 다층 세라믹 기판의 제조 방법.
- 제1항에 있어서,상기 수축억제용 박막을 선택적으로 형성하는 단계는, 상기 세라믹 적층체의 일면 또는 양면의 전체면에 수축억제용 박막을 증착하는 단계인 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
- 제1항에 있어서,상기 수축억제용 박막의 직경은 100 ~ 500 ㎛ 인 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
- 제1항에 있어서,상기 수축억제용 박막의 두께는 3 ~ 20 ㎛인 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
- 제1항에 있어서,상기 난소결성 분말 및 상기 수축억제용 그린 시트들은 상기 미소결 다층 세라믹 기판의 소결 온도보다 높은 소결 온도를 갖는 것을 특징으로 하는 무수축 다층 세라믹 기판의 제조 방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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KR1020080104467A KR101046006B1 (ko) | 2008-10-23 | 2008-10-23 | 무수축 다층 세라믹 기판의 제조방법 |
US12/476,216 US8753462B2 (en) | 2008-10-23 | 2009-06-01 | Method of manufacturing non-shrinking multilayer ceramic substrate |
JP2009134442A JP4881975B2 (ja) | 2008-10-23 | 2009-06-03 | 無収縮多層セラミック基板の製造方法 |
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KR1020080104467A KR101046006B1 (ko) | 2008-10-23 | 2008-10-23 | 무수축 다층 세라믹 기판의 제조방법 |
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KR20100045334A KR20100045334A (ko) | 2010-05-03 |
KR101046006B1 true KR101046006B1 (ko) | 2011-07-01 |
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US (1) | US8753462B2 (ko) |
JP (1) | JP4881975B2 (ko) |
KR (1) | KR101046006B1 (ko) |
Families Citing this family (8)
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JP2011081447A (ja) * | 2009-10-02 | 2011-04-21 | Seiko Instruments Inc | 情報処理方法及び情報処理装置 |
KR101292040B1 (ko) * | 2011-10-04 | 2013-08-01 | 한국세라믹기술원 | 저온동시소성세라믹스 기판의 제조방법 |
JP2013089942A (ja) * | 2011-10-13 | 2013-05-13 | Samsung Electro-Mechanics Co Ltd | 無収縮セラミック基板及びその製造方法 |
US9105561B2 (en) * | 2012-05-14 | 2015-08-11 | The Boeing Company | Layered bonded structures formed from reactive bonding of zinc metal and zinc peroxide |
JP6030373B2 (ja) * | 2012-08-01 | 2016-11-24 | 日本特殊陶業株式会社 | 多層セラミック基板及びその製造方法 |
CN104253884A (zh) * | 2013-06-28 | 2014-12-31 | 深圳富泰宏精密工业有限公司 | 外壳及其制造方法 |
JP2017109895A (ja) * | 2015-12-15 | 2017-06-22 | 株式会社村田製作所 | セラミック焼成体の製造方法 |
JP6597268B2 (ja) * | 2015-12-15 | 2019-10-30 | 株式会社村田製作所 | セラミック焼成体の製造方法 |
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US5662755A (en) * | 1993-10-15 | 1997-09-02 | Matsushita Electric Industrial Co., Ltd. | Method of making multi-layered ceramic substrates |
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JP2010103474A (ja) | 2010-05-06 |
JP4881975B2 (ja) | 2012-02-22 |
KR20100045334A (ko) | 2010-05-03 |
US8753462B2 (en) | 2014-06-17 |
US20100101701A1 (en) | 2010-04-29 |
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