KR101041866B1 - Semiconductor device manufacturing method - Google Patents

Abstract

The present disclosure relates to a method for manufacturing a semiconductor device, such as a diode and a field effect transistor, and when forming an oxide semiconductor layer for an activation region, controlling the electrical characteristics of the oxide semiconductor layer by controlling process conditions including at least a gas atmosphere. It may include the step, wherein the gas atmosphere may be to adjust the ratio of oxygen in the carrier gas, further comprising the step of forming a metal layer having a Schottky bonding characteristics or ohmic bonding characteristics on the oxide semiconductor layer, It is possible to improve the characteristics of the semiconductor device, to facilitate the selection and use of metal electrodes through existing processes, to solve problems such as short channels due to the miniaturization of the device, and to avoid the existing silicon-based electronic devices.

Oxide semiconductor, activation region, Schottky junction, ohmic junction, gas atmosphere

Description

Method of fabricating semiconductor device

The present disclosure relates to a method for manufacturing a semiconductor device such as a diode and a field effect transistor, and more particularly, to use an oxide semiconductor as an activation region, to be fabricated on a flexible substrate through a low temperature process, and to improve the direct The present invention relates to a method of fabricating a semiconductor device in which a Schottky barrier structure is applied to prevent short channel phenomena due to miniaturization, thereby improving device characteristics.

In general, semiconductor devices have made many advances based on the existing silicon, and thin film transistors, which are one of the devices in the display field, have been used as driving devices in recent years, and are prominent in various applications. Indicates.

Currently, driving and switching devices for displays include hydrogenated amorphous silicon thin film transistors (a-Si-TFT: H) and polycrystalline silicon thin film transistors (poly-Si-TFTs) that are being studied in many places.

Amorphous silicon thin film transistor has the advantage of not only the process of integrating a large area on the glass substrate and low substrate temperature but also high stability and low manufacturing cost, but it has low mobility and requires high speed. It is a high barrier to construct the reality. On the other hand, many studies have been conducted due to the advantages of high mobility with the development of low temperature process technology, but there are still problems to be solved due to the disadvantages such as poor uniformity. have.

In order to overcome the problems of the above-mentioned amorphous and crystalline silicon technology, technical researches on oxide semiconductors are actively conducted.

In recent years, ZnO-based n-type oxide semiconductors, which are oxide semiconductors, are being researched in many places as driving devices for next-generation displays. ZnO-based thin films and devices have high mobility and can be embedded in driving circuits. It can be used as a driving device, but due to its electrical and optical instability, doping elements of Group 3, such as B, Al, Ga, and In, have stable electrical and optical properties, thus making it possible to display, solar cells, memories, and optical-electronics. It has begun to be used in various fields.

However, despite the above advantages, ZnO-based devices in the field of electronic devices are mostly characterized by the n-type material, Z-type Z-type features the p-type characteristics of the process stability and hole concentration control Since it is essential, it is not easy to fabricate, making it difficult to fabricate a pn junction device and a silicon-based CMOS structure. For this reason, the study of the Schottky diode structure of the metal-semiconductor junction structure in place of the p-n diode type device is in progress.

However, in most process fabrication of Schottky junction, not only the work function is constant on ZnO series thin film but also the large metal is deposited to obtain diode characteristics. In addition, the process material selection of the MESFET device used as ZnO as an active region and used as a high-speed switching and gas sensor also used a schottky junction material and a material having a large work function difference between the oxide junction as a gate and an ohmic junction metal. Is produced only by selecting the source and drain electrodes.

Currently, the development of ZnO-based oxide semiconductors is mostly made of n-type materials, and the development of p-type materials has been made, but the process is difficult and it is difficult to develop device technologies such as silicon-based pn junction diodes. it's difficult. Accordingly, the development of a device consisting of a ZnO-based oxide junction having a conventional p-type silicon and n-type material is a major reality. On the other hand, in the fabrication of diodes, research on Schottky diodes made of metal materials and oxide semiconductor junctions has been conducted in various places, but only the materials with high work functions or the polarity of the active region have been fabricated.

One aspect of the present invention is to provide a process technology that can artificially control the work function difference between the interface between the metal and the oxide semiconductor to make the semiconductor device easier than the conventional method mentioned above.

According to another aspect of the present invention, a metal and a Schottky barrier having a constant work function can be controlled by adjusting an electron affinity or a work function of an activation surface when forming an activation region using an oxide semiconductor. It is to provide a method for manufacturing a diode as a semiconductor device, which makes it easy to make a structure.

Another aspect of the present invention is to use the Schottky barrier formation technique as described above to create a Schottky barrier between the source and drain and the channel region as the active region to suppress the short-channel effect in the oxide semiconductor according to the miniaturization of the device The present invention provides a method of manufacturing a field effect transistor as a semiconductor device or a method of manufacturing a metal semiconductor field-effect transistor (MESFET), which is a structure of a metal and oxide semiconductor junction field effect transistor using the same.

According to an aspect of the present disclosure, a method of manufacturing a semiconductor device may include adjusting electrical characteristics of the oxide semiconductor layer by adjusting process conditions including at least a gas atmosphere when forming an oxide semiconductor layer for an activation region. The gas atmosphere may be to adjust the ratio of oxygen in the carrier gas, and may further include forming a metal layer having a Schottky bonding property or an ohmic bonding property on the oxide semiconductor layer. The metal layer having the Schottky bonding characteristic may be, for example, made of a metal having a work function of 5 eV or more, and the metal may be gold (Au), silver (Ag), platinum (Pt), nickel (Ni), or palladium. (Pd), iridium (Ir), and cobalt (Co). In addition, the oxide semiconductor layer is an n-type or p-type oxide including at least one metal oxide of indium (In) oxide, gallium (Ga) oxide, zinc (Zn) oxide, aluminum (Al) and tin (Sn) oxide. It can be formed with a semiconductor.

According to another aspect of the present invention, a method of manufacturing a semiconductor device includes forming a first activation region layer on a substrate, and controlling electrical characteristics of the first activation region layer by adjusting first process conditions including at least a gas atmosphere. ; A second activation region layer is formed on the source region and the drain region defined in the first activation region layer, and at least a second process condition including a gas atmosphere is adjusted to adjust the electrical characteristics of the second activation region layer. Adjusting differently from the active region layer; And forming a source electrode and a drain electrode on the second activation region layer, and forming a gate electrode on the gate region defined in the first activation region layer. The first process condition may include the gas atmosphere having an O ₂ / (Ar + O ₂ ) ratio of 5% or less at a pressure of 20 mTorr or less, and the second process condition is O ₂ / at a pressure of 20 mTorr or less (Ar + O ₂ ) ratio may include the above gas atmosphere of 5% or more. In addition, the first and second activation region layers are n-type including one or more metal oxides of indium (In) oxide, gallium (Ga) oxide, zinc (Zn) oxide, aluminum (Al), and tin (Sn) oxide. Or a p-type oxide semiconductor.

According to another aspect of the present invention, a method of manufacturing a semiconductor device includes forming a first activation region layer on a substrate, and controlling electrical characteristics of the first activation region layer by adjusting first process conditions including at least a gas atmosphere. step; A second activation region layer is formed on the gate region defined in the first activation region layer, and the electrical characteristics of the second activation region layer are adjusted by adjusting a second process condition including at least a gas atmosphere. Adjusting differently; And forming a source electrode and a drain electrode on the source region and the drain region defined in the first activation region layer, and forming a gate electrode on the second activation region layer. In the first process conditions, the gas atmosphere may be adjusted so that the ratio of O ₂ / (Ar + O ₂ ) is 5% or more, and in the second process conditions, the gas atmosphere is O ₂ / (Ar + O The ratio of ₂ ) may be adjusted to 5% or less. In addition, the first and second activation region layers are n-type including one or more metal oxides of indium (In) oxide, gallium (Ga) oxide, zinc (Zn) oxide, aluminum (Al), and tin (Sn) oxide. Or it may be formed of a p-type oxide semiconductor. In addition, the source electrode, the drain electrode, and the gate electrode may be formed by the same metal layer.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, wherein the active region layer is formed on a substrate, and at least source and drain regions defined in the activation region layer are controlled by controlling process conditions including at least a gas atmosphere. Adjusting; Forming a source electrode and a drain electrode on the source region and the drain region, respectively; Forming a gate insulating layer on the gate region defined on the activation region layer; And forming a gate electrode on the gate insulating layer. In the process conditions, the gas atmosphere may be adjusted to adjust the ratio of O ₂ / (Ar + O ₂ ) to 5% or less, and the active region layer may include indium (In) oxide, gallium (Ga) oxide, and zinc ( Zn) oxide, aluminum (Al) and tin (Sn) may be composed of one or more metal oxides. In addition, the activation region layer may be formed of a thickness of 5nm ~ 200nm, the gate insulating layer may be made of a high dielectric material having a larger dielectric constant than SiO ₂ .

As described above, according to the semiconductor device manufacturing method according to various aspects of the present disclosure, a low temperature process may be performed on various substrates, and transparent or flexible substrates may also be utilized. In addition, when the activation layer is deposited, the carrier gas may be adjusted to control the electron affinity and work function of the activation layer, and a metal having a relatively large work function may be deposited on the activation layer to manufacture a diode without a post-heat treatment process. In addition, after the activation layer is manufactured in the same manner as the diode fabrication, the MESFET structure may be manufactured by forming an ohmic source and a drain using a metal having a small work function, and forming a gate metal electrode having a large work function. In addition, after forming the activation layer of the above method on the substrate to form a high dielectric constant gate insulating film, depositing a metal gate electrode, patterning and etching to form a source and drain, the junction between the activation region and the source and drain The MOSFET structure can be fabricated by forming a low barrier to electrons during formation.

As described above, according to various aspects of the present invention, since a Schottky junction or an ohmic junction is configured by changing electrical characteristics of an active surface in contact with a metal, a Schottky junction diode and a semiconductor device such as a transistor using the same It not only improves the characteristics, but also facilitates the selection and use of metal electrodes through existing processes, solves problems such as short channels due to the miniaturization of devices, and creates an effect of avoiding conventional silicon-based electronic devices. .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In addition, in describing the component of this invention, terms, such as 1st, 2nd, A, B, (a), (b), can be used. These terms are only for distinguishing the components from other components, and the nature, order or order of the components are not limited by the terms. If a component is described as being "connected", "coupled" or "connected" to another component, that component may be directly connected to or connected to that other component, but there may be another configuration between each component. It is to be understood that the elements may be "connected", "coupled" or "connected".

1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 1, a semiconductor diode device according to an embodiment of the present invention includes a substrate 101, a cathode electrode 102 on the substrate 101, an activation layer 103 on the cathode electrode 102, and an activation layer. (Or referred to as active region layer) a metal anode electrode 104 over 103.

The substrate 101 may use a flexible and transparent ITO substrate, and the activating layer 103 may be a doping material in which at least one of In, Ga, Sn, Zr, Ti, Hf, Li, Al, and the like is uniformly formed in the ZnO series. It may be made of an oxide semiconductor material included or formed in the same ratio as ZnO.

For example, the method of forming the activation layer 103 may be performed by using a low temperature process such as physical vapor deposition (PVD), pulsed laser deposition (PLD), metal organic CVD (MOCVD) method, and the like. A method of forming a thin film using a halide precursor or the like may also be used.

In addition, in the formation of the activation layer 103 according to the embodiment of the present invention, a relatively constant work function of the metal, that is, the electron affinity of the activation layer 103, which is a semiconductor characteristic suitable for the metal anode electrode 104 in this embodiment. By adjusting the degree, a relatively large barrier (qΦ _n = qΦ _m -qχ: qΦ _m = metal work function, qχ = electron affinity of the activating layer (oxide semiconductor)) is formed to shorten even a metal having a relatively low work function. Make a key junction. The metal work function is the difference between the vacuum and Fermi levels, and the electron affinity is the difference from the bottom of the conduction band to the vacuum level. Since ZnO-based materials are semiconductor materials, not only can change the donor level near the conduction band through doping, but also the electron affinity can be changed by changing the donor level during or after ZnO-based formation. You can easily select the bonding with.

That is, according to the embodiment of the present invention, at the time of formation of the activation layer 103, by controlling process conditions including at least a gas atmosphere, the electron affinity as an electrical characteristic of the activation layer 103 may be adjusted, and in this embodiment, gas The atmosphere may be controlled by varying the ratio of oxygen in the carrier gas. For example, the activation layer 103 according to the present embodiment may be formed of an InGaZnO oxide semiconductor formed by adjusting the ratio of argon and oxygen.

In this embodiment, the metal anode electrode 104 is a metal having a work function of 5 eV or more, for example, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), palladium (Pd), And at least one of iridium (Ir) and cobalt (Co).

In the present embodiment, the activation layer 103 is a p-type or n-type type that can be formed by adjusting the above-described materials, such as In, Ga, Sn, Zr, Ti, Hf, Li, Al, to the ZnO material All can be used. In the case of the n-type, when the activation region layer 103 is formed, the electron affinity of the activation region layer 103 is relatively small, so that the Schottky barrier height between the metal electrode 104 and the activation region layer 103 is relatively high. It is possible to improve the rectification characteristics formed to flow a current in one direction. Schottky junction diodes have the same commutation characteristics as pn junction diodes, but their mechanisms differ in that they use a majority carrier and have the advantage of faster switching.

In the present embodiment, the substrate 101 is a glass substrate having an ITO electrode formed thereon, and argon and oxygen on the glass substrate 101 are formed by sputtering, which is a physical vapor deposition (PVD) method, which is frequently used in a vacuum process. An InGaZnO oxide semiconductor formed by adjusting the ratio was deposited to form an activation layer 103. The activation layer 103 was formed in different gas atmospheres, and the results of comparing the characteristics are shown in FIG. 2. Au is used as the metal electrode 104 for the Schottky metal junction, and the rectification characteristics may be better changed by using a metal having a relatively higher work function than Au, such as Pt. In addition, as shown in FIGS. 2A and 2B, by adjusting the ratio of the gas atmosphere when the activation layer 103 is formed, the electrical characteristics may exhibit the ohmic contact characteristics or the Schottky contact characteristics. Can be. In addition, after the activation layer 103 is formed, the electrical properties of the surface may be changed through hydrogen gas or plasma treatment.

The reason for showing different characteristics according to different deposition conditions of the activation region is due to the phenomenon shown by the change of the characteristics of the activation region in contact with the metal having a constant work function. The ZnO series shows that the contact properties may vary depending on the poles of the metal and the contact surface, and the characteristics of the active surface may be changed according to the gas atmosphere of the deposition conditions to form a desired contact. The I-V characteristic curve showing the Schottky contact of FIG. 2 (a) is data measured by forming an anode electrode 104 using Au and an anode electrode 104 using Au. Measurements were measured at intervals of 0.005V from -1V to 1.5V, as shown in FIG. 2 (a), where the current in one direction was relatively higher than the other. This is a characteristic of the metal-oxide oxide junction showing that the Schottky electrode was formed. The current generated in the current in the negative direction is a current generated through the trap at the interface between the metal and the oxide semiconductor when the negative voltage is applied, which may improve the interface characteristics by heat treatment.

Meanwhile, another example of the change in donor level, that is, the change in electron affinity, which is an increase in the conductivity of the channel of the activation region, is shown in FIG. 3. The data of FIG. 3 is data showing the change of the drain current according to the gate voltage of the TFT element which produced IGZO as an active region. In the TFT device illustrated in FIG. 3, TFT_vac is a vacuum heat treatment TFT_H2 is a characteristic obtained through hydrogen heat treatment. As shown, the current characteristics of the hydrogen heat-treated data were higher than the vacuum heat treatment characteristics, which indicates that the donor level was increased in the channel through the hydrogen heat treatment to increase the conductance, thereby changing the electron affinity. This shows that the characteristics of the thin film can be changed through heat treatment, and that the electrical properties of the thin film or the surface of the thin film can be changed by controlling the gas atmosphere during the process as well as the heat treatment.

4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment of the present invention, which is a metal semiconductor field-effect transistor (MESFET) having a metal and oxide semiconductor junction field effect transistor structure.

As shown in FIG. 4, a MESFET according to an embodiment of the present invention is a substrate 401 and a first formed on the substrate 401 to have first electrical characteristics by adjusting first process conditions including at least a gas atmosphere. A second process condition including at least a gas atmosphere is adjusted on the active region layer 402 and the source region and the drain region defined in the first activation region layer 402 to have a second electrical characteristic different from the first electrical characteristic. The gate electrode formed on the gate region defined in the source electrode 404, the drain electrode 405, and the first activation region layer 402 formed on the second activation region layer 403, the second activation region layer 403. 406, a protective film 407 formed over the entire structure to protect the device, and a connection electrode 408 connected to the source / drain electrodes 404 and 405 through the protective film 407.

In this embodiment, the first process condition includes a gas atmosphere having a ratio of O ₂ / (Ar + O ₂ ) of 5% or less at a pressure of 20 mTorr or less, and the second process condition is O ₂ at a pressure of 20 mTorr or less Including a gas atmosphere having a ratio of / (Ar + O ₂ ) of 5% or more, the first activation region layer 402 exhibits a Schottky junction characteristic with the gate electrode 406, and the second activation region layer 403. ) May exhibit ohmic junction characteristics with the source / drain electrodes 404 and 405.

The first and second active region layers 402 and 403 are n-type including at least one metal oxide of indium (In) oxide, gallium (Ga) oxide, zinc (Zn) oxide, aluminum (Al) and tin (Sn) oxide. Or a p-type oxide semiconductor.

Referring to FIG. 4, the source electrode 404 and the drain electrode 405 may separately use a metal electrode exhibiting ohmic characteristics, but the source electrode 404 and the drain electrode 405 may be the same as the gate electrode 406. A first activation region layer 402 having an electrical property for forming a Schottky junction in the gate region portion by using a metal but adjusting the gas atmosphere as in the above-described first and second process conditions, the source and drain regions In the portion, a second active region layer 403 is formed which exhibits electrical characteristics of the ohmic junction.

5-7 is sectional drawing explaining the manufacturing process of the MESFET of FIG.

5 to 7, a first activation region layer 402 having a first electrical characteristic may be formed on the substrate 401 so as to form a Schottky junction with the gate electrode 406, and the first compartment may be formed. After the photoresist 409 is formed on the gate region on the torch region layer 402 through a photo process, the source / drain region portion of the first active region layer 402 is etched for the source and drain electrodes 404 and 405. .

A second activation region layer 403 may be formed on the source / drain regions except for the gate region of the first activation region layer 402, which may be an ohmic electrode junction with the source and drain electrodes 404 and 405. After the source and drain electrodes 404 and 405 are deposited on the layer 403, the photoresist 409, the second active region layer 403, and the source / drain electrodes 404 and 405 which are sequentially formed on the gate region by the above process are formed. The metal layers 403 and 404 formed during the removal are removed through a lift-off process to expose the channel portion.

In another photo process, a gate (metal) electrode 406 is deposited to form a Schottky gate so as to form a depletion region under the gate electrode 406. Thereafter, after forming the protective film 407 of the device, the MESFET device is finally manufactured by forming the contact electrode 408 through the contact hole.

The MESFET device according to the present embodiment includes a first active region layer 402 of the channel region existing under the gate and the junction between the source drain activation region, that is, the second activation region layer 403 and the source / drain electrodes 404 and 405. The junction between the gate electrodes 406 has a homojunction structure.

8 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with still another embodiment of the present invention, which is manufactured by a process different from that of FIG. 4.

As shown in FIG. 9, a MESFET according to another embodiment of the present invention is a substrate 801, a first formed on the substrate 801 to have first electrical characteristics by adjusting first process conditions including at least a gas atmosphere A second activation formed on the activation region layer 802 and the gate region defined in the first activation region layer 802 to have a second electrical characteristic different from the first electrical characteristic by adjusting a second process condition including at least a gas atmosphere; Source layer 803a and drain electrode 804b on source and drain regions defined in region layer 803, first activation region layer 802, and gate electrode 804c on second activation region layer 803. It includes.

In the present embodiment, the first process condition includes a gas atmosphere having a ratio of O ₂ / (Ar + O ₂ ) of 5% or more, and the second process condition has a ratio of O ₂ / (Ar + O ₂ ) of 5% Including the following gas atmosphere, the first activation region layer 802 exhibits ohmic junction characteristics with the source / drain electrodes 804a and 804b, and the second activation region layer 803 has the gate electrode 804c and the Schottky. The bonding properties can be exhibited.

In the present embodiment, the first and second activation region layers include at least one metal oxide of indium (In) oxide, gallium (Ga) oxide, zinc (Zn) oxide, aluminum (Al) and tin (Sn) oxide. The source electrode 804a, the drain electrode 804b, and the gate electrode 804c may be formed of the same metal layer of the same type.

In addition, in the present embodiment, the first and second activation region layers 402 and 403 may be formed of at least one metal of indium (In) oxide, gallium (Ga) oxide, zinc (Zn) oxide, aluminum (Al), and tin (Sn) oxide. It can be formed from an n-type or p-type oxide semiconductor containing an oxide.

Referring to FIG. 8, when depositing an activation region on a substrate 801, a predeposition condition (first process condition) is deposited into a first activation region layer 802 for source and drain junction, and a post deposition condition ( Second process conditions) are deposited into the second activation region layer 803 which can form a Schottky junction with the gate electrode. In the case of pre-deposition conditions (first process conditions), a condition in which an ohmic junction may be formed on the source and drain electrodes 804a and 804b, that is, a gas having an O ₂ / (Ar + O ₂ ) ratio of 5% or more in a vacuum process The first active region layer 802 is deposited in a thickness of 10 to 200 nm in the atmosphere. Subsequently, in the case of a later deposition condition (second process condition), the second activation region layer 803 is deposited under the second process condition so as to form a Schottky junction with the gate electrode by changing the deposition conditions in the same vacuum vessel as in the case of predeposition. do. Afterwards, a photoresist 804 is formed on the gate region by a pattern process to form an electrode, and then second activation is performed until the first active region layer 802 predeposited through a dry or wet etching method is exposed. The region layer 803 is etched. Subsequently, the same metal is deposited to form an ohmic junction at the source and drain electrodes 804a and 804b and a Schottky junction at the junction of the gate electrode 804c to finally fabricate the device.

10 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with still another embodiment of the present invention.

As shown in FIG. 10, a MOSFET according to an embodiment of the present invention may include a substrate 1001 and an activation region layer 1002 and an activation region layer formed by adjusting process conditions including at least a gas atmosphere on the substrate 1001. A source and drain electrode 1003 formed on the source region and the drain region of 1002, a gate insulating layer 1004 formed on the gate region defined on the activation region layer 1002, and a gate insulating layer 1004, respectively. Gate electrode 1005).

In the present embodiment, the gas atmosphere under the process conditions of the activation region layer 1002 is to adjust the ratio of O ₂ / (Ar + O ₂ ) to 5% or less, and the activation region layer 1002 is made of indium (In). Oxide, gallium (Ga) oxide, zinc (Zn) oxide, aluminum (Al) and tin (Sn) oxide may be made of one or more metal oxides, the active region layer 1002 may be formed of a thickness of 5nm to 200nm. . In addition, the gate insulating layer 1004 may be formed of a high dielectric material having a higher dielectric constant than SiO ₂ .

Referring to FIG. 10, when the ZnO-based active region layer 1002 is deposited on the substrate 1001, not only conditions suitable for forming a Schottky junction structure in the source and drain regions but also conditions suitable for basically operating as a transistor are shown. Or only the active portion of the source and drain electrode junctions so that a Schottky junction can be made. In addition, the thickness of the active region layer 1002 is formed to a thickness such that a Schottky junction portion can be formed in the source drain 1003 portion in the process. In order to form the source and drain 1003 on the substrate 1001 on which the activation region layer 1002 is formed, the activation region is etched after the pattern process, and then a metal is deposited to form the source and drain 1003. . The metal of the source and drain electrodes 1003 deposits a metal on which a Schottky barrier can be formed for the electrons to fabricate an n-type transistor. A Schottky barrier is formed on the junction between the metal source drain 1003 and the non-fabricated portion, and the transistor penetrates the junction barrier to perform on-off operation. After the pattern process is performed to form an insulating layer on the gate region of the active region layer 1002, the gate insulating layer 1004 is formed. The low-temperature process allows crystallization at a high temperature to induce a gate leakage current. HfO ₂ , AlO ₂ , and Zr ₂ O ₃ , which are dielectric materials, may be formed, and a gate electrode 1005 is formed thereon to fabricate a Schottky through transistor having a final MOSFET structure.

In addition, the terms "comprise", "comprise" or "having" described above mean that the corresponding component may be included, unless otherwise stated, and thus excludes other components. It should be construed that it may further include other components instead. All terms, including technical and scientific terms, have the same meanings as commonly understood by one of ordinary skill in the art unless otherwise defined. Terms commonly used, such as terms defined in a dictionary, should be interpreted to coincide with the contextual meaning of the related art, and shall not be construed in an ideal or excessively formal sense unless explicitly defined in the present invention.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the present invention.

As described above, the semiconductor device manufacturing method according to various embodiments of the present invention is applied to the technical field of manufacturing a semiconductor device such as a diode and a field effect transistor to change the electrical properties of the activation surface in contact with the metal Schottky junction In addition, by configuring an ohmic junction, not only does it improve the characteristics of a semiconductor device such as a Schottky junction diode and a transistor using the same, but also facilitates the selective use of a metal electrode through an existing process, and short-channel due to the miniaturization of the device. It is a very useful invention that solves such problems and can escape the existing silicon-based electronic devices.

1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

2 (a) and 2 (b) is a view showing the electrical characteristics of the semiconductor diode device according to an embodiment of the present invention,

3 is a view showing a characteristic change of an activation region through heat treatment characteristics;

4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment of the present invention, which is a metal semiconductor field-effect transistor (MESFET) having a metal and oxide semiconductor junction field effect transistor structure;

5 to 7 are cross-sectional views illustrating a manufacturing process of the MESFET of FIG. 4;

8 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with still another embodiment of the present invention.

10 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with still another embodiment of the present invention.

<Description of Symbols for Main Scenes in Drawings>

101,401,801,1001: substrate

102: cathode electrode

103,402,403,802,803,1002: active region layer (or oxide semiconductor layer)

104: metal anode electrode

404,405,804a, 804b, 1003: source / drain electrodes

406,804c, 1005: gate electrode

407: shield

408: contact electrode

409,804: photoresist

1004: gate insulating layer

Claims (20)

delete delete delete delete delete delete Forming a first activation region layer on a substrate, wherein controlling electrical characteristics of the first activation region layer by adjusting first process conditions including at least a gas atmosphere; A second activation region layer is formed on the source region and the drain region defined in the first activation region layer, and at least a second process condition including a gas atmosphere is adjusted to adjust the electrical characteristics of the second activation region layer. Adjusting differently from the active region layer; And Forming a source electrode and a drain electrode on the second activation region layer, and forming a gate electrode on the gate region defined in the first activation region layer; A semiconductor device manufacturing method comprising a. The method of claim 7, wherein Wherein said first process conditions comprise said gas atmosphere in which the ratio of O ₂ / (Ar + O ₂ ) is 5% or less at a pressure of 20 mTorr or less. The method of claim 7, wherein And the second process condition comprises the gas atmosphere in which the ratio of O ₂ / (Ar + O ₂ ) is 5% or more at a pressure of 20 mTorr or less. The method of claim 7, wherein The first and second activation region layers are n-type or p-containing at least one metal oxide of indium (In) oxide, gallium (Ga) oxide, zinc (Zn) oxide, aluminum (Al) and tin (Sn) oxide. A semiconductor device manufacturing method, characterized in that it is formed of a type oxide semiconductor. Forming a first activation region layer on a substrate, wherein controlling electrical characteristics of the first activation region layer by adjusting first process conditions including at least a gas atmosphere; A second activation region layer is formed on the gate region defined in the first activation region layer, and the electrical characteristics of the second activation region layer are controlled by adjusting a second process condition including at least a gas atmosphere. Adjusting differently from the layers; And Forming a source electrode and a drain electrode on the source region and the drain region defined in the first activation region layer, and forming a gate electrode on the second activation region layer; A semiconductor device manufacturing method comprising a. The method of claim 11, The gas atmosphere of the first process conditions is a semiconductor device manufacturing method, characterized in that to adjust the ratio of O ₂ / (Ar + O ₂ ) to 5% or more. The method of claim 11, The gas atmosphere of the second process conditions is a semiconductor device manufacturing method, characterized in that to adjust the ratio of O ₂ / (Ar + O ₂ ) to 5% or less. The method of claim 11, The first and second activation region layers are n-type or p-containing at least one metal oxide of indium (In) oxide, gallium (Ga) oxide, zinc (Zn) oxide, aluminum (Al) and tin (Sn) oxide. A semiconductor device manufacturing method, characterized in that it is formed of a type oxide semiconductor. The method of claim 11, And the source electrode, the drain electrode, and the gate electrode are formed by the same metal layer. Forming an activation region layer on the substrate, wherein the process conditions including at least a gas atmosphere are adjusted to control electrical characteristics of at least source and drain regions defined in the activation region layer; Forming a source electrode and a drain electrode on the source region and the drain region, respectively; Forming a gate insulating layer on the gate region defined on the activation region layer; And Forming a gate electrode on the gate insulating layer; A semiconductor device manufacturing method comprising a. The method of claim 16, Under the process conditions, the gas atmosphere is a method of manufacturing a semiconductor device, characterized in that to adjust the ratio of O ₂ / (Ar + O ₂ ) to 5% or less. The method of claim 16, The activation region layer is a semiconductor device manufacturing method, characterized in that made of at least one metal oxide of indium (In) oxide, gallium (Ga) oxide, zinc (Zn) oxide, aluminum (Al) and tin (Sn) oxide. The method of claim 16, The activation region layer is a semiconductor device manufacturing method, characterized in that made of a thickness of 5nm ~ 200nm. The method of claim 16, The gate insulating layer is a semiconductor device manufacturing method, characterized in that made of a high dielectric material having a larger dielectric constant than SiO ₂ .

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