KR101002337B1 - LCD and its manufacturing method - Google Patents

Abstract

It is possible to reduce the misalignment caused by the asymmetrical design of the pixel, and to control the abnormal behavior of the liquid crystal due to the asymmetrical electric field by configuring the entire pixel to be symmetrical up, down, left, and right. To provide a liquid crystal display device and a method of manufacturing the same that can reduce the defect rate due to the reduction and increase the pixel design freedom in the design of the pen tile by changing the size of the adjacent pixel region, to achieve the above object The liquid crystal display device comprises: a gate line arranged in one direction on a substrate and having first and second gate electrodes defined in one region; A common data line intersecting with the gate line and arranged to divide and define one unit pixel area into four first to fourth sub-pixel areas; First and second active layers formed on the first and second gate electrodes and separated from each other; A plurality of thin film transistors disposed on the gate line and the common data line so as to be symmetrical with the common source electrode and the first and second drain electrodes; An interlayer insulating film formed on the entire surface of the substrate to have first to fourth contact holes in upper and lower regions of the first and second drain electrodes, respectively; A first first contacting the first drain electrode through the first and second contact holes and contacting the second drain electrode through the third and fourth contact holes respectively formed in the first to fourth sub-pixel regions To fourth pixel electrodes.

Common source electrode, pixel

Description

Liquid Crystal Display Device and method for fabricating the same

1 is a plan view showing a unit pixel of a typical TN liquid crystal display device

2 is a plan view of a liquid crystal display according to a first embodiment of the present invention.

3 is a cross-sectional view taken along line II ′ and II-II ′ of FIG. 2;

4A to 4C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

FIG. 5 is an exemplary view of changing a sub-pixel size of a liquid crystal display having the configuration of FIG. 2. FIG.

6 is a plan view of a liquid crystal display according to a second exemplary embodiment of the present invention.

7 is a cross-sectional view taken along line III-III ′ and IV-IV ′ of FIG. 6.

8A to 8C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a second embodiment of the present invention.

9 is a view illustrating a sub-pixel size change of a liquid crystal display having the configuration of FIG.

10 is a plan view of a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along line VV ′ of FIG. 10.                 

12A to 12C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a third embodiment of the present invention.

13 is a plan view of a liquid crystal display according to a fourth embodiment of the present invention.

FIG. 14 is a cross-sectional view taken along line VI-VI ′ and VII-VII ′ of FIG. 13;

15A to 15C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a fourth embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

40, 80, 100, 130: lower substrate 41, 81, 101, 131: gate line

41a, 81a, 101a, 1031a: first gate electrode

41b, 81b, 101b, and 131b: second gate electrode

42, 82, 102, 132: gate insulating films 43a, 83a: first active layer

43b, 83b: second active layer 43c, 133a: ohmic contact layer

44, 84: common data lines 44a, 134a: common source electrode

44b, 84c, 104b, 134b: first drain electrode

44c, 84d, 104c, 134c: second drain electrode

45, 105: interlayer insulating film

46a, 46b, 46c, 46d: 1st, 2nd, 3rd, 4th contact hole

47a, 85a, 107a, 135a: first pixel electrode

47b, 85b, 107b, 135b: second pixel electrode

47c, 85c: third pixel electrode 47d, 85d: fourth pixel electrode                 

48a, 86a, 108a, 136a: first storage electrode

48b, 86b, 108b, 136b: second storage electrode

48c, 86c: third storage electrode 48d, 86d: fourth storage electrode

81c, 101c, and 131c: first common wiring 81d, 101d, and 131d: second common wiring

81e, 131e: common electrode

84a and 84b: first and second source electrodes 103 and 133: active layer

104, 134: data lines 106a, 106b: first and second contact holes

104a, 134a: source electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same, which are configured such that all pixels are symmetric in up, down, left and right, and which can increase the degree of freedom in pixel design.

As the information society develops, the demand for display devices is increasing in various forms.In recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent display (VFD) have been developed. Various flat panel display devices have been studied, and some are already used as display devices in various equipment.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness and low power consumption. In addition, it is being developed in various ways, such as a television for receiving and displaying broadcast signals, and a monitor of a computer.

As described above, although various technical advances have been made in order for the liquid crystal display device to serve as a screen display device in various fields, the task of improving the image quality as the screen display device has many advantages and disadvantages.

Therefore, in order to use a liquid crystal display device in various parts as a general screen display device, the key to development is how much high definition images such as high definition, high brightness, and large area can be realized while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

Such a liquid crystal display device may be broadly divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates having a space and are bonded to each other; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.

The first glass substrate (TFT array substrate) may include a plurality of gate lines arranged in one direction at a predetermined interval, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing each gate line and a data line and a plurality of pixels which are switched by signals of the gate line to transfer the signal of the data line to each pixel electrode. A thin film transistor is formed.

The second glass substrate (color filter substrate) includes a black matrix layer for blocking light in portions other than the pixel region, an R, G, B color filter layer for expressing color colors, and a common electrode for implementing an image. Is formed. Of course, the common electrode is formed on the first glass substrate in the transverse electric field type liquid crystal display device.

The first and second glass substrates are bonded by a sealing material having a predetermined space by a spacer and having a liquid crystal injection hole, and a liquid crystal is injected between the two substrates.

In this case, in the liquid crystal injection method, the liquid crystal is injected between the two substrates by osmotic pressure when the liquid crystal injection hole is immersed in the liquid crystal container by maintaining the vacuum state between the two substrates bonded by the reality. When the liquid crystal is injected as described above, the liquid crystal injection hole is sealed with a sealing material.

On the other hand, the driving principle of the liquid crystal display device as described above uses the optical anisotropy and polarization of the liquid crystal.

Since the liquid crystal is thin and long in structure, the liquid crystal has a direction in the arrangement of molecules, and the liquid crystal may be artificially applied to control the direction of the molecular arrangement.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light polarized by optical anisotropy may be arbitrarily modulated to display image information.

Such liquid crystals may be classified into positive liquid crystals having a positive dielectric anisotropy and negative liquid crystals having a negative dielectric anisotropy according to an electrical specific classification, and liquid crystal molecules having a positive dielectric anisotropy are long axes of liquid crystal molecules in a direction in which electric fields are applied. The liquid crystal molecules arranged in parallel and having negative dielectric anisotropy are arranged perpendicularly to the direction in which the electric field is applied and the major axis of the liquid crystal molecules.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is a plan view illustrating unit pixels of a general TN liquid crystal display.

In the liquid crystal display according to the related art, as shown in FIG. 1, a gate line 11 and a data line 13 are alternately arranged in a lower substrate (not shown) to define a pixel region P. A pixel electrode 15 is formed in each pixel region P where the gate line 11 and the data line 13 cross each other, and a thin film is formed at a portion where the gate line 11 and the data line 13 cross each other. The transistor is formed.

The thin film transistor includes a gate electrode 11a defined in one region of the gate line 11, a gate insulating film (not shown) formed on the front surface, and an active layer 12 formed on the gate insulating film above the gate electrode 11a. And a source electrode 13a defined in one region of the data line 13 crossing the gate line 11 and overlapping an upper portion of the active layer 12, and spaced apart from the source electrode 13a. The drain electrode 13b overlaps with the other side of the active layer 12.                         

A thick insulating film (not shown) is formed on an entire surface of the lower substrate above the thin film transistor, and a contact hole 14 is formed to expose one region of the drain electrode 13b.

The pixel electrode 15 is formed in the pixel region to be in contact with the drain electrode 13b through the contact hole 14.

In this case, the pixel electrode 15 is made of a transparent conductive metal having excellent light transmittance, such as indium-tin-oxide (ITO).

The storage electrode 15a extending from the pixel electrode 15 is formed on the gate line 11 of the previous stage.

Although not shown in the drawing, the upper substrate facing the lower substrate includes a black matrix layer for blocking light of portions except the pixel region P, and an R, G, B color filter layer for expressing color colors. And a common electrode for realizing an image are formed.

However, such a conventional liquid crystal display device has an asymmetrical structure in which one thin film transistor is located at one corner of the top, bottom, left, and right sides of one pixel area, and one storage electrode is formed at one end of one pixel area. Since it is designed, a misalignment problem may occur, and an abnormal behavior of the liquid crystal may occur due to an asymmetric electric field.

In addition, when a defect occurs in one thin film transistor and a storage electrode, a bright point or a dark point defect of one pixel area may occur. As a result, the yield may be reduced.

The present invention has been made to solve the above problems, and an object of the present invention is to configure the entire pixel to be symmetrical up, down, left, and right to reduce the misalignment problem caused by the asymmetric design of the pixel, and also the liquid crystal by the asymmetric electric field An object of the present invention is to provide a liquid crystal display and a method for manufacturing the same.

Another object of the present invention is to provide a liquid crystal display device and a method for manufacturing the same, which can reduce the defective rate due to the size of the bright spot or dark spot due to the process defect by configuring the entire pixel to be symmetrical up, down, left and right.

It is still another object of the present invention to provide a liquid crystal display device and a method of manufacturing the same, which can increase the pixel design freedom when designing a pen tile or the like by changing the size of a neighboring pixel region.

According to an aspect of the present invention, there is provided an LCD device including: a gate line arranged in one direction on a substrate and having first and second gate electrodes defined in one region; A common data line intersecting with the gate line and arranged to divide and define one unit pixel area into four first to fourth sub-pixel areas; First and second active layers formed on the first and second gate electrodes and separated from each other; A plurality of thin film transistors disposed on the gate line and the common data line so as to be symmetrical with the common source electrode and the first and second drain electrodes; An interlayer insulating film formed on the entire surface of the substrate to have first to fourth contact holes in upper and lower regions of the first and second drain electrodes, respectively; A first first contacting the first drain electrode through the first and second contact holes and contacting the second drain electrode through the third and fourth contact holes respectively formed in the first to fourth sub-pixel regions To fourth pixel electrodes.

And first to fourth storage electrodes respectively formed in the first to fourth sub-pixel areas so as to overlap the upper part of the gate line before and after the gate line.

The first to fourth storage electrodes may extend from the first to fourth pixel electrodes.

The common source electrode is defined in one region of the common data line crossing the gate line, and overlaps the upper portion of one side of the first and second active layers.

The first and second drain electrodes may be spaced apart from the common source electrode at predetermined intervals and overlap the upper portions of the other sides of the first and second active layers.

An ohmic contact layer may be further formed between the first and second drain electrodes and the first and second active layers.

The first and second drain electrodes may be formed in the common data line direction.

The first drain electrode is used as a drain electrode in the first and second sub-pixel regions, and the second drain electrode is used as a drain electrode in the third and fourth sub-pixel regions.

The common data line and the common source electrode may be commonly used in the first to fourth sub-pixel areas.

The first to fourth sub-pixel areas are divided into equal areas by the common data line.

The first to fourth sub-pixel areas may be divided to have different areas by the common data line.

The common data line may be arranged such that an area of the third and fourth subpixel areas of the upper and lower left portions is equally narrower or wider than an area of the first and second subpixel areas of the upper and lower right portions. It is characterized by.

One unit pixel area including the four first to fourth sub-pixel areas may have different areas.

Each of the unit pixel areas may be implemented with one R, G, or B pixel.

According to another exemplary embodiment of the present invention, a liquid crystal display device includes: a gate line arranged in one direction on a substrate and having first and second gate electrodes defined in one region; A common data line perpendicular to the gate line, the common data line arranged to divide and define one unit pixel area into first to fourth sub pixel areas on left and right sides; First and second common lines arranged at upper and lower ends of the gate line and spaced apart from the gate line; A plurality of common electrodes formed in the first to fourth sub pixel regions in a direction perpendicular to the gate line; First and second active layers formed on the first and second gate electrodes and separated from each other; First and second source electrodes protruding to the left and right sides of the common data line and overlapping one side of the first and second active layers; First and second drain electrodes spaced apart from the first and second source electrodes at predetermined intervals and overlapped on upper portions of the first and second active layers, respectively; And first to fourth pixel electrodes formed between the common electrodes of the first to fourth sub-pixel regions so as to be connected to the first and second drain electrodes.

The liquid crystal display may further include first to fourth storage electrodes overlapping the upper portions of the upper and lower ends of the first to second common lines.

The first to fourth storage electrodes may extend from the first to fourth pixel electrodes, and the first to fourth pixel electrodes may extend from the first and second drain electrodes.

The first and second common lines and the common electrode are formed on the same layer as the gate line, and the plurality of common electrodes extend from one side of the first and second common lines.

The common data line and the first to fourth pixel electrodes may be formed of an opaque metal, and may be indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IN). IZO) or Indium Tin Zinc Oxide (ITZO).                     

The first gate electrode, the first source electrode, and the first drain electrode constitute a first thin film transistor, and the second gate electrode, the second source electrode, and the second drain electrode constitute a second thin film transistor. It is characterized by.

The first thin film transistor is shared in the first and second sub-pixel regions, and the second thin film transistor is shared in the third and fourth sub-pixel regions.

The first to fourth sub-pixel areas are divided into equal areas by the common data line.

The first to fourth sub-pixel areas may be divided to have different areas by the common data line.

One unit pixel area including the first to fourth sub-pixel areas may include different areas.

Each of the unit pixel areas may be implemented with one R, G, or B pixel.

According to another exemplary embodiment of the present invention, a liquid crystal display includes: a plurality of gate lines and data lines arranged on a substrate to define first and second pixel regions adjacent to upper and lower portions thereof; First and second common wires arranged spaced apart before and after the gate line; First and second thin film transistors formed in a cross shape at portions where the gate lines and the data lines cross each other; First and second pixel electrodes formed on the first and second pixel areas; And first and second storage electrodes extending from the first and second pixel electrodes and formed on the first and second common lines.

The first and second thin film transistors may include first and second gate electrodes protruding above and below the gate line, a gate insulating film formed on an entire surface of the substrate including the first and second gate electrodes, and the first and second gate electrodes. An active layer formed on the gate insulating layer on the first and second gate electrodes, a common source electrode protruding from the data line and overlapping the center of the active layer, and spaced apart from the common source electrode and on both sides of the active layer; And first and second drain electrodes overlapped with each other.

The first and second drain electrodes may be formed in the same direction (horizontal direction) as the gate line.

An interlayer insulating film having first and second contact holes formed in one region of the first and second drain electrodes may be further formed on an entire surface of the substrate including the first and second thin film transistors.

The first and second pixel electrodes may be in contact with the first and second drain electrodes through the first and second contact holes.

The first and second pixel electrodes may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (Indium tin zinc oxide). It is characterized in that it is composed of a transparent metal such as ITZO).

According to another exemplary embodiment of the present invention, a liquid crystal display includes: a plurality of gate lines and data lines arranged on a substrate to define first and second pixel regions adjacent to upper and lower portions thereof; First and second common wires arranged spaced apart before and after the gate line; A plurality of common electrodes formed in the first and second pixel regions in a direction perpendicular to the gate line; First and second thin film transistors formed in a cross shape at portions where the gate lines and the data lines cross each other; First and second pixel electrodes arranged between the common electrodes of the first and second pixel regions; And first and second storage electrodes overlapped on the first to second common lines.

The first and second thin film transistors may include first and second gate electrodes protruding above and below the gate line, a gate insulating film formed on an entire surface of the substrate including the gate line, and the first and second thin film transistors. An active layer formed in an island shape on the gate insulating layer above the gate electrode, a common source electrode protruding from one side of the data line and overlapping an upper portion of the center of the active layer, and spaced apart from the common source electrode at a predetermined interval. The first and second drain electrodes overlapping the upper and lower sides of the layer, respectively.

The first and second drain electrodes may be formed in the same direction (horizontal direction) as the gate line.

The first and second storage electrodes may extend from the first and second pixel electrodes, and the first and second pixel electrodes may extend from the first and second drain electrodes.

The first and second common wirings and the common electrode may be formed on the same layer as the gate line.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, the method comprising: forming a gate line in one region on a substrate and defining first and second gate electrodes in one region; Forming first and second active layers on the first and second gate electrodes so as to be isolated from each other; Forming a common data line intersecting with the gate line and defining a unit pixel area divided into four first to fourth sub-pixel areas; Forming a plurality of thin film transistors including a common source electrode and first and second drain electrodes in first to fourth sub-pixel regions intersecting the gate line and the common data line; Forming an interlayer insulating film on an entire surface of the substrate to have first to fourth contact holes in upper and lower regions of the first and second drain electrodes, respectively; First to fourth sub-pixel regions respectively contacted to the first drain electrode through the first and second contact holes, and contacted to the second drain electrode through the third and fourth contact holes. Forming a fourth pixel electrode; And forming first to fourth storage electrodes to overlap the upper part of the gate line before and after the gate line.

The first to fourth storage electrodes may be formed simultaneously with the first to fourth pixel electrodes.

The first and second drain electrodes may be formed in the same direction (up and down direction) with the common data line to cover the first to fourth sub pixel areas.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, the method including: forming a gate line arranged in one direction on a substrate and defining first and second gate electrodes in one region; Forming first and second common wires on upper and lower ends of the gate line and spaced apart from the gate line; Forming a plurality of common electrodes in first to fourth sub pixel regions in a direction perpendicular to the gate line; Forming first and second active layers on the first and second gate electrodes so as to be isolated from each other; Forming a common data line vertically intersecting with the gate line to define a unit pixel area divided into first to fourth sub pixel areas in left and right sides; Forming first and second source electrodes protruding from left and right sides of the common data line so as to overlap one side of the first and second active layers; Forming first and second drain electrodes spaced apart from the first and second source electrodes at predetermined intervals and overlap the upper portions of the first and second active layers, respectively; Forming first to fourth pixel electrodes in first to fourth sub-pixel regions so as to be disposed between the common electrodes; First to fourth storage electrodes are formed on the gate line so as to overlap the upper portion of the first to second common lines.

The gate line, the first and second common lines, and the common electrodes may be formed on the same layer.

The first and second drain electrodes, the first to fourth pixel electrodes, and the first to fourth storage electrodes may be formed on the same layer.

According to still another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including forming a plurality of gate lines defining first and second gate electrodes protruding upward and downward on a substrate; Forming first and second common lines to be spaced apart before and after the gate line; Forming a gate insulating film on an entire surface of the substrate including the first and second gate electrodes; Forming an active layer on the gate insulating layer on the first and second gate electrodes; Forming a plurality of data lines arranged to intersect the gate line to define first and second pixel areas adjacent to upper and lower parts thereof; Forming a common source electrode protruding from the data line and overlapping the center upper portion of the active layer; Forming first and second drain electrodes spaced apart from the common source electrode and arranged in a horizontal direction on both sides of the active layer; Forming first and second pixel electrodes in the first and second pixel regions so as to be connected to the first and second drain electrodes, respectively; First and second storage electrodes may be formed to extend from the first and second pixel electrodes to overlap the upper portions of the first and second common lines.

The gate line and the first and second common lines may be formed on the same layer.

The first and second pixel electrodes and the first and second storage electrodes may be formed on the same layer.

According to still another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including forming a plurality of gate lines defining first and second gate electrodes protruding upward and downward on a substrate; Forming first and second common lines to be spaced apart before and after the gate line; Forming a plurality of common electrodes in first and second pixel regions in a direction perpendicular to the gate line; Forming a gate insulating film on an entire surface of the substrate including the gate line; Forming an active layer on the gate insulating layer on the first and second gate electrodes; Forming a common source electrode to protrude from one side of the data line and to overlap the center upper portion of the active layer; Forming first and second drain electrodes horizontally spaced apart from the common source electrode at upper and lower sides of the active layer in a horizontal direction; Forming first and second pixel electrodes in the first and second pixel areas so as to be arranged between the common electrodes; The first and second storage electrodes may be formed to overlap the first and second common lines.

The gate line, the first and second common wirings and the common electrodes may be formed on the same layer.

The first and second drain electrodes, the first and second pixel electrodes, and the first and second storage electrodes may be formed on the same layer.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First embodiment

First, the configuration of the liquid crystal display device according to the first embodiment of the present invention will be described.

FIG. 2 is a plan view of a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view of the structure taken along lines II ′ and II-II ′ of FIG. 2.                     

FIG. 5 is an exemplary diagram of changing a sub-pixel size of the liquid crystal display having the configuration of FIG. 2.

In the liquid crystal display according to the first exemplary embodiment of the present invention, as shown in FIGS. 2 and 3, the gate line 41 arranged in one direction on the transparent lower substrate 40 and the gate line 41 of the gate line 41 are formed. A first and second gate electrodes 41a and 41b defined in one region, a gate insulating layer 42 formed of a material such as SiNx or SiOx on the entire surface of the lower substrate 40 including the gate line 41, First and second active layers 43a and 43b formed in an island shape on the gate insulating layer 42 on the first and second gate electrodes 41a and 41b and in a central portion defined by one pixel area. A common data line 44 intersecting with the gate line 41 and a region of the data line 44 intersecting with the gate line 41 and defined in the first and second active layers 43a. The first and second common source electrodes 44a overlapped with one side of 43b and spaced apart from the common source electrode 44a by a predetermined interval. First and second contact holes 46a in the upper and lower regions of the first and second drain electrodes 44b and 44c overlapping the other sides of the TV layers 43a and 43b and the first drain electrode 44b. , 46b and a front surface of the lower substrate 40 including the common data line 44 to have third and fourth contact holes 46c and 46d in upper and lower regions of the second drain electrode 44c. Contacting the first drain electrode 44b through the formed interlayer insulating layer 45 and the first and second contact holes 46a and 46b, and through the third and fourth contact holes 46c and 46d. The first to fourth pixel electrodes 47a, 47b, 47c, and 47d are formed in each sub-pixel region so as to contact the second drain electrode 44c.

An ohmic contact layer 43c is further formed between the first and second drain electrodes 44b and 44c and the first and second active layers 43a and 43b.

The first and second drain electrodes 44b and 44c are formed to extend across the first to fourth subpixel regions.

Although not shown in the drawing, an alignment film (not shown) made of polyimide is formed on the entire surface of the lower substrate 40.

One unit pixel area is divided into four sub-pixel areas (first to fourth sub-pixel areas) by being divided by the gate line 41 and the common data line 44.

As described above, the common data line 44 and the common source electrode 44a are commonly used in four sub-pixel regions, and the first drain electrode 44b is formed toward the common data line 44. The first and second sub-pixel regions are respectively used as drain electrodes, and the second drain electrode 44c is formed toward the common data line 44 to be used as drain electrodes in the third and fourth sub-pixel regions, respectively. do.

In addition, the first to fourth pixel electrodes 47a, 47b, 47c, and 47d extend above and after the gate lines, and are divided so as to be vertically symmetrical at the end of each subpixel region, and thus, the first to fourth storages. Electrodes 48a, 48b, 48c and 48d are formed.

As described above, the first and second drain electrodes 44b and 44c protrude upward and downward on the left side of the common data line 44 and upward and downward on the right side of the common data line 44. Since the electrodes 48a, 48b, 48c, and 48d are divided so as to be symmetrical up, down, left, and right at each end of the 1 pixel region, the entire 1 pixel is designed to be symmetric up, down, left, and right.

In addition, as described above, the first exemplary embodiment of the present invention relates to a TN liquid crystal display device, in which one unit pixel region includes one thin film transistor (TFT), one storage electrode, and one pixel electrode. Rather, it consists of four TFTs, four storage electrodes and four pixel electrodes. Therefore, when a failure occurs, the entire pixel does not become inoperable. Therefore, even if a point defect occurs, it is unlikely to be recognized, thereby preventing a decrease in yield. In the above, the four TFTs are designed to be symmetrical.

In addition, the liquid crystal display of the present invention having the above configuration may be configured by changing the size of the sub-pixel region without changing the pixel pitch.

That is, the first to fourth subpixel regions are not divided into equal parts by the common data line 44, but the third and fourth subpixel regions on the upper right and lower sides of the first and second subpixel regions on the upper left and lower sides are not divided. It may be formed by boiling to have a wider or narrower area.

For example, when a blue pixel is designed to be approximately 50% wider than a red pixel, as shown in FIG. 5, the third and fourth sub-pixel areas positioned on the upper right and lower sides of the one pixel area in which the red pixel is formed are located on the upper left and lower sides. Designed to have a width twice as large as the first and second sub-pixel regions located at, and the first to fourth sub-pixel regions of the one-pixel region where the blue pixel is formed are the first and second sub-pixel regions of the red pixel region. It should be designed to have the same area as.                     

One unit pixel area including the first to fourth sub-pixel areas implements one R, G, or B pixel, respectively.

The liquid crystal display configured as described above is easy to implement in a technology such as a pentile having different RGB pixel sizes.

Next, a manufacturing method of the liquid crystal display device according to the first embodiment of the present invention having the above configuration will be described.

4A to 4C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

In the method of manufacturing the liquid crystal display device according to the first embodiment of the present invention, as shown in FIG. 4A, the conductive metal is deposited on the transparent lower substrate 40, and the conductive metal is patterned using photo and etching processes. Thus, the gate lines 41 arranged in one direction are formed. In this case, first and second gate electrodes 41a and 41b are defined in one region of the gate line 41.

Thereafter, the gate insulating layer 42 is formed on the entire surface of the lower substrate 40 on which the gate line 41 is formed.

The gate insulating layer 42 may use a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ).

Thereafter, a semiconductor layer (amorphous silicon + impurity amorphous silicon) is formed on the gate insulating layer 42.                     

Subsequently, the semiconductor layer is patterned by photo and etching processes to form first and second active layers 43a and 43b having an island shape on the first and second gate electrodes 41a and 41b. do.

Thereafter, as shown in FIG. 4B, a conductive metal is deposited on the entire surface of the lower substrate 40 on which the first and second active layers 43a and 43b are formed and patterned through a photo and etching process to form the gate line. A common data line 44 is formed to intersect with the 41, and first and second drain electrodes 44b and 44c are formed at left and right sides to be separated from the common data line 44 by a predetermined distance.

In this case, a common source electrode 44a is formed at a portion of the data line 44 crossing the gate line 41. The first and second drain electrodes 44b and 44c are formed in the same direction (the vertical direction) with the common data line 44 so as to extend across the first to fourth subpixel regions.

The common data line 44 is formed to overlap each side of the first and second active layers 43a and 43b, and the first and second drain electrodes 44b and 44c are formed of the first and second active layers. It is formed so as to overlap the other side of (43a, 43b), respectively. When the common data line 44 and the first and second drain electrodes 44b and 44c are etched, the impurity amorphous silicon layer is overetched to form the common data line 44 and the first and second drain electrodes. An ohmic contact layer 43c is formed between the portions 44b and 44c and the first and second active layers 43a and 43b, respectively.

As in the above process, the gate line 41 and the common data line 44 are formed to cross each other to divide one pixel area into four first to fourth sub-pixel areas, and four thin films on the top, bottom, left and right of the intersection. Form a transistor.

Thereafter, the interlayer insulating layer 45 is deposited on the entire surface of the lower substrate 40 on which the common data line 44 is formed. In this case, the interlayer insulating layer 45 may be formed using at least one of an oxide film, a nitride film, photoacryl, polyimide, and benzocyclobutene (BCB).

Subsequently, the interlayer insulating layer 45 is etched to expose the upper and lower regions of the first and second drain electrodes 44b and 44c positioned in the first to fourth sub-pixel regions to expose the first to fourth contact holes ( 46a, 46b, 46c, 46d).

Subsequently, as illustrated in FIG. 4C, after the transparent conductive film is deposited on the interlayer insulating layer 45, the transparent conductive film is selectively removed through a photo and etching process to form first to fourth contact holes 46a and 46b, First to fourth pixel electrodes 47a, 47b, 47c, and 47d are formed in the first to fourth sub-pixel regions to contact the first and second drain electrodes 44b and 44c through 46c and 46d. .

In addition, the transparent conductive layer is formed to overlap the upper and / or later gate lines to form first to fourth storage electrodes 48a, 48b, 48c, and 48d.

The storage capacitor of the present invention formed by the above method has a storage on gate structure.

The transparent conductive film may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). Can be formed.

Subsequently, although not shown in the drawing, an alignment layer made of polyimide or a photo-alignment material is formed on the entire surface of the lower substrate 40 including the first to fourth pixel electrodes 47a, 47b, 47c, and 47d.

Here, the alignment layer made of polyimide is determined by mechanical rubbing, and the photoreactive material made of polyvinylcinnamate based material or polysiloxane based material is oriented by irradiation with light such as ultraviolet rays. This is determined.

At this time, the orientation direction is determined by the irradiation direction of the light or the property of the irradiated light, that is, the polarization direction.

Second embodiment

First, the configuration of the liquid crystal display device according to the second embodiment of the present invention will be described.

6 is a plan view of a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view of the structure taken along line III-III ′ and IV-IV ′ of FIG. 6.

FIG. 9 is an exemplary diagram of sub-pixel size change of the liquid crystal display having the configuration of FIG. 6.

6 and 7, the liquid crystal display according to the second exemplary embodiment of the present invention includes a gate line 81 arranged in one direction on a transparent lower substrate 80, and the gate line 81. A common data line 84 defining first to fourth sub-pixel regions at right and left sides up and down perpendicularly to the first and second gate electrodes 81a and 81b defined in one region of the gate line 81. And first and second common wirings 81c and 81d arranged in parallel on and under the same layer as the gate line 81, and one side of the first and second common wirings 81c and 81d. Extends from the plurality of common electrodes 81e formed in the first to fourth sub-pixel regions in a direction perpendicular to the gate line 81 and on the front surface of the lower substrate 80 including the gate line 81. A gate insulating layer 82 formed of a material such as SiNx or SiOx, and the gates above the first and second gate electrodes 81a and 81b. The first and second active layers 83a and 83b formed in an island shape on the insulating layer 82 and the left and right sides of the common data line 84 protrude from the first and second active layers 83a and 83b. ) Is spaced apart from the first and second source electrodes 84a and 84b and the first and second source electrodes 84a and 84b at regular intervals and overlap the first and second active layers 83a and 83b. ) Extends from the first and second drain electrodes 84c and 84d and the first and second drain electrodes 84c and 84d respectively overlapped with the other side of Upper and lower ends extending from the first to fourth pixel electrodes 85a, 85b, 85c and 85d formed between the electrodes 81e and the first to fourth pixel electrodes 85a, 85b, 85c and 85d. And first to fourth storage electrodes 86a, 86b, 86c, and 86d overlapping the first to second common wires 81c and 81d.

Although not shown in the drawing, an alignment film (not shown) made of polyimide is formed on the entire surface of the lower substrate 80.

First to fourth storage electrodes extending from the first to fourth pixel electrodes 85a, 85b, 85c, and 85d on the gate insulating layer 82 on the first and second common lines 81c and 81d. Since 86a, 86b, 86c, and 86d are formed, the storage capacitor of the present invention has a storage on common structure.

The first and second common lines 81c and 81d and the common electrode 81e are formed on the same layer as the gate line 81.

The common data line 84 and the first to fourth pixel electrodes 85a, 85b, 85c, and 85d may be formed of an opaque metal, and may be indium tin oxide (ITO) or tin oxide (Tin Oxide). It may be composed of a transparent metal such as TO), Indium Zinc Oxide (IZO) or Indium Tin Zinc Oxide (ITZO).

The common electrode 81e adjacent to the common data line 84 among the common electrodes 81e is formed to have a small distance from the common data line 84. In this manner, light leakage due to distortion of the liquid crystal alignment state between the common data line 84 and the common electrode 81e can be reduced.

In the above description, the first gate electrode 81a, the first source electrode 84a, and the first drain electrode 84c constitute the first thin film transistor, and the second gate electrode 81b and the second source electrode 84b The second drain electrode 84d constitutes a second thin film transistor.

The first thin film transistor also operates as a switching transistor for driving the first and second sub-pixel regions, and the second thin film transistor operates as a switching transistor for driving the third and fourth sub-pixel regions. That is, the first thin film transistor is shared in the first and second sub-pixel regions, and the second thin film transistor is shared in the third and fourth sub-pixel regions. The first and second thin film transistors are configured to be symmetrical left and right.

As described above, the first thin film transistor is shared in the first and second sub pixel regions, respectively, and the second thin film transistor is shared in the third and fourth sub pixel regions, respectively, and the first to fourth storage electrodes 86a are provided. Since 86b, 86c, and 86d are divided so as to be symmetrical at the end of one pixel area, the entire pixel is designed to be symmetrical.

In addition, the second embodiment of the present invention is a transverse electric field type liquid crystal display device, wherein one pixel region is composed of one thin film transistor (TFT), one storage electrode, one pixel electrode, and a common electrode. Rather, substantially one pixel region is divided into four sub-pixel regions, and consists of two TFTs, four storage electrodes and four pixel electrodes to operate. Therefore, when a failure occurs, the entire pixel does not become inoperable. Therefore, even if a point defect occurs, it is unlikely to be recognized, thereby preventing a decrease in yield.

Next, the liquid crystal display of the present invention configured as described above may be configured by changing the size of the sub-pixel region without changing the pixel pitch as shown in FIG.

That is, the sub pixel areas are not divided into equal areas by the common data line 84 and the gate line 81, but the sub pixel areas of the upper and lower right portions have a larger area than the sub pixel areas of the upper left and lower parts. It may be formed by boiling.                     

For example, if a blue pixel is designed to be approximately 50% wider than a red pixel, as shown in FIG. 9, the upper and lower left portions of the third and fourth sub-pixel regions located at the upper right and lower sides of the one pixel area where the red pixel is formed are shown in FIG. 9. Designed to have a width twice as large as the first and second sub-pixel regions located at, and the first to fourth sub-pixel regions of the one-pixel region where the blue pixel is formed are the first and second sub-pixel regions of the red pixel region. It should be designed to have the same area as.

In this case, the common electrode 81e of the blue pixel is increased by one more line than the red pixel, and the third and fourth pixel electrodes 85c and 85d are arranged by one more line between the common electrodes 81e. The third and fourth storage electrodes 86c and 86d are further formed on the first and second common wirings 81c and 81d of the blue pixel portion.

Such a configuration is easy to implement in a technology such as a pentile having different RGB pixel sizes.

Next, a manufacturing method of the liquid crystal display device according to the second embodiment of the present invention having the above configuration will be described.

8A through 8C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a second embodiment of the present invention.

In the method of manufacturing the liquid crystal display according to the second exemplary embodiment of the present invention, as shown in FIG. 8A, the conductive metal is deposited on the transparent lower substrate 80, and the conductive metal is patterned using photo and etching processes. The gate lines 81 arranged in one direction are formed. In this case, first and second gate electrodes 81a and 81b are defined in one region of the gate line 81.

In addition, first and second common wirings 81c and 81d are formed at upper and lower portions of the same layer as the gate line 81 in the same material to be arranged in a direction parallel to the gate line 81.

At the same time, a plurality of common electrodes 81e are disposed in the first to fourth sub-pixel regions, which will be described later to extend from one side of the first and second common lines 81c and 81d to have a direction perpendicular to the gate line 81. ).

Thereafter, as shown in FIG. 8B, a gate insulating layer 82 is formed on the entire surface of the lower substrate 80 on which the gate line 81 and the first and second common wirings 81c and 81d are formed.

The gate insulating layer 82 may use a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ).

Thereafter, a semiconductor layer (amorphous silicon + impurity amorphous silicon) is formed on the gate insulating layer 82.

Subsequently, the semiconductor layer is patterned by photo and etching processes to form first and second active layers 83a and 83b having island shapes on the first and second gate electrodes 81a and 81b. do.

Subsequently, as shown in FIG. 8C, a conductive metal is deposited on the entire surface of the lower substrate 80 on which the first and second active layers 83a and 83b are formed and patterned through photo and etching processes to form the gate line. A common data line 84 is formed so as to intersect with 81 to define the first to fourth sub pixel areas.                     

The first and second source electrodes 84a and 84b and the first and second sources protruding in one direction from the left and right sides of the common data line 84 while forming the common data line 84. The first and second drain electrodes 84c and 84d separated from the electrodes 84a and 84b by a predetermined interval are formed.

The first to second sub-pixel regions are formed to extend from the first and second drain electrodes 84c and 84d by etching the conductive metal while forming the first and second drain electrodes 84c and 84d. The first to fourth pixel electrodes 85a, 85b, 85c, and 85d are respectively formed so as to be disposed between the common electrodes 81e. In this case, the first and second pixel electrodes 85a and 85b of the first and second sub-pixel regions are integrally connected, and the third and fourth pixel electrodes 85c of the third and fourth sub-pixel regions. 85d) are integrally connected.

In addition, the first to fourth pixel electrodes 85a, 85b, 85c, and 85d are formed, and the first to fourth pixel electrodes 85a, 85b, 85c, and 85d extend from the first and second pixel electrodes 85a, 85b, 85c, and 85d. First to fourth storage electrodes 86a, 86b, 86c, and 86d are formed to overlap the upper portions of the wirings 81c and 81d, respectively.

Such storage capacitors form a storage on common structure.

Subsequently, although not shown in the drawing, an alignment layer made of polyimide or a photo-alignment material is formed on the entire surface of the lower substrate 80 including the first to fourth pixel electrodes 85a, 85b, 85c, and 85d.

Here, the alignment layer made of polyimide is determined by mechanical rubbing, and the photoreactive material made of polyvinylcinnamate based material or polysiloxane based material is oriented by irradiation with light such as ultraviolet rays. This is determined.

At this time, the orientation direction is determined by the irradiation direction of the light or the property of the irradiated light, that is, the polarization direction.

Third Embodiment

First, the configuration of a liquid crystal display device according to a third embodiment of the present invention will be described.

FIG. 10 is a plan view of a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view of the structure taken along line VV ′ of FIG. 10.

In the liquid crystal display according to the third exemplary embodiment of the present invention, when the upper and lower neighboring first and second pixel areas are described together, as shown in FIGS. 10 and 11, the lower substrate 100 is formed on the lower substrate 100. In order to define the first and second pixel regions P, the gate lines 101 and the data lines 104 are arranged to cross each other, and are spaced apart from the gate lines 101 so that the first, second, and first ends are separated in the same direction. Second common wirings 101c and 101d are formed, and the first and second pixel areas P adjacent to the upper and lower portions defined by the gate line 101 and the data line 104 intersect with each other are first. The second pixel electrodes 107a and 107b are formed, and first and second thin film transistors are formed at portions where the gate lines 101 and the data lines 104 cross each other.

The first and second thin film transistors include first and second gate electrodes 101a and 101b protruding upward and downward of the gate line 101, and first and second gate electrodes 101a and 101b. From the gate insulating film 102 formed on the entire lower substrate 100, the active layer 103 formed on the gate insulating film 102 above the first and second gate electrodes 101a and 101b, and the data line 103 The common source electrode 104a protruding and overlapping the center of the active layer 103, and the first and second drain electrodes spaced apart from the common source electrode 104a and overlapped on both sides of the active layer 103. It consists of 104b and 104c.

The first and second drain electrodes 104b and 104c are formed in a horizontal direction parallel to the gate line 101.

A thick insulating film 105 is formed on an entire surface of the lower substrate 100 including the first and second thin film transistors, and the first and second drain electrodes 104b and 104c respectively have a first and second thin film transistors. Second contact holes 106a and 106b are formed.

The first and second pixel electrodes 107a and 107b formed in the upper and lower neighboring first and second pixel regions are formed through the first and second contact holes 106a and 106b. It is in contact with the two drain electrodes 104b and 104c.

First and second storage electrodes 108a and 108c are formed to extend from the first and second pixel electrodes 107a and 107b and overlap the upper portions of the first and second common wires 101c and 101d.

In this case, the first and second pixel electrodes 107a and 107b may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide. It is composed of a transparent metal such as (Indium Tin Zinc Oxide: ITZO).

Although not shown in the drawing, the upper substrate facing the lower substrate includes a black matrix layer for blocking light of portions other than the first and second pixel regions P, R for expressing color colors, G, B color filter layers and a common electrode for realizing an image are formed.

Next, a manufacturing method of the liquid crystal display device according to the third embodiment of the present invention having the above configuration will be described.

12A to 12C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a third embodiment of the present invention.

In the method of manufacturing the liquid crystal display device according to the third embodiment of the present invention, as shown in FIG. 12A, the conductive metal is deposited on the transparent lower substrate 100, and the conductive metal is patterned using photo and etching processes. Thus, the gate lines 101 arranged in one direction and the first and second gate electrodes 101a and 101b are formed to protrude in the upper and lower directions of the gate line 101.

The gate line 101 is formed and first and second common lines 101c and 101d are formed in the same direction before and after the gate line 101 so as to be spaced apart from the gate line 101.

Thereafter, the gate insulating layer 102 is formed on the entire surface of the lower substrate 100 on which the gate line 101 is formed.                     

The gate insulating layer 102 may use a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ).

Thereafter, a semiconductor layer (amorphous silicon + impurity amorphous silicon) is formed on the gate insulating layer 102.

Subsequently, the semiconductor layer is patterned by photo and etching processes to form an active layer 103 having an island shape on the first and second gate electrodes 101a and 101b.

Thereafter, as shown in FIG. 12B, a conductive metal is deposited on the entire surface of the lower substrate 100 on which the active layer 103 is formed, and patterned through photo and etching processes so as to cross-align with the gate line 101. A data source 104 is formed, and a common source electrode 104a is formed to protrude from one side of the data line 104 so as to overlap the center of the active layer 103, and to be constant with the common source electrode 104a. The first and second drain electrodes 104b and 104c are formed to be spaced apart from each other and overlap the upper portions of both sides of the active layer 103.

The first and second drain electrodes 104b and 104c are formed in a horizontal direction parallel to the gate line 101.

When the data line 104, the common source electrode 104a, and the first and second drain electrodes 104b and 104c are formed, the impurity amorphous silicon layer is excessively etched to form the first and second drain electrodes 104b, An ohmic contact layer 103a is formed between the 104c and the active layer 103 and between the common source electrode 104a and the active layer 103.

By the above process, first and second thin film transistors using a common source electrode are disposed in regions where the data lines 104 and the gate lines 101 of the upper and lower neighboring first and second pixel regions intersect. Is formed.

Since the first and second drain electrodes 104b and 104c of the first and second thin film transistors are formed in the same horizontal direction as the gate line 101, the common source electrode 104a and the first and second drain electrodes are formed. Even when left and right misalignments between the first and second gate electrodes 101a and 101b occur, there is no difference in Cgs between the first and second pixel regions adjacent to the upper and lower portions.

Thereafter, an interlayer insulating layer 105 is deposited on the entire surface of the lower substrate 100 on which the data line 104 is formed. In this case, the interlayer insulating film 105 may be formed using at least one of an oxide film, a nitride film, photoacryl, polyimide, and BCB (Benzo Cyclo Butene).

Subsequently, the interlayer insulating layer 105 is etched to expose one region of the first and second drain electrodes 104b and 104c positioned in the upper and lower first and second pixel regions to expose the first and second contact holes 106a. , 106b).

Subsequently, as shown in FIG. 12C, after the transparent conductive film is deposited on the interlayer insulating film 105, the transparent conductive film is selectively removed through a photo and etching process to form the first and second contact holes 106a and 106b. First and second pixel electrodes 107a and 107b are formed in the first and second pixel regions so as to contact the first and second drain electrodes 104b and 104c.

In addition, the first and second storage electrodes 108a and 108b are formed by etching the transparent conductive layer so as to overlap the upper portions of the first and second common wirings 101b and 101c. In this case, the first and second storage electrodes 108a and 108b extend from the first and second pixel electrodes 107a and 107b.

The storage capacitor of the present invention formed by the above method has a storage on common structure.

The transparent conductive film may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). Can be formed.

Subsequently, although not shown in the drawings, an alignment layer made of polyimide or a photo-alignment material is formed on the entire surface of the lower substrate 100 including the first and second pixel electrodes 107a and 107b.

Here, the alignment layer made of polyimide is determined by mechanical rubbing, and the photoreactive material made of polyvinylcinnamate based material or polysiloxane based material is oriented by irradiation with light such as ultraviolet rays. This is determined.

At this time, the orientation direction is determined by the irradiation direction of the light or the property of the irradiated light, that is, the polarization direction.

Fourth embodiment

First, the configuration of a liquid crystal display device according to a fourth embodiment of the present invention will be described.                     

FIG. 13 is a plan view of a liquid crystal display according to a fourth exemplary embodiment of the present invention, and FIG. 14 is a cross-sectional view of the structure taken along line VI-VI ′ and VIII-VIII of FIG. 13.

13 and 14, the liquid crystal display according to the fourth embodiment of the present invention includes a gate line 131 arranged in one direction on a transparent lower substrate 130, and the gate line 131. Data lines 134 intersecting with each other to define first and second pixel areas adjacent to upper and lower parts, and first and second gate electrodes 131a protruding from the upper and lower parts of the gate line 131. 131b, first and second common wirings 131c and 131d arranged parallel to the front and rear ends of the gate line 131, and on one side of the first and second common wirings 131c and 131d. SiNx or a plurality of common electrodes 131e formed in the first and second pixel regions extending in a direction perpendicular to the gate line 131 and the lower substrate 130 including the gate line 131. A gate insulating layer 132 formed of a material such as SiOx, and the gate insulating layer 13 on the first and second gate electrodes 131a and 131b. 2, an active layer 133 formed in an island shape, a common source electrode 134a protruding from one side of the data line 134 and overlapping an upper portion of the center of the active layer 133, and the common source electrode. First and second drain electrodes 134b and 134c spaced apart from each other at a predetermined interval and overlapping the upper and lower sides of the active layer 133, respectively, and the first and second drain electrodes 134b and 134c. Extended from the first and second pixel electrodes 135a and 135b formed between the common electrodes 131e of the first and second pixel regions of the upper and lower portions, and the first and second pixel electrodes 135a, The first and second storage electrodes 136a and 136b extending from 135b and overlapping the upper and lower common first and second common wires 131c and 131d may be included.

Although not shown in the drawing, an alignment layer (not shown) made of polyimide is formed on the entire surface of the lower substrate 130.

Since the first and second storage electrodes 136a and 136b are formed on the gate insulating layer 132 on the first and second common wirings 131c and 131d, the storage capacitor of the present invention is a storage on comon (Storage). On Common) structure.

The first and second common lines 131c and 131d and the common electrode 131e are formed on the same layer as the gate line 131.

The data line 134 and the first and second pixel electrodes 135a and 135b may be formed of an opaque metal, and may be indium tin oxide (ITO), tin oxide (TO), or indium. It may be composed of a transparent metal such as zinc oxide (IZO) or indium tin zinc oxide (ITZO).

The common electrode 131e adjacent to the data line 134 of the common electrode 131e is formed to have a small distance from the data line 134. In this way, the light leakage phenomenon due to the distortion of the liquid crystal alignment state between the data line 134 and the common electrode 131e can be reduced to some extent.

Next, a manufacturing method of the liquid crystal display device according to the fourth embodiment of the present invention having the above configuration will be described.

15A to 15C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a fourth embodiment of the present invention.

In the method of manufacturing the liquid crystal display device according to the fourth embodiment of the present invention, as shown in FIG. 15A, the conductive metal is deposited on the transparent lower substrate 130, and the conductive metal is patterned using photo and etching processes. Thus, the gate lines 131 arranged in one direction are formed. In this case, the first and second gate electrodes 131a and 131b are defined to protrude upward and downward from the gate line 131.

In addition, first and second common lines 131c and 131d are formed before and after the same material on the same layer as the gate line 131 in a direction parallel to the gate line 131.

At the same time, a plurality of common electrodes are disposed in upper and lower neighboring first and second pixel regions extending from one side of the first and second common lines 131c and 131d to have a direction perpendicular to the gate line 131. 131e are formed.

Thereafter, as shown in FIG. 15B, a gate insulating layer 132 is formed on the entire surface of the lower substrate 130 on which the gate line 131 and the first and second common wirings 131c and 131d are formed.

The gate insulating layer 132 may use a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ).

Thereafter, a semiconductor layer (amorphous silicon + impurity amorphous silicon) is formed on the gate insulating layer 132.                     

Subsequently, the semiconductor layer is patterned by photo and etching processes to form an active layer 133 having an island shape on the first and second gate electrodes 131a and 131b.

Subsequently, as shown in FIG. 15C, a conductive metal is deposited on the entire surface of the lower substrate 130 on which the active layer 133 is formed, and patterned through photo and etching processes to cross the gate line 131. Data lines 134 are formed to define first and second pixel areas adjacent to upper and lower parts thereof.

In addition, the data lines 134 are formed, and the first and second drains separated from the common source electrode 134a and the common source electrode 134a by a predetermined interval so as to protrude in one direction of the data line 134. Electrodes 134b and 134c are formed.

In this case, the common source electrode 134a is formed to overlap the center upper portion of the active layer 133, and the first and second drain electrodes 134b and 134c are formed to overlap the upper sides of the active layer 133, respectively.

The first and second drain electrodes 134b and 134c are formed in a horizontal direction parallel to the gate line 131.

When the data line 134, the common source electrode 134a, and the first and second drain electrodes 134b and 134c are formed, the impurity amorphous silicon layer is excessively etched to form the first and second drain electrodes 134b, An ohmic contact layer 133a is formed between the 134c and the active layer 133 and between the common source electrode 134a and the active layer 133.

By the above process, first and second thin film transistors using a common source electrode are formed in a region where the data line 134 and the gate line 131 intersect.

Since the first and second drain electrodes 134b and 134c of the first and second thin film transistors are formed in the same horizontal direction as the gate line 131, the common source electrode 134a and the first and second drain electrodes are formed. Even if left and right misalignment between the 134b and 134c and the first and second gate electrodes 131a occurs, there is no difference in Cgs between the first and second pixel areas adjacent to the upper and lower parts.

Thereafter, the first and second drain electrodes 134b and 134c are formed, and at the same time, the conductive metal is etched to extend from the first and second drain electrodes 134b and 134c. First and second pixel electrodes 135a and 135b are formed between the common electrodes 131e.

In addition, the first and second pixel electrodes 135a and 135b are formed, and at the same time, the first and second pixel electrodes 135a and 135b extend from the first and second common wires 131c and 131d. The first and second storage electrodes 136a and 136b are formed to overlap each other.

Such storage capacitors form a storage on common structure.

Subsequently, although not shown in the drawing, an alignment layer made of polyimide or a photo-alignment material is formed on the entire surface of the lower substrate 130 including the first and second pixel electrodes 135a and 135b.

Here, the alignment layer made of polyimide is determined by mechanical rubbing, and the photoreactive material made of polyvinylcinnamate based material or polysiloxane based material is oriented by irradiation with light such as ultraviolet rays. The direction is determined.

At this time, the orientation direction is determined by the irradiation direction of the light or the property of the irradiated light, that is, the polarization direction.

The configuration and method of the present invention described above can be applied not only to TN and IPS but also to vertical field liquid crystal display (VA).

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the above embodiments, but should be defined by the claims.

The liquid crystal display of the present invention as described above and a manufacturing method thereof have the following effects.

First, by designing the entire pixel to be symmetric up, down, left, and right, it is possible to reduce the misalignment caused by the asymmetric design of the pixel. In addition, it is possible to control the abnormal operation phenomenon of the liquid crystal by the asymmetric electric field.

Second, since the common source electrode and the first and second drain electrodes are arranged in the horizontal direction, even if misalignment occurs in the source / drain electrodes and the gate electrode in the left and right (X, Y) directions, Cgs does not change.

Third, since one unit pixel region is configured to operate by two or four thin film transistors, it is possible to prevent a problem that the entire pixel does not operate when a defect occurs. Therefore, even if a point defect occurs, the possibility of recognizing is low, so that the yield can be reduced.

Fourth, since the size of the neighboring pixel region can be formed differently, the degree of freedom of pixel design can be increased when designing a pentile or the like.

Claims (48)

A gate line arranged in one direction on the substrate and having first and second gate electrodes defined in one region; A common data line intersecting with the gate line and arranged to divide and define one unit pixel area into four first to fourth sub-pixel areas; First and second active layers formed on the first and second gate electrodes and separated from each other; A plurality of thin film transistors disposed on the gate line and the common data line so as to be symmetrical with the common source electrode and the first and second drain electrodes; An interlayer insulating film formed on the entire surface of the substrate to have first to fourth contact holes in upper and lower regions of the first and second drain electrodes, respectively; A first first contacting the first drain electrode through the first and second contact holes and contacting the second drain electrode through the third and fourth contact holes respectively formed in the first to fourth sub-pixel regions And a fourth pixel electrode. The method of claim 1, And first to fourth storage electrodes which are divided at each end of the first to fourth sub-pixel regions so as to overlap the upper part of the gate line before and after the gate line. The method of claim 2, And the first to fourth storage electrodes extend from the first to fourth pixel electrodes. The method of claim 1, And the common source electrode is defined in one region of the common data line intersecting the gate line, and overlaps an upper portion of one side of the first and second active layers. The method of claim 4, wherein And the first and second drain electrodes spaced apart from the common source electrode at predetermined intervals and overlap the upper portions of the other sides of the first and second active layers. The method of claim 1, And an ohmic contact layer is further formed between the first and second drain electrodes and the first and second active layers. The method of claim 1, And the first and second drain electrodes are formed in the common data line direction. The method of claim 1, Wherein the first drain electrode is used as a drain electrode in the first and second sub-pixel regions, and the second drain electrode is used as a drain electrode in the third and fourth sub-pixel regions. . The method of claim 1, And the common data line and the common source electrode are commonly used in the first to fourth sub-pixel regions. The method of claim 1, And the first to fourth sub-pixel areas are equally divided to have the same area by the common data line. The method of claim 1, And the first to fourth sub-pixel areas are equally divided to have different areas by the common data line. The method of claim 11, The common data line may be arranged such that an area of the third and fourth subpixel areas of the upper and lower left portions is equally narrower or wider than an area of the first and second subpixel areas of the upper and lower right portions. Liquid crystal display device characterized in that. The method of claim 1, And one unit pixel area including the four first to fourth sub-pixel areas includes different areas. The method of claim 13, And one pixel unit each implements one R, G, or B pixel. A gate line arranged in one direction on the substrate and having first and second gate electrodes defined in one region; A common data line perpendicular to the gate line, the common data line arranged to divide and define one unit pixel area into first to fourth sub pixel areas on left and right sides; First and second common lines arranged at upper and lower ends of the gate line and spaced apart from the gate line; A plurality of common electrodes formed in the first to fourth sub pixel regions in a direction perpendicular to the gate line; First and second active layers formed on the first and second gate electrodes and separated from each other; First and second source electrodes protruding to the left and right sides of the common data line and overlapping one side of the first and second active layers; First and second drain electrodes spaced apart from the first and second source electrodes at predetermined intervals and overlapped on upper portions of the first and second active layers, respectively; And first to fourth pixel electrodes formed between the common electrodes of the first to fourth sub-pixel regions so as to be connected to the first and second drain electrodes. The method of claim 15, The liquid crystal display device further comprises first to fourth storage electrodes overlapping the upper and lower ends of the first to second common wires so as to be symmetrically arranged up, down, left, and right. The method of claim 16, And the first to fourth storage electrodes extend from the first to fourth pixel electrodes, and the first to fourth pixel electrodes extend from the first and second drain electrodes. The method of claim 15, And the first and second common lines and the common electrode are formed on the same layer as the gate line, and the plurality of common electrodes extend from one side of the first and second common lines. The method of claim 15, The common data line and the first to fourth pixel electrodes may be formed of an opaque metal, and may be indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IN). IZO) or Indium Tin Zinc Oxide (ITZO). The method of claim 15, The first gate electrode, the first source electrode, and the first drain electrode constitute a first thin film transistor, and the second gate electrode, the second source electrode, and the second drain electrode constitute a second thin film transistor. Liquid crystal display device characterized in that. The method of claim 20, And a first thin film transistor is shared in the first and second sub-pixel regions, and the second thin film transistor is shared in the third and fourth sub-pixel regions. The method of claim 15, And the first to fourth sub-pixel areas are equally divided to have the same area by the common data line. The method of claim 15, And the first to fourth sub-pixel areas are equally divided to have different areas by the common data line. The method of claim 15, And one unit pixel area including the first to fourth sub-pixel areas includes different areas. The method of claim 24, And one pixel unit each implements one R, G, or B pixel. A plurality of gate lines and data lines arranged on the substrate to define first and second pixel regions adjacent to the upper and lower parts; First and second common wires arranged spaced apart before and after the gate line; First and second thin film transistors formed in a cross shape at portions where the gate lines and the data lines cross each other; First and second pixel electrodes formed on the first and second pixel areas; And first and second storage electrodes extending from the first and second pixel electrodes and formed on the first and second common wirings. The method of claim 26, The first and second thin film transistors, First and second gate electrodes protruding above and below the gate line; A gate insulating film formed on an entire surface of the substrate including the first and second gate electrodes; An active layer formed on the gate insulating film on the first and second gate electrodes; A common source electrode protruding from the data line and overlapping the center of the active layer; And first and second drain electrodes spaced apart from the common source electrode and overlapped on both sides of the active layer. 28. The method of claim 27, And the first and second drain electrodes are formed in the same direction (horizontal direction) with the gate line. 28. The method of claim 27, And an interlayer insulating layer in which first and second contact holes are formed in one region of the first and second drain electrodes, respectively, on an entire surface of the substrate including the first and second thin film transistors. 30. The method of claim 29, And the first and second pixel electrodes are in contact with the first and second drain electrodes through the first and second contact holes. The method of claim 26, The first and second pixel electrodes may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (Indium tin zinc oxide). Liquid crystal display, characterized in that composed of a transparent metal such as ITZO). A plurality of gate lines and data lines arranged on the substrate to define first and second pixel regions adjacent to the upper and lower parts; First and second common wires arranged spaced apart before and after the gate line; A plurality of common electrodes formed in the first and second pixel regions in a direction perpendicular to the gate line; First and second thin film transistors formed in a cross shape at portions where the gate lines and the data lines cross each other; First and second pixel electrodes arranged between the common electrodes of the first and second pixel regions; And first and second storage electrodes overlapped on the first to second common lines. 33. The method of claim 32, The first and second thin film transistors, First and second gate electrodes protruding above and below the gate line; A gate insulating film formed on an entire surface of the substrate including the gate line; An active layer formed in an island shape on the gate insulating layer on the first and second gate electrodes; A common source electrode protruding from one side of the data line and overlapping an upper portion of a center of the active layer; And first and second drain electrodes spaced apart from the common source electrode at predetermined intervals and overlapped on upper and lower sides of the active layer, respectively. The method of claim 33, wherein And the first and second drain electrodes are formed in the same direction (horizontal direction) with the gate line. The method of claim 33, wherein And the first and second storage electrodes extend from the first and second pixel electrodes, and the first and second pixel electrodes extend from the first and second drain electrodes. 33. The method of claim 32, And the first and second common wirings and the common electrode are formed on the same layer as the gate line. Forming a gate line arranged in one direction on the substrate and defining first and second gate electrodes in one region; Forming first and second active layers on the first and second gate electrodes so as to be isolated from each other; Forming a common data line intersecting with the gate line and defining a unit pixel area divided into four first to fourth sub-pixel areas; Forming a plurality of thin film transistors including a common source electrode and first and second drain electrodes in first to fourth sub-pixel regions intersecting the gate line and the common data line; Forming an interlayer insulating film on an entire surface of the substrate to have first to fourth contact holes in upper and lower regions of the first and second drain electrodes, respectively; First to fourth sub-pixel regions respectively contacted to the first drain electrode through the first and second contact holes, and contacted to the second drain electrode through the third and fourth contact holes. Forming a fourth pixel electrode; And forming first to fourth storage electrodes to overlap the gate lines before and after the gate line. 39. The method of claim 37, The first to fourth storage electrodes are formed simultaneously with the first to fourth pixel electrodes. 39. The method of claim 37, And the first and second drain electrodes are formed in the same direction (up and down direction) with the common data line so as to cover the first to fourth sub pixel areas. Forming a gate line arranged in one direction on the substrate and defining first and second gate electrodes in one region; Forming first and second common wires on upper and lower ends of the gate line and spaced apart from the gate line; Forming a plurality of common electrodes in first to fourth sub pixel regions in a direction perpendicular to the gate line; Forming first and second active layers on the first and second gate electrodes so as to be isolated from each other; Forming a common data line vertically intersecting with the gate line to define a unit pixel area divided into first to fourth sub pixel areas in left and right sides; Forming first and second source electrodes protruding from left and right sides of the common data line so as to overlap one side of the first and second active layers; Forming first and second drain electrodes spaced apart from the first and second source electrodes at predetermined intervals and overlap the upper portions of the first and second active layers, respectively; Forming first to fourth pixel electrodes in first to fourth sub-pixel regions so as to be disposed between the common electrodes; And forming first to fourth storage electrodes on the gate line so as to overlap the first to second common lines above and below the gate line. 41. The method of claim 40, And the gate line, the first and second common wirings, and the common electrodes are formed on the same layer. 41. The method of claim 40, The first and second drain electrodes, the first to fourth pixel electrodes and the first to fourth storage electrodes are formed on the same layer. Forming a plurality of gate lines defining first and second gate electrodes protruding upward and downward on a substrate; Forming first and second common lines to be spaced apart before and after the gate line; Forming a gate insulating film on an entire surface of the substrate including the first and second gate electrodes; Forming an active layer on the gate insulating film above the first and second gate electrodes; Forming a plurality of data lines arranged to intersect the gate line to define first and second pixel areas adjacent to upper and lower parts thereof; Forming a common source electrode protruding from the data line and overlapping the center upper portion of the active layer; Forming first and second drain electrodes spaced apart from the common source electrode and arranged in a horizontal direction on both sides of the active layer; Forming first and second pixel electrodes in the first and second pixel regions so as to be connected to the first and second drain electrodes, respectively; And first and second storage electrodes extending from the first and second pixel electrodes to overlap the first and second common lines. 44. The method of claim 43, And the gate line and the first and second common wires are formed on the same layer. 44. The method of claim 43, And the first and second pixel electrodes and the first and second storage electrodes are formed on the same layer. Forming a plurality of gate lines defining first and second gate electrodes protruding upward and downward on a substrate; Forming first and second common lines to be spaced apart before and after the gate line; Forming a plurality of common electrodes in first and second pixel regions in a direction perpendicular to the gate line; Forming a gate insulating film on an entire surface of the substrate including the gate line; Forming an active layer on the gate insulating layer on the first and second gate electrodes; Forming a plurality of data lines arranged to intersect the gate line to define the first and second pixel areas adjacent to upper and lower parts; Forming a common source electrode to protrude from one side of the data line and to overlap the center upper portion of the active layer; Forming first and second drain electrodes horizontally spaced apart from the common source electrode at upper and lower sides of the active layer in a horizontal direction; Forming first and second pixel electrodes in the first and second pixel areas so as to be arranged between the common electrodes; And forming first and second storage electrodes on the first and second common lines so as to overlap each other. The method of claim 46, And the gate line, the first and second common wirings, and the common electrodes are formed on the same layer. The method of claim 46, And the first and second drain electrodes, the first and second pixel electrodes, and the first and second storage electrodes are formed on the same layer.

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