KR100963525B1 - Active matrix display device and driving method - Google Patents

Abstract

In the method of driving the active-matrix display device and the active-matrix display device, the fifth transistor is connected to the power supply line such that the fixed voltage required for the compensation of the power supply voltage, that is, the threshold voltage, is supplied by the power supply line through the fifth transistor instead of the signal line. It is connected between the drain terminal of a 1st transistor. Thus, a sufficient length of time for the threshold voltage compensation period can be maintained, and the second transistor of each pixel can be accurately compensated for the threshold voltage irregularity.

Description

Active-matrix display device and method of driving the same

1 is a schematic block diagram of an active-matrix display device according to an embodiment of the present invention.

2 is a circuit diagram of a pixel circuit of the first circuit.

3 is a timing diagram illustrating the operation of the pixel circuit of the first circuit.

4 is a circuit diagram of a pixel circuit of a second circuit.

5 is a circuit diagram of a pixel circuit of a third circuit.

6 is a circuit diagram of a pixel circuit of a fourth circuit.

7 is a circuit diagram of a pixel circuit of a fifth circuit.

8 is a circuit diagram of a pixel circuit of a sixth circuit.

9 is a circuit diagram of a pixel circuit of a seventh circuit.

Fig. 10 shows the relationship between the input data (gray shade) and the voltage of the signal line.

11 is a schematic block diagram of a simple active-matrix organic-EL display.

12 is a circuit diagram of a pixel circuit having two transistors.

13 is a circuit diagram of a conventional pixel circuit.

14 is a timing diagram illustrating the operation of the conventional pixel circuit.                 

* Explanation of symbols on the main parts of the drawings

11, 11a, 11b, 11c, 11d, 11e, 11f, 11g. Pixel circuit

12. Data Driver 13. Signal Line

14. Scan driver 15a, 15b, 15c, 15d. scanning line

21. 1st transistor 22. 2nd transistor

23. 3rd transistor 24. 4th transistor

25. 5th transistor 26. 1st capacitor

27. Second Capacitor 31. First Power Line

32. Second Power Line 33. Third Power Line

The present invention relates to an active-matrix display device including pixels (pixel circuits) having display device elements arranged in a matrix and to read and display image data by scanning lines and signal lines, and a method of driving such an active-matrix display device. . In particular, the present invention relates to an active-matrix display device having an organic electroluminescent (hereinafter referred to as EL) element as a display element and a method of driving an active-matrix organic-EL display device.

In an active-matrix display device, an electro-optical element, such as a liquid crystal cell or an organic-EL element, is used for the display element of each pixel. The organic-EL device is a structure in which an organic layer is disposed between electrodes. By supplying a voltage to the organic-EL, electrons are injected from the cathode into the organic layer and holes are injected from the anode into the organic layer. The electrons and holes then recombine to emit light. The organic-EL device has the following characteristics.

1. The organic-EL device is a drive for obtaining luminance of 100 to 10,000 cd / m ² , and requires a low power consumption of 10 V or less.

2. The organic-EL device has high image-contrast due to self-luminous, good visibility due to high response speed, and is also suitable for moving picture display.

3. The organic-EL device is an all-solid-state element with a simple structure, thus achieving high reliability and low-profile device.

For display devices of pixels, organic-EL displays (hereinafter referred to as organic-EL displays) having organic-EL elements having such characteristics are expected to be used as next-generation flat panel displays.

As the organic-EL display driving method, a simple matrix method and an active-matrix method are known. In both methods, the active-matrix method has the following characteristics.

1. The active-matrix method is suitable for high resolution and high brightness organic-EL displays because it can maintain the emission of light from the organic-EL elements of each pixel within one frame.

2. The active-matrix method can have a peripheral circuit with thin film transistors formed in the panel to simplify the external interface of the panel and also to achieve a high performance panel.

In an active-matrix organic-EL display, a polysilicon thin film transistor (hereinafter referred to as TFT) having polysilicon as the active layer is usually used as a transistor, that is, an active element. The reason for using a polysilicon TFT normally is because of its excellent driving ability and ability to reduce pixel size to achieve high resolution. On the other hand, however, polysilicon TFTs are also known to have very irregular characteristics.

Thus, with respect to active-matrix organic-EL displays using polysilicon TFTs, the irregularities in the TFT characteristics need to be reduced and the irregularities of the TFTs in the circuit need to be compensated for. This is due to the following reason. In a liquid crystal display having a liquid crystal cell as the display element of the pixel, the luminance data of the pixel is controlled by voltage, while in the organic-EL display, the luminance data of the pixel is controlled by current.

A general outline of an active-matrix organic-EL display will be described. In FIG. 11 a schematic of an active-matrix organic-EL display is shown. In Fig. 12, one figure of the pixel circuit of the active-matrix organic-EL display is shown (see, for example, Japanese Unexamined Patent Application Publication No. 8-234683). In an active-matrix organic-EL display, m columns x n rows of pixels 101 are arranged in a matrix. In the pixels 101 arranged in a matrix, each m column of the signal lines 103-1 to 103-m driven by the data driver 102 is connected to the pixels 101 corresponding to the pixel columns, and the scan driver 104 Each of the n rows of the scanning lines 105-1 to 105-n driven by N is connected to the pixel 101 in correspondence with the pixel rows.

As can be seen from FIG. 12, each pixel (pixel circuit) 101 includes an organic-EL element 110, a first transistor 111, a second transistor 112, and a capacitor 113. The N-channel transistor is used as the first transistor 111 and the P-channel transistor is used as the second transistor 112.

The source terminal of the first transistor 111 is connected to a corresponding one of the signal lines 103 (103-1 to 103-m) and the gate terminal corresponds to one of the scanning lines 105 (105-1 to 105-n). It is connected with one line. The first end of the capacitor 113 is connected to, for example, the first power supply line 121 of the power supply voltage VCC1 which can be a positive supply voltage. The second end of the capacitor 113 is connected to the drain terminal of the first transistor 111. The source terminal of the second transistor 112 is connected to the first power line 121, and the gate terminal of the second transistor 112 is connected to the drain terminal of the first transistor 111. The anode of the organic-EL element 110 is connected to the drain terminal of the second transistor 112, and the cathode of the organic-EL element 110 is, for example, a power supply voltage VCC2 which can be a ground potential. Is connected to the second power supply line 122.

In the pixel circuit described above, a row containing one of the pixels for writing the luminance data is selected by the scan driver 104 via the scanning line 105. This turns on the first transistor 111 of the pixel in the row. Luminance data is supplied via the voltage from the data driver 102 via the signal line 103. The luminance data is then sent through the first transistor 111 and written into the capacitor 113 holding the data voltage. The luminance data written into the capacitor 113 is held for one field period. The sustain data voltage is applied to the gate terminal of the second transistor 112.

The second transistor 112 drives the organic-EL device with an electric current according to the maintenance data. Grayscale is achieved in the organic-EL device by modulating the voltage Vdata (<0) held by the capacitor 113 between the gate and the source of the second transistor 112.

The luminance L _oled of the organic-EL device is usually proportional to the electrical current I _oled in the device. As a result, the following equation maintains between the luminance L _oled and the electrical current I _oled of the organic-EL device.

L _oled ∝ I _oled = k (Vdata-Vth) ² ... (1)

In Equation (1), k = 1/2 占 占 占 OX / W / L, where mu represents carrier mobility of the second transistor, Cox represents gate capacity per unit area of the second transistor, W denotes the gate width of the second transistor 112 and L denotes the gate length of the second transistor 112. Therefore, irregularities in the mobility μ of the second transistor 112 and the threshold voltage Vth (<0) directly affect the luminance irregularity of the organic EL device.

In order to compensate for the threshold voltage Vth which tends to easily cause luminance irregularity, the threshold voltage compensation pixel circuit is, for example, USP No. 6,229,506.

13 is a circuit diagram of a conventional threshold voltage compensation pixel circuit. In Fig. 13, the same parts as in Fig. 12 are designated by the same reference numerals. As can be seen from FIG. 13, this conventional pixel circuit includes one organic-EL element 110, four transistors 111, 112, 114 and 115 and two capacitors 113 and 116. In the organic-EL display having this pixel circuit, the three scanning lines 105a, 105b, 105c driven by the scan driver 104 are connected with each other in rows corresponding to the columns of the pixels (see Fig. 11).

The source terminal of the first transistor 111 is connected to the signal line 103, and the gate terminal of the first transistor 111 is connected to the first scanning line 105A. The first end of the first capacitor 116 is connected to the drain terminal of the first transistor 111. The gate terminal of the second transistor 112 is connected to the second end of the first capacitor 116, and the source terminal of the second transistor 112 is, for example, a power supply that can be a positive supply voltage. It is connected to the first power supply line 121 of the voltage VCC1. The first end of the second capacitor 113 is connected to the first power line 121, and the second end of the second capacitor 113 is connected to the gate terminal of the second transistor 112.

The gate terminal of the third transistor 114 is connected to the second scanning line 105B, the source terminal of the third transistor 114 is connected to the gate terminal of the second transistor 114, and the third transistor 114 The drain terminal of is connected to the drain terminal of the second transistor 112. The gate terminal of the fourth transistor 115 is connected to the third scanning line 105C, and the source terminal of the fourth transistor 115 is connected to the drain terminal of the second transistor 112. The anode of the organic-EL element 110 is connected to the drain terminal of the fourth transistor 115, and the cathode is connected to the second power supply line 122 of the power supply voltage VCC2, which may be, for example, a ground potential. Connected.

The operation of the conventional threshold voltage compensation pixel circuit is described below with reference to the timing diagram of FIG. This timing diagram illustrates the timing relationship between the i th row and the (i + 1) th row in the pixel circuit during driving. Further, the term "compensation" denotes a threshold voltage compensation period, the term "write" denotes a data writing period, and the term "maintenance" denotes a data retention period.

In the operation of the pixel circuit, the threshold voltage compensation period comes before the data writing period. In the threshold voltage compensation period, the scanning pulse SCAN1 is supplied through the first scanning line 105A at a high level (hereinafter referred to as “H” level) to turn on the first transistor 111. The fixed voltage V ₀ is then supplied from the data driver 102 to the signal line 103. Therefore, the fixed voltage V ₀ is written into the first capacitor 116 through the first transistor 111. The scanning pulse SCAN2 supplied through the second scanning line 105b also reaches the "H" level at this time to turn on the third transistor 114. Further, the fourth transistor 115 is off because the scanning pulse SCAN3 supplied through the third scanning line 105C is at a low level (hereinafter referred to as "L" level).

In this state, the first capacitor 116 having a fixed (V ₀ ) adjacent to the first end of the capacitor 116 is charged from the second end through the source and drain terminals of the third transistor 114. If the threshold voltage compensation period is long enough, the voltage adjacent to the second end of the first capacitor 116, that is, the voltage between the gate terminal and the source terminal of the second transistor 112 is the threshold voltage Vth (<0) of the transistor. Converge to).

In the following data writing period, a scanning pulse (SCAN1) is "H" because it remains level, the first transistor 111 in the on mode is maintained in the (ON mode), the data voltage (V ₀ + Vdata (Vdata < 0)) is supplied from the signal line 102. Since the scanning pulse SCAN2 is at the "L" level at this time, the third transistor 114 is off.

For example, by ignoring the gate capacitance or parasitic capacitance of the transistor, the voltage between the gate terminal and the source terminal of the second transistor 112 can be expressed as follows.

Vgs = Vth + C1 / (C1 + C2) Vdata ... (2)

Here, C1 and C2 represent the capacities of the first and second capacitors 116 and 113, respectively.

By applying equation (2), the electric current I _oled flowing through the organic-EL element 110 can be expressed by the following equation.

L _oled ∝ I _oled = k {C1 / (C1 + C2) Vdata} ² ... (3)

As can be seen from equation (3), the electric current I _oled flowing through the organic-EL element 110 is not affected by the threshold voltage Vth of the second transistor 112. In other words, by using the conventional threshold voltage compensation pixel circuit, the threshold voltage Vth of the transistor 112 of each pixel is compensated. This means that the irregularity in the threshold voltage Vth of the second transistor 112 does not cause the luminance irregularity of the organic-EL element 110.

In the conventional threshold voltage compensation pixel circuit described above, during the threshold voltage compensation period, the second transistor 112 is gradually turned off as the voltage between the source terminal and the gate terminal approaches the threshold voltage Vth. )do. This also requires too much time for the voltage between the source and gate terminals of transistor 112 to deactivate the operation and converge to the threshold voltage Vth. For this reason, the threshold voltage compensation period requires a lot of time.

The differential expression of the gate voltage of the second transistor 112 in the threshold voltage compensation period is as follows.

k. {Vgs (t) -Vth} ² = -Cs.dVgs / dt ... (4)

In equation (4), the sufficient length of the threshold voltage compensation period is considered to be a time requiring half the amount of electric current during the minimum luminance.

If the electric current value is expressed by I _max during the maximum luminance of the organic-EL element 110, the initial value of the voltage Vgs between the gate terminal and the source terminal of the second transistor 112 is represented by V _init , and the second The holding capacitor of the gate voltage of the transistor 112 is mainly denoted by the capacitance C1, Cs of the second capacitor 113, the grayscale value is denoted by n, and provides the electric current I _max during the maximum luminance. The voltage (Vgs) between the gate terminal and the source terminal is expressed as Vgs = ΔV + Vth, and the following equation describes the time required for half the amount of electric current during the minimum luminance represented by I _max / 2 (n-1). do.

t = Cs.ΔV / Imax {√ (2n-2) -ΔV / V _init } ... (5)

For example, if Cs = 1 [pF], n = 64, ΔV = 4, I _max = 1 [μA] and the second term is sufficiently small, t = 45 [μs]. On the other hand, if the resolution (graphics display standard) is VGA, the number of scanning lines is 480, the frame frequency is 60 Hz, and one horizontal period is about 30 s. This means that it is difficult to complete the threshold voltage compensation period within one horizontal period.

Therefore, in the VGA-class display device, a sufficient length of the threshold voltage compensation period requires several microseconds to several tens of microseconds. For this reason, it is difficult to perform threshold voltage compensation and continuous data writing in one horizontal period. In other words, the conventional threshold voltage compensation pixel circuit cannot be applied to the VGA-lubricator-EL display. Moreover, as the display is defined higher, one horizontal period which is inversely proportional to the scanning frequency becomes shorter. Therefore, the sufficient length of the threshold voltage compensation period is difficult to maintain further.

In the conventional threshold voltage compensation pixel circuit, the signal line voltage corresponding to the threshold voltage compensation period and the data writing period, that is, the fixed voltage V ₀ during the threshold voltage compensation period and the data voltage Vdata + fixed voltage V during the data writing period. ₀ ) must be supplied from the signal line 103. For this reason, the structure of the data driver 102 (see Fig. 11) which is a signal line driver circuit tends to be complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-definition active-matrix display device using a threshold voltage compensation pixel circuit to improve the uniformity of the display image and to ensure a sufficient length of the threshold voltage compensation period despite the length of one horizontal period. It is.

The active-matrix display device of the present invention comprises a pixel circuit arranged in a matrix, each signal line interconnected in correspondence with a column of pixel circuits arranged in a matrix, and an interconnection corresponding to a row of pixel circuits arranged in a matrix. And a first scanning line, a second scanning line, a third scanning line, and a fourth scanning line. Each of the pixel circuits includes a first transistor having a gate terminal connected to a first scanning line and a first electrode terminal connected to one of the signal lines, a first capacitor having a first end connected to a second electrode terminal of the first transistor; A second capacitor having a first end connected to the first end or a second end of the first capacitor, a gate terminal connected to the second end of the first capacitor, and a first electrode terminal connected to the first power line A second transistor having a second transistor and a gate terminal connected to a second scanning line, wherein a first electrode terminal of the third transistor is connected to a gate terminal of a second transistor, and a second electrode terminal of the third transistor A third transistor connected to a second electrode terminal of a second transistor, a fourth transistor connected to a third scanning line of the gate terminal, and a first transistor connected to a second electrode terminal of the second transistor; A fifth transistor connected to a fourth scanning line of its own, wherein a first electrode terminal of the fifth transistor is connected to a third power supply line, and a second electrode terminal of the fifth transistor is connected to a second electrode terminal of the first transistor. And a display element connected to both the fifth transistor to be connected, the second electrode terminal of the fourth transistor, and the second power supply line.

In the active-matrix display device, since the first transistor and the fourth transistor are turned off and the third transistor and the fifth transistor are turned on, the threshold voltage of the second transistor in each pixel is compensated. The first transistor is then turned on and the third and fifth transistors are turned off to drive the device for writing display data from the signal line to the pixel. During the period of compensating the threshold voltage of the second transistor, the fifth transistor supplies the power supply voltage of the third power supply line to the first capacitor as a fixed voltage.

Thus, by supplying a fixed voltage required for threshold voltage compensation from the power supply line and not from the signal line, compensation of the threshold voltage is performed while simultaneously writing display data from the signal line in another pixel. In either row of pixels, one horizontal period may be set as the data write period and any length of the period may be set as the threshold voltage compensation period before the data write period. Thus, sufficient time for the threshold voltage compensation period can be maintained. This accurately compensates for the irregularities of the threshold voltages of the transistors in each pixel in order to improve the uniformity of brightness and to achieve high clarity of the display.

The present invention requires the continuous supply of only the data voltage, which simplifies the structure of the signal line driver circuit. Furthermore, since the power supply voltage of the signal line driver circuit can be reduced to the extent that the fixed voltage is eliminated, low power consumption can be achieved for the entire display.

Embodiments of the present invention will be described with reference to the drawings. 1 is a schematic block diagram of an active-matrix display device according to an embodiment of the present invention. In this embodiment, the organic-EL element is used as the display element of each pixel, and the polysilicon thin film transistor (TFT) is used as the active element. The present invention will be described using an active-matrix organic-EL display having an organic-EL element formed on a TFT substrate as an example.

Referring to Fig. 1, m columns x n rows of pixels (pixel circuits) 11 are arranged in a matrix. Each pixel 11 has an organic EL element as a display element. In the matrix arrangement of pixels 11, each column of pixels is interconnected with a corresponding column of signal lines (data lines) 13-1 to 13-m. The signal line is driven by the data driver 12 which is a signal line driver circuit. Each n row includes, for example, four lines driven by the scan driver 14, that is, multiple scanning lines, which can be scanning line driving circuits. Each group of multiple scanning lines 15A-1 to 15D-1, 15A-2 to 15D-2, ... 15A-n to 15D-n are interconnected with corresponding columns of pixels.

A distinguishing feature of the active-matrix organic-EL display device of the present invention lies in the structure and operation of the pixel (recovery circuit) 11. An example of the specific circuit of the pixel 11 will now be described.

[First circuit]

2 is a circuit diagram of the pixel circuit 11A according to the first circuit. As can be seen from FIG. 2, the pixel circuit 11A includes an organic-EL element 20, five transistors 21 to 25, and two capacitors 26 and 27. The organic EL device 20 is formed of an organic layer including a light emitting layer disposed between the first and second electrodes.

The first to fifth transistors 21 to 25 are polysilicon thin film transistors (TFTs) having polysilicon as an active layer. In the first circuit, a P-channel transistor is used as the second transistor 22. For the other transistors 21, 23, 24, 25, N-channel transistors are used.

The source terminal of the first transistor 21 is connected to the signal line 13, and the gate terminal of the transistor 21 is connected to the first scanning line 15A. The input terminal of the first capacitor 26 is connected to the drain terminal of the first transistor 11. The gate terminal of the second transistor 22 is connected to the output terminal of the first capacitor 26, and the source terminal of the transistor 22 is, for example, of the power supply voltage VCC1, which can be a positive supply voltage. It is connected to the first power supply line 31.

The first end of the second capacitor 27 is connected to the first power supply line, and the second end is connected to the gate terminal of the second transistor 22. The gate terminal of the third transistor 23 is connected to the second scanning line 15B, the source terminal is connected to the gate terminal of the second transistor 22, and the drain terminal is connected to the drain terminal of the second transistor 22. Connected. The gate terminal of the fourth transistor 24 is connected to the third scanning line 15C, and the source terminal is connected to the drain terminal of the second transistor 22.

The gate terminal of the fifth transistor 25 is connected to the fourth scanning line 15D, and the source terminal is connected to a third power supply line of the power supply voltage VCC3, which can be, for example, a positive supply voltage. The drain terminal is connected to the drain terminal of the first transistor 21 which is an input terminal of the first capacitor 26. The power supply voltage VCC3 has a different voltage value from the power supply voltage VCC1. The anode of the organic-EL element 20 is connected to the drain terminal of the fourth transistor 24 and the cathode is connected to the second power line 32 of the power supply voltage VCC2, which can be a ground potential, for example. do.

The pixel circuit 11A of the first circuit differs in that the data writing period and the threshold voltage compensation period exist simultaneously between the pixels connected along the same signal line. The operation of the data writing period and the threshold voltage compensation period will be described with reference to the timing diagram of FIG. 3 using the i-th row of pixels as an example. In Fig. 3, the term "compensation" indicates a threshold voltage compensation period, the term "write" indicates a data writing period, and the term "hold" indicates a data holding period.

In the threshold voltage compensation period, the first transistor 21 because the scanning pulse SCAN1 (i) supplied by the scan driver 14 (see Fig. 1) through the first scanning line 15A is at the " L " level. ) Is off. The fifth transistor 25 is on because the scanning pulse SCAN4 (i) supplied through the fourth scanning line 15D is at the "H" level. Therefore, the power supply voltage VCC3, that is, the fixed voltage V ₀ is supplied from the third power supply line 33 to the input terminal of the first capacitor 26 through the fifth transistor 25.

At the same time, since the scanning pulse SCAN2 (i) supplied through the second scanning line 15B is at the "H" level, the third transistor 23 is in the on mode. Further, since the scanning pulse SCAN3 (i) supplied through the third scanning line 15C is at the "L" level, the fourth transistor 24 is off. Therefore, the first capacitor 26 is charged from its output terminal through the source terminal and the drain terminal of the third transistor 23. If the threshold voltage compensation period is long enough, the voltage between the gate terminal and the source terminal of the second transistor 22 converges to the threshold voltage Vth (<0) of the transistor.

At the beginning of the data writing period, the scanning pulse SCAN1 (i) is at the " H " level and the first transistor 21 is in the on mode. In addition, the scanning pulse SCAN4 (i) is at the " L " level and the fifth transistor 25 is in the off mode. Therefore, the data voltage V ₀ + Vdata (Vdata <0) is supplied from the signal line 13 through the first transistor 21. In this case, since the scanning pulse 2 (i) is at the "L" level, the third transistor 23 is in the off mode.

Equations (2) and (3) mentioned above are also established in the pixel circuit 11A of the first circuit. Therefore, the electric current I _oled flowing through the organic-EL element 20 is not affected by the threshold voltage Vth of the transistor. In other words, the threshold voltage Vth of the second transistor 22 is compensated for in each pixel.

Similarly, the time required for the threshold voltage compensation period can be represented by equations (4) and (5). In the pixel circuit 11A of the first circuit, however, the connection between the input terminal of the first capacitor 26 and the signal line 13 is controlled by the first transistor 21 during the threshold voltage compensation period, and the first capacitor ( The connection between the input terminal of 26 and the power supply line 33 is controlled by the fifth transistor 25. Therefore, during the threshold voltage compensation period, the input terminal of the capacitor 26 is connected to the power supply line 33 to receive the power supply voltage VCC3, that is, the fixed voltage V ₀ . On the other hand, during the data writing period, the input terminal of the capacitor 26 is connected to the signal line 13 to receive the data voltage V ₀ + Vdata.

By controlling the switching of the input terminal of the capacitor 26 between the threshold voltage compensation period and the data writing period, one pixel is in the data writing period to write data from the signal line 13, while at the same time, the other pixel is at the threshold voltage. It is connected to the power supply line 33 so as to be within a compensation period. Moreover, the plurality of pixels can easily be within the threshold voltage compensation period. As a result, a sufficient amount of time for the threshold voltage compensation period can be maintained.

Specifically, in the row of pixels in the pixel circuit 11A of the first circuit, as can be seen from the timing diagram of FIG. 3, one horizontal period is equal to the data writing period and two horizontal periods are critical before the data writing period. It is set as the voltage compensation period. Considering the timing, it can be seen that one pixel in the i th row is within the data writing period, while the other two pixels in the (i + 1) th and (i + 2) th rows are within the threshold voltage compensation period. It can also be seen from the figure.

Therefore, the threshold voltage compensation period and the data writing period are not required to be within one horizontal period. This achieves a high definition display and also maintains a sufficient amount of time for the threshold voltage compensation period to allow a uniform display picture. Furthermore, as can be seen from the timing chart of Fig. 3, since the signal line 13 is required to continuously supply only luminance data, the drive waveform of the signal line 13 is simple. The driving of the signal line 13 may be performed, for example, with a waveform similar to that of a normal liquid crystal display. Thus, the structure of the data driver 12 (see Fig. 1), that is, the signal line driver circuit, is simplified.

[Second circuit]

4 is a circuit diagram of a pixel circuit 11B according to the second circuit. In Fig. 4, the same components as in Fig. 2 are denoted by the same reference numerals. As can be seen from FIG. 4, the pixel circuit 11B has a point where the circuit 11B includes an organic-EL element 20, five transistors 21 to 25, and two capacitors 26 and 27. Is the same as the pixel circuit 11A. The only structural difference between the two circuits 11A and 11B is the connection position of the second capacitor 27 in the circuit 11B.

Hereinafter, the connection of each circuit element will be described in detail. The source terminal of the first transistor 21 is connected to the signal line 13, and the gate terminal of the transistor 21 is connected to the first scanning line 15A. The input terminal of the first capacitor 26 is connected to the drain terminal of the first transistor 11. The gate terminal of the second transistor 22 is connected to the output terminal of the first capacitor 26, and the source terminal of the transistor 22 is, for example, a power supply voltage VCC1 which can be a positive supply voltage. Is connected to the first power supply line 31.

The first end of the second capacitor 27 is connected to the first power line 31, the second end is connected to the drain terminal of the first transistor 21, and is an output end of the first capacitor 26. The gate terminal of the third transistor 23 is connected to the second scanning line 15B, the source terminal is connected to the gate terminal of the second transistor 22, and the drain terminal is connected to the drain terminal of the second transistor 22. Connected. The gate terminal of the fourth transistor 24 is connected to the third scanning line 15C, and the source terminal is connected to the drain terminal of the second transistor 22.

The gate terminal of the fifth transistor 25 is connected to the fourth scanning line 15D, and the source terminal is, for example, the third power line 33 of the power supply voltage VCC3, which can be a positive supply voltage. ), The drain terminal is connected to the drain terminal of the first transistor 21, and is an input terminal of the first capacitor 26. The anode of the organic-EL element 20 is connected to the drain terminal of the fourth transistor 24 and the cathode is connected to the second power line 32 of the power supply voltage VCC2, which can be a ground potential, for example. do.

In the pixel circuit 11B, the operation of threshold voltage compensation and data writing and holding are basically the same as the pixel circuit 11A. Equations (2) and (3) hold in the pixel circuit 11A, but the following equations (6) and (7) hold in the pixel circuit 11B.

Vgs = Vth + Vdata ... (6)

L _oled ∝ I _oled = k {Vdata} ² ... (7)

As can be seen from equations (6) and (7), the electric current I _oled flowing through the organic-EL element 20 is not affected by the threshold voltage Vth of the transistor. In other words, the threshold voltage Vth of the second transistor 22 is compensated for in each pixel. In addition, the input voltage amplitude Vdata of the data becomes the gate voltage amplitude of the second transistor 22, whereby the amplitude of the signal line 13 becomes small and a low power consumption is achieved.

The threshold voltage compensation pixel circuit requires a plurality of scanning lines. In the pixel circuit 11A of the first circuit and the pixel circuit 11B of the second circuit, four scanning lines 15A, 15B, 15C, and 15D are used. However, the second scanning line 15B and the fourth scanning line 15D must respectively drive the third transistor 23 and the fifth transistor 25 in the ON mode only during the threshold voltage compensation period. In addition, the third scanning line 15C must drive the fourth transistor 24 in the off mode only during the threshold voltage compensation period. Thus, two or all three of the second, third and fourth scanning lines 15B, 15C and 15D may be joined together.

The driving of the third, fourth and fifth transistors 23, 24 and 25 is controlled by the respective second, third and fourth scanning lines 15B, 15C and 15D. When the third scanning line 15C is combined with one of the at least two scanning lines 15B and 15D, the conductivity type of the fourth transistor 24 is different from that of the third and fifth transistors 23 and 25. Must be reversed.

Another example of the pixel circuit will be described. In order to explain each pixel circuit of the following example, the basic structure of the pixel circuit 11B of the second circuit having the second capacitor 27 connected adjacent to the input terminal of the first capacitor 26 will be used. Otherwise, the pixel circuit 11A of the first circuit will likewise be used as the basic structure.

[Third circuit]

5 is a circuit diagram of a pixel circuit 11C according to the third circuit. In FIG. 5, the same components as in FIG. 4 are denoted by the same reference numerals. In the pixel circuit 11C, the second scanning line 15B and the fourth scanning line 15D are coupled together to drive the third transistor 23 and the fifth transistor 25 by a common scanning pulse SCAN2. do.

[4th circuit]

6 is a circuit diagram of a pixel circuit 11D according to the fourth circuit. In FIG. 6, the same components as in FIG. 4 are denoted by the same reference numerals. In the pixel circuit 11D, the second scanning line 15B and the third scanning line 15C are coupled together to drive the third transistor 23 and the fourth transistor 24 by a common scanning pulse SCAN2. do. In this case, the third transistor 23 and the fourth transistor 24 have opposite conductivity types. In the fourth circuit, an N-channel transistor is used for the third transistor 23 and a P-channel transistor is used for the fourth transistor 24.

[5th circuit]                     

7 is a circuit diagram of a pixel circuit 11E according to the fifth circuit. In FIG. 7, the same components as in FIG. 4 are denoted by the same reference numerals. In the pixel circuit 11E, the third scanning line 15C and the fourth scanning line 15D are coupled together to drive the fourth transistor 24 and the fifth transistor 25 by a common scanning pulse SCAN2. do. In this case, the fourth transistor 24 and the fifth transistor 25 have opposite conductivity types. In the fifth circuit, a P-channel transistor is used for the fourth transistor 24 and an N-channel transistor is used for the fifth transistor 25.

[6th circuit]

8 is a circuit diagram of a pixel circuit 11F according to the sixth circuit. In FIG. 8, the same components as in FIG. 4 are denoted by the same reference numerals. In the pixel circuit 11F, the second scanning line 15B, the third scanning line 15C, and the fourth scanning line 15D are coupled together to form the third transistor 23 by the common scanning pulse SCAN2. , The fourth transistor 24 and the fifth transistor 25 are driven. In this case, the third transistor 23 and the fifth transistor 25 have a conductivity type opposite to that of the fourth transistor 24. In the sixth circuit, an N-channel transistor is used for the third and fifth transistors 23 and 25 and a P-channel transistor is used for the fourth transistor 24.

In the pixel circuits 11C to 11F according to the third to sixth circuits, the operations of threshold voltage compensation, data writing and data holding are basically the same as in the pixel circuit of the second circuit, respectively. Therefore, the threshold voltage compensation function of the pixel circuits 11C to 11F is also performed in the same manner as the pixel circuit 11B.

Since two or three of the second, third, and fourth scanning lines 15B, 15C, and 15D are combined together in each of the pixel circuits 11C to 11F, the reduction in the number of scanning lines results in a smaller pixel circuit. Have a structure. The combination of scanning lines also allows to reduce the number of scanning pulses output from the scan driver 14 (see FIG. 1), and also to reduce the size of the output buffer of the scan driver 14, for example. This contributes to the simplification of the structure of the scan driver 14.

In the pixel circuits 11A to 11F according to the first to sixth circuits, the voltage values of the power supply voltage VCC3 of the third power supply line 33 and the power supply voltage VCC1 of the first power supply line 31 are respectively. Is required to be set differently. However, the difference in voltage values is not specified.

[7th circuit]

9 is a circuit diagram of a pixel circuit 11G according to the seventh circuit. In Fig. 9, the same components as in Fig. 4 are denoted by the same reference numerals. In the pixel circuit 11G, the first power supply line 31 and the third power supply line 33 are coupled together to supply the power supply voltage VCC1, that is, the fixed voltage V ₀ to the first capacitor 26. The rest of the structure is the same as in the pixel circuit 11B of the second circuit. Therefore, the threshold voltage compensation function of the pixel circuit 11G is performed in the same manner as the pixel circuit 11B.

By combining the first power supply line 31 and the third power supply line 33 together, not only the same threshold voltage compensation function is achieved as in the pixel circuit 11B but also the number of power supply lines is reduced, thus making the structure smaller. A pixel circuit having is achieved. Also, the reduction of one power supply voltage simplifies the structure of the circuit.

Although the first power supply line 31 and the third power supply line 33 are coupled in the pixel circuit 11G using the basic structure of the pixel circuit 11B of the second circuit, the pixel circuit 11G is the third circuit. As in the pixel circuit 11C, the second scanning line 15B may further have a combined second scanning line 15B and a fourth scanning line 15D.

In each of the pixel circuits 11A to 11G, each of the source terminals of the first to fifth transistors 21 to 25 corresponds to the first electrode, and each of the drain terminals of the first to fifth transistors 21 to 25 is formed. It corresponds to the second electrode. The conductivity type of the first to fifth transistors 21 to 25 is not limited to each circuit example and may be changed to the opposite conductivity type as desired.

Next, a process of determining the voltage of the signal line 13 will be described. FIG. 10 shows the relationship between the input data (gray shade) and the voltage in the conventional pixel circuit of FIG. 12 having two transistors and in the pixel circuit 11B of the second circuit in FIG. The relationship of the voltage is between the signal line 103 of the conventional pixel circuit and the signal line of the pixel circuit 11B.

In the conventional pixel circuit, the voltage of the signal line 103 is affected by the power supply voltage VCC1. Therefore, when the power supply voltage VCC1 is large, the voltage of the signal line 103 also tends to be large. On the other hand, since Expression (7) is established in the pixel circuit 11B of the second circuit, the luminance data is determined by the difference with respect to the power supply voltage VCC3. Therefore, the power supply voltage VCC3 can be set substantially small regardless of the power supply voltage VCC1.
By setting the power supply voltage VCC3 extremely small with respect to the power supply voltage VCC1, the signal line driving circuit can be reduced so that the voltage of the data driver 12, that is, low power consumption can be achieved. In actual pixel circuits, since high parasitic capacitance exists between the interconnects and the transistors, it is difficult to supply accurate luminance data. A variable power supply voltage VCC3 can be used to fine tune the accurate grayscale display. This can be used similarly in the pixel circuits 11C to 11F of the third to sixth circuits, respectively.

In the above embodiment, the organic-EL element is used as the display element of each pixel, and the polysilicon thin film transistor is used as the active element. Although the present invention has been described as an example of an active-matrix organic-EL display having an organic-EL element formed on a polysilicon thin film transistor substrate, the present invention is not limited to an active-matrix organic-EL display. Therefore, the present invention is applicable to all kinds of active-matrix display devices having display elements for all pixels and capable of holding luminance data in each pixel.

The present invention can provide a high definition active-matrix display device using a threshold voltage compensation pixel circuit to improve the uniformity of the display image and to ensure a sufficient length of the threshold voltage compensation period despite the length of one horizontal period.

Thus, by supplying a fixed voltage required for threshold voltage compensation from the power supply line and not from the signal line, compensation of the threshold voltage is performed while simultaneously writing display data from the signal line in another pixel. In either row of pixels, one horizontal period may be set as the data write period and any length of the period may be set as the threshold voltage compensation period before the data write period. Thus, sufficient time for the threshold voltage compensation period can be maintained. This accurately compensates for the irregularities of the threshold voltages of the transistors in each pixel in order to improve the uniformity of brightness and to achieve high clarity of the display.

The present invention requires the continuous supply of only the data voltage, which simplifies the structure of the signal line driver circuit. Furthermore, since the power supply voltage of the signal line driver circuit can be reduced to the extent that the fixed voltage is eliminated, low power consumption can be achieved for the entire display.

Claims (12)

The active matrix display device Pixel circuits arranged in a matrix, Each signal line interconnected corresponding to a column of pixel circuits arranged in the matrix; A first scanning line, a second scanning line, a third scanning line, and a fourth scanning line interconnected to correspond to the rows of the pixel circuits arranged in the matrix, Each of the pixel circuits, A first transistor having a gate terminal connected to the first scanning line and a first electrode terminal connected to one of the signal lines; A first capacitor having a first end connected to the second electrode terminal of the first transistor; A second capacitor having a first terminal connected to a first end or a second end of the first capacitor, A second transistor having a gate terminal connected to a second end of the first capacitor and a first electrode terminal connected to a first power line; A third transistor having a gate terminal connected to the second scanning line, a first electrode terminal connected to a gate terminal of the second transistor, and a second electrode terminal connected to a second electrode terminal of the second transistor; A fourth transistor having a gate terminal connected to the third scanning line and a first electrode terminal connected to a second electrode terminal of the second transistor; A fifth transistor having a gate terminal connected to the fourth scanning line, a first electrode terminal connected to a third power supply line, and a second electrode terminal connected to a second electrode terminal of the first transistor; And a display element connected to both the second electrode terminal and the second power supply line of the fourth transistor. The method of claim 1, And the third transistor and the fifth transistor have the same conductivity type, and the second scanning line and the fourth scanning line are coupled as a common line. The method of claim 1, And the third transistor and the fourth transistor have opposite conductivity types, and the second scanning line and the third scanning line are coupled as a common line. The method of claim 1, And the fourth transistor and the fifth transistor have opposite conductivity types, and the third scanning line and the fourth scanning line are coupled as a common line. The method of claim 1, The third transistor and the fifth transistor have a conductivity type opposite to that of the fourth transistor, and an active-matrix organic material in which the second scanning line, the third scanning line, and the fourth scanning line are combined as a common line. -EL display. The method of claim 1, And an active-matrix organic-EL display device in which the first power supply line and the third power supply line are coupled as a common line. The method of claim 1, The active-matrix organic-EL display device of which the power supply voltage of the third power supply line is lower than the power supply voltage of the first power supply line. The method of claim 7, wherein An active-matrix organic-EL display device, wherein the power supply voltage of the third power line is variable. The method of claim 1, And the first transistor to the fifth transistor are polysilicon thin film transistors. The method of claim 1, An active-matrix organic-EL display device, wherein the display device is an electroluminescent organic device comprising an organic layer having a light emitting layer disposed between the first electrode and the second electrode. Pixel circuits arranged in a matrix, Each signal line interconnected corresponding to a column of pixel circuits arranged in the matrix; A first scanning line, a second scanning line, a third scanning line, and a fourth scanning line interconnected to correspond to the rows of the pixel circuits arranged in the matrix, Each of the pixel circuits, A first transistor having a gate terminal connected to the first scanning line and a first electrode terminal connected to one of the signal lines; A first capacitor having a first end connected to the second electrode terminal of the first transistor; A second capacitor having a first terminal connected to a first end or a second end of the first capacitor, A second transistor having a gate terminal connected to a second end of the first capacitor and a first electrode terminal connected to a first power line; A third transistor having a gate terminal connected to the second scanning line, a first electrode terminal connected to a gate terminal of the second transistor, and a second electrode terminal connected to a second electrode terminal of the second transistor; A fourth transistor having a gate terminal connected to the third scanning line and a first electrode terminal connected to a second electrode terminal of the second transistor; A fifth transistor having a gate terminal connected to the fourth scanning line, a first electrode terminal connected to a third power supply line, and a second electrode terminal connected to a second electrode terminal of the first transistor; A method of driving an active-matrix display device comprising a display element connected to both the second electrode terminal and the second power supply line of the fourth transistor, The method, Compensating the threshold voltage of the second transistor at each pixel by turning off the first transistor and the fourth transistor while turning on the third transistor and the fifth transistor; And turning on the first transistor while turning off the third transistor and the fifth transistor, and writing display data from the signal line to each pixel. The method of claim 11, A driving method of an active-matrix organic-EL display device, wherein a period for compensating the threshold voltage and a period for writing the display data are simultaneously present in pixels connected along the same signal line and in different rows.

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