KR100947774B1 - Driving device of liquid crystal display - Google Patents

Abstract

The present invention relates to a driving device of a liquid crystal display device, comprising: a liquid crystal panel driven by being divided into a left part and a right part; At least one first data integrated circuit for driving data lines formed in the left portion; At least one second data integrated circuit for driving data lines formed in the right part; Third data integrated circuits positioned at boundary portions of the left and right portions to drive data lines formed on the left side and data lines formed on the right side; And a timing controller for generating control signals using the synchronization signals supplied from the outside and dividing the data supplied from the outside into the left portion data and the right portion data to supply the data integrated circuits.

Description

Apparatus of Driving Liquid Crystal Display Device             

1 is a view showing a conventional liquid crystal display device.

2 is a view showing a liquid crystal display device according to another conventional embodiment.

3 is a diagram illustrating data integrated circuits included in the data driver of FIG. 2.

FIG. 4 is a detailed view of the data integrated circuit shown in FIG. 3;

5 is a view showing a liquid crystal display device according to an embodiment of the present invention.

Fig. 6 shows a first embodiment of a data integrated circuit located at the boundary between the left side and the right side;

Fig. 7 shows a second embodiment of a data integrated circuit located at the boundary between the left side and the right side;

<Description of Symbols for Main Parts of Drawings>

2,12,52 LCD panel 4,18,20,58,60 Data driver

6: gate driver 8: timing controller                 

10: common voltage generator 14,54: left side

16,56: right part 22,68: timing controller

24,64,66: data integrated circuit 30,90,120: signal controller

32,88,118: Gamma voltage part 34,74,104,105: Shift register part

36,76,106: Latch part 38,78,108: DAC part

40, 42, 80, 82, 110, 112: decoding unit 44, 84, 114: multiplexer

46,86,116: Output buffer part 70,72: Memory

92: switching unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device of a liquid crystal display device, and more particularly, to a driving device of a liquid crystal display device which enables left / right division driving in an LCD including an odd data integrated circuit.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel having a pixel matrix and a driving circuit for driving the liquid crystal panel. The driving circuit drives the pixel matrix so that the image information is displayed on the display panel.

1 is a view showing a conventional liquid crystal display device.                         

Referring to FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2, a data driver 4 for driving data lines DL1 to DLm of the liquid crystal panel 2, and a liquid crystal panel 2. A gate driver 6 for driving the gate lines GL0 to GLn, a timing controller 8 for controlling driving timing of the data and gate drivers 4 and 6, and a common voltage Vcom to the liquid crystal cell. And a common voltage generator 10 for supplying the same.

The timing controller 8 receives a data clock DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable DE, and data from an external system. The timing controller 8 that receives the data rearranges the data and supplies the data to the data driver 4. The timing controller 8 receiving the data clock, the horizontal synchronization signal, the vertical synchronization signal, and the data enable signal receives control signals such as timing signals and polarity inversion signals for controlling the timing of the data and gate drivers 4 and 6. Will occur.

The liquid crystal panel 2 is connected to the thin film transistor TFT formed at the intersection of the n gate lines GL1 to GLn and the m data lines DL1 to DLm, and is formed in a matrix form. The liquid crystal cells are arranged as.

The thin film transistor TFT supplies data from the data lines DL1 to DLm to the liquid crystal cell in response to gate signals from the gate lines GL1 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween, and a pixel electrode connected to the thin film transistor TFT, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor Cst connected to the previous gate line to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

The gate driver 6 sequentially supplies gate signals to the gate lines GL1 to GLn according to a control signal from the timing controller 8. The data driver 4 converts the data R, G, and B supplied from the timing controller 8 into a video signal, which is an analog signal, and converts the data signal 4 into one video signal every 1 horizontal period in which the gate signals are supplied to the gate lines GL1 to GLn. The video signal for the horizontal line is supplied to the data lines DL1 to DLm.

The data driver 4 selects a gamma voltage having a predetermined DC level according to the luminance values of the data R, G, and B, and supplies the selected gamma voltage to the data lines DL1 to DLm.

The common voltage generator 10 generates a common voltage Vcom and supplies the generated common voltage Vcom to a common electrode which is one side of the liquid crystal capacitor Clc.

In the conventional liquid crystal display device, since m pieces of data must be supplied to the data driver within one horizontal period, the data clock must have a high frequency. As such, when the data clock has a high frequency, high electromagnetic interference (EMI) is generated in the liquid crystal display. In addition, the conventional liquid crystal display device has a problem that a high transfer rate is required and a lot of power consumption is required because m data must be supplied to the data driver within one horizontal period.

In order to solve this problem, a liquid crystal display device according to another exemplary embodiment as shown in FIG. 2 has been proposed.                         

2 is a diagram illustrating a liquid crystal display according to another exemplary embodiment of the prior art. In the configuration of FIG. 2, detailed structures of the gate driver and the liquid crystal cell are omitted.

Referring to FIG. 2, a liquid crystal display according to another exemplary embodiment includes a liquid crystal panel 12 divided into a left portion 14 and a right portion 16, and data lines DL1 to DLm / of the left portion 14. 2) a first data driver 18 for driving the second data driver; a second data driver 20 for driving the data lines DLm / 2 + 1 to DLm of the right side 16; A timing controller 22 is provided for controlling the drive timing of the two data drivers 18 and 20.

The liquid crystal panel 12 is driven by being divided into a left portion 14 and a right portion 16. Here, the left part 14 and the right part 16 are driven simultaneously.

The timing controller 22 receives a data clock DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable DE, and data from an external system. The timing controller 22 receiving the data divides the data into data of the left part 14 and the right part 16, and simultaneously supplies the divided data to the first and second data drivers 18 and 20. The timing controller 22 receiving the data clock, the horizontal synchronization signal, the vertical synchronization signal, and the data enable signal controls the timing signals and the polarity inversion signal for controlling the first and second data drivers 18 and 20. Generate signals.

The first data driver 18 converts the data supplied thereto into an analog video signal and supplies the data to the data lines DL1 to DLm / 2 of the left part 14. The second data driver 20 converts the data supplied thereto into an analog video signal and supplies the data to the data lines DLm / 2 + 1 to DLm of the right side 16. In this case, the video signals supplied from the first and second data drivers 18 and 20 are simultaneously supplied every one horizontal period in which the gate signals are supplied to the gate lines.

Each of the first data driver 18 and the second data driver 20 includes the same number of integrated circuits 24 as shown in FIG. 3. Each of the data ICs 24 converts an analog video signal and supplies the data supplied thereto to the data lines DL.

To this end, each of the data ICs 24 includes a shift register 34 for sequentially supplying a sampling signal as shown in FIG. 4, and sequentially latching and simultaneously outputting data in response to the sampling signal. A latch unit 36, a digital-to-analog converter (hereinafter referred to as a "DAC unit") 38 for converting data (Data) from the latch unit 36 into an analog video signal, and a DAC unit 38. And an output buffer section 46 for buffering and outputting video signals from the video signal.

In addition, each of the data ICs 24 includes a signal control unit 30 relaying control signals and data Data supplied from the timing control unit 22, and a positive and negative polarity required by the DAC unit 38. A gamma voltage unit 32 for supplying gamma voltages is provided. The data ICs 24 having this configuration drive i (eg, 384 and 480) channels and i data lines DL.

The signal controller 30 controls various control signals (SSP, SSC, SOE, REV, POL, etc.) and data from the timing controller 22 to be output to the corresponding components.

The gamma voltage unit 12 subdivides and outputs a plurality of gamma reference voltages inputted from a gamma reference voltage generator (not shown) for each gray.

The shift register 34 includes a plurality of shift registers to sequentially shift the source start pulse SSP from the signal controller 10 in correspondence with the source sampling clock SSC to output a sampling signal.

The latch unit 36 sequentially samples and latches the data Data from the signal control unit 30 in predetermined units in response to the sampling signal from the shift register unit 34. To this end, the latch unit is composed of i latches to latch i data, each of which has a size corresponding to the number of bits (eg, 3 bits or 6 bits) of the data. The latch unit 36 simultaneously outputs the n pieces of latched data in response to a source output enable (SOE) signal from the signal controller 30.

The DAC unit 38 simultaneously converts the data Data from the latch unit 36 into positive and negative video signals and outputs the same. To this end, the DAC unit 38 includes a positive (P) decoding unit 40 and a N (Netative) decoding unit 42, and a P decoding unit 40 and an N decoding unit 42 commonly connected to the latch unit 36. Is provided with a multiplexer (MUX) 44 for selecting the output signal.

The i P decoders included in the P decoding unit 40 convert the data input from the latch unit 36 into a positive video signal. The i N decoders included in the N decoding unit 42 convert the data input from the latch unit 36 into a negative video signal.

The multiplexer (MUX) 44 selectively outputs the video signals from the P decoding unit 40 and the N decoding unit 42 in response to the polarity control signal POL from the signal control unit 30. The output buffer unit 46 buffers the video signals from the multiplexer 44 and supplies them to the data lines DL.

Since the liquid crystal display shown in FIG. 2 supplies m / 2 pieces of data to each of the first and second data drivers 18 and 20 during one horizontal period, the frequency is lower than that of the liquid crystal display shown in FIG. Has a data clock of EMI, thereby reducing EMI. In addition, since m / 2 pieces of data are supplied to the first and second data drivers 18 and 20, respectively, transmission speed and power consumption can be lowered as compared to the liquid crystal display shown in FIG. It can be easily applied to the liquid crystal display of the screen.

However, in order to divide the liquid crystal panel 12 into the left portion 14 and the right portion 16 as shown in FIG. 2, the liquid crystal panel 12 is included in the first data driver 18 and the second data driver 20. The number of integrated circuits (hereinafter referred to as "ICs") must be the same (i.e., the total number of data ICs must be set to an even number).

In other words, the first data driver 18 and the second data driver 20 simultaneously receive data from the timing controller 22. Therefore, simultaneous driving is possible only if the number of data ICs (D-ICs) 24 included in each of the data drivers 18 and 20 is the same. That is, if the number of data ICs 24 included in the first and second data drivers 18 and 20 is different, the amount of data to be supplied to the first data driver 18 or the second data driver 20 is different. As a result, the liquid crystal panel 12 cannot be divided into the left portion 14 and the right portion 16.                         

On the other hand, currently used data ICs 24 are released with a fixed number of channels. For example, the data IC 24 has a fixed number of channels, such as 384 channels and 480 channels. As described above, since the number of channels of the data IC 24 is fixed and released, the liquid crystal panel 12 may not be divided into the left portion 14 and the right portion 16. For example, in the case of the SVGA (800 × 600) class liquid crystal panel 12, 800 × 3 (R, G, B subpixels) = 2400 (number of data lines) channels are required.

Here, the liquid crystal panel 12 is conventionally driven by using seven data ICs 24 (2688 channels) having 384 channels. That is, in the conventional SVGA class liquid crystal panel 12, seven data ICs 24 are used, and thus, the liquid crystal panel 12 cannot be divided into the left portion 14 and the right portion 16.

Accordingly, an object of the present invention is to provide a driving device of a liquid crystal display device which enables left / right division driving in a liquid crystal display device including an odd number of data integrated circuits.

In order to achieve the above object, the driving apparatus of the liquid crystal display device of the present invention comprises: a liquid crystal panel driven by being divided into a left part and a right part; At least one first data integrated circuit for driving data lines formed in the left portion; At least one second data integrated circuit for driving data lines formed in the right part; Third data integrated circuits positioned at boundary portions of the left and right portions to drive data lines formed on the left side and data lines formed on the right side; And a timing controller for generating control signals using the synchronization signals supplied from the outside and dividing the data supplied from the outside into the left portion data and the right portion data to supply the data integrated circuits.
The timing controller supplies a first selection signal to the third data integrated circuit when the right side data is supplied to the third data integrated circuit, and the third data when the left data is supplied to the third data integrated circuit. The second selection signal is supplied to the integrated circuit.

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The timing controller includes a first memory in which left side data is stored, and a second memory in which right side data is stored.

The third data integrated circuit may include a signal controller for relaying a control signal and outputting any one of left side data and right side data in response to any one of a first selection signal and a second selection signal; A shift register unit for receiving a source start pulse and a source sampling clock among the control signals and outputting i / 2 (i is a natural number) sampling signals while shifting the source start pulse corresponding to the source sampling clock; A latch unit for storing i / 2 left-side data and i / 2 right-side data supplied to itself corresponding to the sampling signal supplied from the shift register section; A switching unit is provided between the shift register unit and the latch unit and controls a sampling signal path corresponding to the first selection signal and the second selection signal.

When the first selection signal is supplied, the signal controller supplies the right side data to the first to i / 2th latches included in the latch unit, and the switching unit to the first to i / 2th latches included in the latch unit. To be supplied.

When the second selection signal is supplied, the signal controller supplies the left side data to the i / 2 + 1 th latch to the i th latch included in the latch unit, and the switching unit includes the i / 2 + 1 th latch to i included in the latch unit. The sampling signal is supplied to the first latch.

The third data integrated circuit may include a signal controller for relaying a control signal and outputting any one of left side data and right side data in response to any one of a first selection signal and a second selection signal; A first shift register section for supplying i / 2 sampling signals (i is a natural number) to the first to i / 2th latches when a source start pulse and a source sampling clock are input from the signal controller; and a source from the signal controller. A second shift register section for supplying i / 2 sampling signals (i is a natural number) to the i / 2 + 1 th latch to the i th latch when the start pulse and the source sampling clock are input, and the first and second And a latch portion for storing i / 2 left portion data and i / 2 right portion data supplied to itself corresponding to the sampling signal supplied from the shift register portion.

When the first selection signal is supplied, the signal controller supplies the right side data to the i / 2 + 1 th latch to the i th latch included in the latch unit, and supplies a source start pulse and a source sampling clock to the second shift register unit. .                     

When the second selection signal is supplied, the signal controller supplies the right side data to the first to i / 2th latches included in the latch unit, and supplies a source start pulse and a source sampling clock to the first shift register unit.

The third data integrated circuit includes a digital-analog converter for receiving data stored in the latch unit and converting the data into a positive video signal and a negative video signal, and the data converted by the digital-analog converter are connected to the third data integrated circuit. and an output buffer section for supplying i data lines.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 7.

5 is a view showing a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 5, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 52 divided into a left portion 54 and a right portion 56, and data lines DL1 to DLm / of the left portion 54. 2) a first data driver 58 for driving the second data driver; a second data driver 60 for driving the data lines DLm / 2 + 1 to DLm of the right part 56; The timing control part 68 is provided for controlling the drive timing of the two data drive parts 58 and 60.

The liquid crystal panel 52 is divided into a left portion 54 and a right portion 56 to be driven. Here, the left portion 54 and the right portion 56 are driven at the same time.

The timing controller 68 receives a data clock DLCK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable DE, and data from an external system. The timing controller 68 receiving the data divides the data into the left portion 54 data and the right portion 56 data. Here, the left portion 54 data is stored in the second memory 72 and the right portion 56 data is stored in the first memory 70.

The timing controller 68 receives the data clock, the horizontal synchronization signal, the vertical synchronization signal, and the data enable signal, and controls the timing signals and the polarity inversion signal for controlling the first and second data drivers 58 and 60. Generate signals. In addition, the timing controller 68 which receives the data clock force, the horizontal synchronization signal, the vertical synchronization signal, and the data enable signal generates a selection signal and supplies the selected signal to the first and second data drivers 58 and 60. The selection signal is supplied to the data IC 66 located at the boundary between the left portion 54 and the right portion 56)

The first data driver 58 converts the data supplied thereto into an analog video signal and supplies the data to the data lines DL1 to DLm / 2 of the left part 54. The second data driver 60 converts the data supplied thereto into an analog video signal and supplies the data to the data lines DLm / 2 + 1 to DLm of the right side 56. Here, the total number of data ICs 64, 66 included in the first and second data drivers 58, 60 is set to an odd number. Accordingly, the first and second data drivers 58 and 68 share the data IC 66 provided at the boundary between the left portion 54 and the right portion 56. In other words, the data IC 66 provided at the boundary between the left portion 54 and the right portion 56 supplies the video signal to the data lines DL of the left portion 54 and the right portion 56.                     

Referring to the operation of the liquid crystal display according to the present invention, first, the timing controller 68 first connects the first data data1 stored in the second memory 72 to the first data line DL1. ) Is sequentially supplied to the data IC 66 connected to the m / 2th data line DLm / 2. In addition, the timing controller 68 controls the second data data2 stored in the first memory 70 from the data IC 66 connected to the m / 2 + 1 th data line DLm / 2 + 1. Supply is sequentially performed to the data IC 64 connected to the line DLm. Here, the data IC 66 positioned at the boundary between the left part 54 and the right part 56 is first supplied with two data data2 (data of DLm / 2 + 1 to DL3i) and after a predetermined time, the first data ( data1) (DL2i + 1 to DLm / 2).

When the first and second data data1 and data2 are supplied to the data ICs 64 and 66, each of the data ICs 64 and 66 converts the data supplied thereto into a video signal and converts the video signal into a gate signal. Is supplied to the company as data lines DL1 through DLm for one horizontal period. Here, the configuration and operation of the remaining data ICs 64 except for the data IC 66 positioned at the boundary between the left portion 54 and the right portion 56 are the same as those of the conventional data IC 24 shown in FIG. 4. Therefore, detailed description will be omitted.

FIG. 6 is a diagram showing the first embodiment of the data IC 66 located at the boundary between the left portion 54 and the right portion 56. FIG.

Referring to FIG. 6, the data IC 66 positioned at the boundary between the left portion 54 and the right portion 56 includes a shift register portion 74 which sequentially supplies a sampling signal, and data (data1) in response to the sampling signal. and latch portion 76 for latching and simultaneously outputting data2, and between the shift register portion 74 and the latch portion 76 to control the path of the sampling signal supplied from the shift register portion 74. A switching unit 92, a DAC unit 78 for converting data (data1, data2) from the latch unit 76 into an analog video signal, and an output buffer for buffering and outputting the video signal from the DAC unit 78. The part 86 is provided.

In addition, the data IC 66 includes a signal control unit 90 for relaying control signals supplied from the timing control unit 68 and data data 1 and data 2, and a positive and negative polarity required by the DAC unit 78. A gamma voltage unit 88 for supplying gamma voltages is provided. The data IC 66 having such a configuration drives i (i is a natural number, for example, i is 348, 480) channels, i.e., i data lines DL2i + 1 to 3i.

The signal controller 90 controls various control signals (SSP, SSC, SOE, POL, etc.) and data (data1, data2) from the timing controller 68 to be output to the corresponding components. In addition, the signal controller 30 controls the output paths of the data data1 and data2 in response to the selection signal supplied to the signal controller 30. For example, the signal controller 90 supplies the data data2 inputted to the first selection signal to the i / 2 + 1 th latch to the i th latch included in the latch unit 76. When the second selection signal is input to the signal controller 90, the data data1 input to the signal controller 90 is supplied to the first to i / 2 latches included in the latch 76.

The gamma voltage unit 88 divides and outputs a plurality of gamma reference voltages inputted from a gamma reference voltage generator (not shown) for each gray.

The shift register unit 74 includes a plurality of shift registers to sequentially shift the source start pulse SSP from the signal controller 90 in correspondence to the source sampling clock SSC to output a sampling signal. Here, the shift register section 74 outputs i / 2 sampling signals.

The switching unit 92 controls the path of the sampling signal output from the shift register unit 74 in response to the selection signal supplied from the timing control unit 68. For example, the switching unit 92 sequentially supplies a sampling signal input to the i / 2 + 1 th latch to the i th latch when the first selection signal is input. When the second selection signal is input, the switching unit 92 sequentially supplies the sampling signal input thereto to the first to i / 2th latches.

The latch unit 76 sequentially samples and latches data data1 and data2 supplied from the signal controller 90 in response to the sampling signal from the switching unit 92. For this purpose, the latch unit is composed of i latches for latching i data (data1, data2), each of which has a size corresponding to the number of bits (for example, 3 bits or 6 bits) of the data. The latch unit 76 simultaneously outputs the latched n data in response to the source output enable (SOE) signal from the signal controller 90.

The DAC unit 78 simultaneously converts the data data1 and data2 from the latch unit 76 into positive and negative video signals and outputs the same. To this end, the DAC unit 78 selects the P decoding unit 80 and the N decoding unit 82, which are commonly connected to the latch unit 76, and the output signals of the P decoding unit 80 and the N decoding unit 82. A multiplexer (MUX: 84) is provided.

The i P decoders included in the P decoding unit 80 convert the data input from the latch unit 76 into a positive video signal. The i N decoders included in the N decoding unit 42 convert the data input from the latch unit 76 into a negative video signal.

The multiplexer 84 selectively outputs the video signals from the P decoding unit 80 and the N decoding unit 82 in response to the polarity control signal POL from the signal control unit 90. The output buffer unit 86 buffers the video signals from the multiplexer 84 and supplies them to the data lines DL2i + 1 to DL3i.

Referring to the operation of the data IC 66 as described above, first, the timing controller 68 supplies the first selection signal, the control signal, and the second data data2 to the signal controller 90. Here, the first selection signal is also supplied to the switching unit 92. The signal controller 90 receiving the control signal outputs various control signals (SSP, SSC, SOE, POL, etc.) to the corresponding components. The signal controller 90 supplies the second data data2 to the i / 2 + 1 th latch to the i th latch included in the latch unit 76 in response to the first selection signal.

On the other hand, the switching unit 92 receives the i / 2 sampling signals supplied from the shift register unit 74 in response to the first selection signal from the i / 2 + 1th latch to the ith latch included in the latch unit 76. To supply. In this case, the second data data2 is stored in the i / 2 + 1 th latch to the i th latch included in the latch unit 76.

Thereafter, the timing controller 68 supplies the second selection signal and the first data data1 to the signal controller 90. Here, the second selection signal is also supplied to the switching unit 92. The signal controller 90 receiving the first data data1 supplies the first data data1 to the first latches to i / 2 latches included in the latch unit 76 in response to the second selection signal.                     

On the other hand, the switching unit 92 supplies i / 2 sampling signals supplied from the shift register unit 74 to the first latches to i / 2 latches included in the latch unit 76 in response to the second selection signal. . In this case, the second data data1 are stored in the first latch to i / 2 latch included in the latch unit 76.

Thereafter, the data data1 and data2 stored in the latch unit 76 are supplied to the DAC 78 in response to the source output enable (SOE) signal. The DAC 78 converts the data data1 and data2 supplied to the multiplexer 84 into a positive and negative video signal. The multiplexer 84 selectively outputs the positive and negative video signals in response to the polarity control signal POL, and the video signals are temporarily stored in the output buffer unit 86 and then the data lines DL2i + 1 to DL3i. ).

Thus, in the present invention, since one data IC 66 is shared between the left portion 54 and the right portion 56, that is, the data line of the left portion 54 and the right portion 56 in one data IC 66 is used. Since data can be supplied to each of the plurality of terminals DL, left / right division driving can be performed in an LCD including an odd data integrated circuit. In other words, even in the SVGA-class liquid crystal panel using seven 384 channel-class data ICs, left / right split driving can be performed, thereby reducing power consumption, EMI, and transmission speed.

FIG. 7 shows a second embodiment of the data IC 66 located at the boundary between the left portion 54 and the right portion 56. FIG.

Referring to FIG. 7, the data IC 66 positioned at the boundary between the left portion 54 and the right portion 56 includes the first and second shift register portions 104 and 105 which sequentially supply the sampling signal, and the sampling signal. A latch section 106 for latching and simultaneously outputting data data1 and data2, a DAC section 108 for converting data data1 and data2 from the latch section 106 into an analog video signal, and a DAC section. And an output buffer unit 116 for buffering and outputting the video signal from 108.

In addition, the data IC 66 includes a signal controller 120 for relaying control signals supplied from the timing controller 68 and data (data 1, data 2), and the positive and negative polarities required by the DAC unit 108. A gamma voltage unit 118 for supplying gamma voltages is provided. The data IC 66 having such a configuration drives i (i is a natural number, for example, i is 348, 480) channels, i.e., i data lines DL2i + 1 to 3i.

The signal controller 120 outputs various control signals (SSP, SSC, SOE, POL, etc.) and data (data1, data2) from the timing controller 68 to the corresponding components. In addition, the signal controller 120 controls the output paths of the source start pulse SSP, the source sampling clock SSC, and the data data1 and data2 in response to the selection signal supplied thereto. For example, when the first selection signal is input, the signal controller 120 supplies data data2 input thereto to the i / 2 + 1th latches to the ith latches included in the latch unit 106. In this case, the signal controller 120 supplies the source start pulse SSP and the source sampling clock SSC to the second shift register 105. When the second selection signal is input, the signal controller 120 supplies data data1 input to the first latch to the i / 2 latches included in the latch unit 106. At this time, the signal controller 120 supplies the source start pulse SSP and the source sampling clock SSC to the first shift register 104.

The gamma voltage unit 118 divides and outputs a plurality of gamma reference voltages inputted from a gamma reference voltage generator (not shown) for each gray.

The first shift register 104 includes a plurality of shift registers to sequentially shift the source start pulse SSP supplied from the signal controller 120 in correspondence to the source sampling clock SSC to output a sampling signal. Here, the sampling signal output from the first shift register section 104 is supplied to the first latches to i / 2 latches included in the latch section 106. The second shift register 104 includes a plurality of shift registers to sequentially shift the source start pulse SSP supplied from the signal controller 120 in correspondence with the source sampling clock SSC to output a sampling signal. Here, the sampling signal output from the second shift register section 104 is supplied to the i / 2 + 1 th latch to the i th latch included in the latch section 106.

The latch unit 106 sequentially samples the data data1 and data2 supplied from the signal control unit 120 in response to a sampling signal supplied from the first shift register 104 or the second shift register 105. Latch To this end, the latch unit 106 is composed of i latches for latching i data (data1, data2), each of the latches corresponding to the number of bits (for example, 3 bits or 6 bits) of the data Has a size. The latch unit 106 simultaneously outputs the n data latched in response to the source output enable (SOE) signal from the signal controller 120.

The DAC unit 108 converts the data data1 and data2 from the latch unit 106 into positive and negative video signals at the same time and outputs the same. To this end, the DAC unit 108 selects the P decoding unit 110 and the N decoding unit 112 and the output signals of the P decoding unit 110 and the N decoding unit 112 commonly connected to the latch unit 106. A multiplexer (MUX) 114 is provided.

The i P decoders included in the P decoding unit 110 convert the data input from the latch unit 106 into a positive video signal. The i N decoders included in the N decoding unit 112 convert the data input from the latch unit 106 into a negative video signal.

The multiplexer 114 selectively outputs video signals from the P decoding unit 110 and the N decoding unit 112 in response to the polarity control signal POL from the signal controller 120. The output buffer unit 116 buffers the video signals from the multiplexer 114 and supplies them to the data lines DL2i + 1 to DL3i.

Referring to the operation of the data IC 66 as described above, first, the timing controller 68 supplies the first selection signal, the control signal and the second data data2 to the signal controller 120. The signal controller 120 receiving the control signal outputs various control signals (SSP, SSC, SOE, POL, etc.) to the corresponding components. In addition, the signal controller 120 receiving the first selection signal supplies the second data data2 to the i / 2 + 1 th latch to the i th latch included in the latch unit 106 and the source start pulse SSP. ) And the source sampling clock SSC are supplied to the second shift register 105. At this time, the second shift register section 105 supplies the sampling signal to the i / 2 + 1 th latch to the i th latch included in the latch section 106, and thus i / 2 included in the latch section 106. Second data data2 is stored in the +1 th latch to the i th latch.                     

Thereafter, the timing controller 68 supplies the second selection signal and the first data data1 to the signal controller 120. The signal controller 120 receiving the second selection signal supplies the first data data1 to the first latch to i / 2 latch included in the latch unit 106, and also the source start pulse SSP and the source sampling clock. The SSC is supplied to the first shift register section 104. At this time, the first shift register unit 104 supplies the sampling signal to the first latch to the i / 2th latch included in the latch unit 106, and accordingly, the first latch to i included in the latch unit 106 is provided. The first data data1 is stored in the / 2th latch.

The data data1 and data2 stored in the latch unit 106 are supplied to the DAC 108 in response to a source output enable (SOE) signal. The DAC 108 converts the data data1 and data2 supplied to the multiplexer 114 into a positive and negative video signal. The multiplexer 114 selectively outputs the positive and negative video signals in response to the polarity control signal POL, and the video signals are temporarily stored in the output buffer unit 116 and then the data lines DL2i + 1 to DL3i. ).

Thus, in the present invention, since one data IC 66 is shared between the left portion 54 and the right portion 56, that is, the data line of the left portion 54 and the right portion 56 in one data IC 66 is used. Since data can be supplied to each of the plurality of terminals DL, left / right division driving can be performed in an LCD including an odd data integrated circuit. In other words, even in the SVGA-class liquid crystal panel using seven 384 channel-class data ICs, left / right split driving can be performed, thereby reducing power consumption, EMI, and transmission speed.

As described above, according to the driving apparatus of the liquid crystal display device according to the present invention, since one data IC is shared by the left and right parts of the liquid crystal panel, the left and right sides of the liquid crystal display device including an odd data integrated circuit are also driven. It is possible to drive. That is, in the present invention, regardless of the number of data integrated circuits, all of the liquid crystal panels may be driven by being divided into left and right parts, thereby achieving effects such as power consumption reduction, EMI reduction, and transmission speed improvement.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (12)

A liquid crystal panel driven by being divided into a left part and a right part; At least one first data integrated circuit for driving data lines formed in the left portion; At least one second data integrated circuit for driving data lines formed in the right part; Third data integrated circuits positioned at boundary portions of the left and right portions to drive data lines formed on the left side and data lines formed on the right side; And A timing controller for generating control signals using synchronization signals supplied from the outside, dividing data supplied from the outside into the left portion data and the right portion data, and supplying the data to the data integrated circuits; The timing controller supplies a first selection signal to the third data integrated circuit when the right side data is supplied to the third data integrated circuit, and the third data when the left data is supplied to the third data integrated circuit. And a second selection signal supplied to the integrated circuit. delete delete delete The method of claim 1, The timing controller includes a first memory in which the left side data is stored, and a second memory in which the right side data is stored. The method of claim 1, The third data integrated circuit A signal controller for relaying the control signal and outputting any one of the left side data and the right side data in response to any one of the first selection signal and the second selection signal; A shift register unit for receiving a source start pulse and a source sampling clock among the control signals, and outputting i / 2 (i is a natural number) sampling signals while shifting the source start pulse corresponding to the source sampling clock; A latch unit for storing the i / 2 left side data and i / 2 right side data supplied to the corresponding one of the sampling signals supplied from the shift register unit; And a switching unit disposed between the shift register unit and the latch unit and controlling a path of the sampling signal in correspondence to the first selection signal and the second selection signal. The method of claim 6, When the first selection signal is supplied, the signal controller supplies the right side data to the first to i / 2th latches included in the latch unit, and the switching unit to the first to i / 2 latches included in the latch unit. And the sampling signal is supplied to the second latch. The method of claim 6, When the second selection signal is supplied, the signal controller supplies the left part data to the i / 2 + 1 th latch to the i th latch included in the latch part, and the switching part includes i / 2 + included in the latch part. And the sampling signal is supplied to the first to ith latches. The method of claim 1, The third data integrated circuit A signal controller for relaying the control signal and outputting any one of the left side data and the right side data in response to any one of the first selection signal and the second selection signal; A first shift register section for supplying i / 2 sampling signals (i is a natural number) to first latches to i / 2th latches when a source start pulse and a source sampling clock are input from the signal controller; A second shift register section for supplying i / 2 sampling signals (i is a natural number) to the i / 2 + 1 th latch to the i th latch when a source start pulse and a source sampling clock are input from the signal controller; And a latch unit for storing the i / 2 left side data and i / 2 right side data supplied to the first and second shift registers corresponding to the sampling signals supplied from the first and second shift register units. Drive of the device. The method of claim 9, When the first selection signal is supplied, the signal controller supplies the right side data to the i / 2 + 1 th latch to the i th latch included in the latch unit, and supplies the source start pulse and the source sampling clock to the second latch. A drive device for a liquid crystal display device, which is supplied to a shift register section. The method of claim 9, When the second selection signal is supplied, the signal controller supplies the right side data to the first to i / 2th latches included in the latch unit, and the source start pulse and the source sampling clock to the first shift register unit. A drive device for a liquid crystal display device, characterized in that the supply. The method according to claim 6 or 9 The third data integrated circuit A digital-to-analog converter for receiving data stored in the latch unit and converting the data into a positive video signal and a negative video signal; And an output buffer for supplying the data converted by the digital-analog converter to i data lines connected thereto.

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