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KR100943485B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR100943485B1
KR100943485B1 KR1020020088278A KR20020088278A KR100943485B1 KR 100943485 B1 KR100943485 B1 KR 100943485B1 KR 1020020088278 A KR1020020088278 A KR 1020020088278A KR 20020088278 A KR20020088278 A KR 20020088278A KR 100943485 B1 KR100943485 B1 KR 100943485B1
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forming
trench
metal wiring
metal
insulating film
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KR20040061969A (en
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유승종
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 제조방법을 개시한다. 개시된 발명은, 반도체기판 상에 제1절연막을 형성한후 상기 제1절연막의 소정영역내에 제1트렌치를 형성하는 단계; 상기 제1트렌치내에 제1금속배선을 형성한후 전체 구조의 상면에 제2절연막을 형성한후 이를 선택적으로 제거하여 상기 제1금속배선 상면을 노출시키는 제2 트렌치를 형성하는 단계; 상기 제2트렌치내에 제2금속배선을 형성한후 상기 제2 절연막내에 적어도 상기 제2금속배선의 일부와 오버랩되는 제3트렌치를 형성하는 단계; 상기 제3트렌치내에 하부전극과 유전체막 및 상부전극 및 제3금속배선을 형성하는 단계; 상기 제3금속배선을 포함한 전체 구조의 상면에 제3절연막을 형성 한후 상기 제2금속배선과 제3금속배선을 노출시키는 제4트렌치를 형성하는 단계; 및 상기 제4트렌치내에 제4금속배선을 형성하는 단계를 포함하여 구성된다.
The present invention discloses a method for manufacturing a semiconductor device. The disclosed invention includes forming a first trench in a predetermined region of the first insulating film after forming the first insulating film on the semiconductor substrate; Forming a second trench for exposing the upper surface of the first metal interconnection by forming a second insulating layer on the upper surface of the entire structure after forming the first metal interconnection in the first trench; Forming a third trench in the second trench and overlapping at least a portion of the second metal interconnect in the second insulating layer; Forming a lower electrode, a dielectric film, an upper electrode, and a third metal wiring in the third trench; Forming a fourth trench for exposing the second metal wiring and the third metal wiring after forming a third insulating film on the upper surface of the entire structure including the third metal wiring; And forming a fourth metal wiring in the fourth trench.

Description

반도체소자의 제조방법{Method for fabricating semiconductor device} Method for fabricating semiconductor device

도 1 내지 도 6은 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도.1 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

[도면부호의설명][Description of Drawing Reference]

10 : 반도체기판 12 : 제1절연막10 semiconductor substrate 12 first insulating film

14 : 제1트렌치 16 : 제1금속배선14 first trench 16 first metal wiring

18 : 제2절연막 20 : 제2트렌치18: second insulating film 20: second trench

22a, 22b : 제2금속배선 24 : 감광막패턴 22a, 22b: second metal wiring 24: photoresist pattern

26 : 제3트렌치 28 : 하부전극 물질층26: third trench 28: lower electrode material layer

30 : 유전체 물질층 32 : 상부전극 물질층30 dielectric layer 32 upper electrode material layer

28a : 하부전극 30a : 유전체막28a: lower electrode 30a: dielectric film

32a : 상부전극 34a : 제3금속배선32a: upper electrode 34a: third metal wiring

36 : 제3절연막 38 : 제4트렌치36: third insulating film 38: fourth trench

40a, 40b : 제4금속배선40a, 40b: fourth metal wiring

본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 금속배선과 금속배선사이의 스페이서를 활용하므로써 MIM 캐패시터를 위해 별도로 층을 형성할 필요없고 MIM 캐패시터의 하부전극과 금속배선의 측벽을 연결시킬 수 있는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, by using a spacer between a metal wiring and a metal wiring, there is no need to separately form a layer for the MIM capacitor, and connects the lower electrode of the MIM capacitor to the sidewall of the metal wiring. It relates to a method for manufacturing a semiconductor device that can be made.

종래기술에 따른 MIM 캐패시터 구조의 반도체소자의 제조방법에 대해 설명하면, 금속배선층과 금속배선층사이에 캐패시터용 하부전극, 유전체막, 상부전극을 형성하여야 하며, 또한 하부전극과 상부전극에 전류를 가하기 위한 추가적인 콘택홀 공정을 진행하여야 한다.Referring to the manufacturing method of the semiconductor device of the MIM capacitor structure according to the prior art, the lower electrode, the dielectric film, the upper electrode for the capacitor should be formed between the metal wiring layer and the metal wiring layer, and to apply a current to the lower electrode and the upper electrode Additional contact hole process should be performed.

또한, 하부전극과 상부전극은 각각 다른 콘택홀로 연결시켜야 하므로 마스크작업 역시 하부전극과 상부전극을 분리하여 고려해야만 한다.In addition, since the lower electrode and the upper electrode must be connected to different contact holes, the masking work must also be considered by separating the lower electrode and the upper electrode.

상기 종래기술에 의하면, 일련의 추가적인 작업뿐만 아니라 캐패시터를 형성하기 위한 추가적인 층을 형성하므로써 전체 토폴러지의 증가로 후속 공정에서의 콘택홀 형성에 상당한 어려움이 있다.According to the above prior art, there is a considerable difficulty in forming a contact hole in a subsequent process by increasing the overall topology by forming an additional layer for forming a capacitor as well as a series of additional operations.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 금속배선과 금속배선사이의 스페이서를 활용하므로써 MIM 캐패시터를 위해 별도로 층을 형성할 필요가 없고 MIM 캐패시터의 하부전극과 금속배선의 측벽을 용이하게 연결할 수 있는 반도체소자의 제조방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above problems of the prior art, by using a spacer between the metal wiring and the metal wiring, there is no need to form a separate layer for the MIM capacitor, and the bottom electrode and the metal wiring of the MIM capacitor It is an object of the present invention to provide a method for manufacturing a semiconductor device that can easily connect sidewalls.

상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조법은, 반도체 기판상에 제1절연막을 형성한후 상기 제1절연막의 소정영역내에 제1트렌치를 형성하는 단계;According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first trench in a predetermined region of a first insulating film after forming a first insulating film on a semiconductor substrate;

상기 제1트렌치내에 제1금속배선을 형성한후 전체 구조의 상면에 제2절연막을 형성한후 이를 선택적으로 제거하여 상기 제1금속배선 상면을 노출시키는 제2트렌치를 형성하는 단계; Forming a second trench for exposing the upper surface of the first metal interconnection by forming a first insulating layer on the first trench and then removing a second insulating layer on the upper surface of the entire structure;

상기 제2트렌치내에 제2금속배선을 형성한후 상기 제2절연막내에 적어도 상기 제2금속배선의 일부와 오버랩되는 제3트렌치를 형성하는 단계;Forming a third trench in the second trench and overlapping at least a portion of the second metal interconnect in the second insulating layer;

상기 제3트렌치내에 하부전극과 유전체막 및 상부전극 및 제3금속배선을 형성하는 단계;Forming a lower electrode, a dielectric film, an upper electrode, and a third metal wiring in the third trench;

상기 제3금속배선을 포함한 전체 구조의 상면에 제3절연막을 형성한후 상기 제2금속배선과 제3금속배선을 노출시키는 제4트렌치를 형성하는 단계; 및Forming a fourth trench for exposing the second metal wiring and the third metal wiring after forming a third insulating film on the upper surface of the entire structure including the third metal wiring; And

상기 제4트렌치내에 제4금속배선을 형성하는 단계를 포함하여 구성되는 것을 특징으로한다.And forming a fourth metal wiring in the fourth trench.

(실시예)(Example)

이하, 본 발명에 따른 반도체소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 6은 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도이다.1 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

본 발명에 따른 반도체소자의 제조방법은, 도 1에 도시된 바와같이, 먼저 소자의 공정으로 반도체소자를 형성하기 위한 여러 요소가 형성된 반도체기판(10) 상 에 제1절연막(12)을 형성한후 식각공정으로 상기 제1절연막(12)의 소정영역을 식각하여 제1트렌치(14)를 형성한다. 이때, 상기 제1절연막은 SiO2, FSG 또는 유전율이 3.0 이하인 저유전율의 절연막을 이용한다.In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 1, first, a first insulating film 12 is formed on a semiconductor substrate 10 on which various elements for forming a semiconductor device are formed by a device process. After the etching process, a predetermined region of the first insulating layer 12 is etched to form a first trench 14. In this case, the first insulating layer may be SiO 2 , FSG, or an insulating layer having a low dielectric constant of 3.0 or less.

이어, 금속물질을 상기 식각된 소정영역 즉, 트렌치(14)내에 금속물질을 매립하여 제1금속배선(16)을 형성한다. 이때, 상기 제1 금속배선은 구리를 사용하며, 무전해 또는 전기도금법으로 듀얼 다마신 패턴을 매립하여 형성한다.Subsequently, the metal material is embedded in the etched predetermined region, that is, the trench 14, to form the first metal wiring 16. In this case, the first metal wiring is copper, and is formed by burying a dual damascene pattern by electroless or electroplating.

그다음, 상기 제1금속배선(16)을 포함한 전체 구조의 상면에 제2절연막(18)을 형성한후 듀얼다마신패턴(미도시)을 이용하여 패드지역의 제1금속배선(16) 부분을 개구시키는 제2트렌치(20)을 형성한다. 이때, 상기 제2절연막은 SiO2, TEOS, SiN과 같은 절연막을 사용한다. Next, after forming the second insulating film 18 on the upper surface of the entire structure including the first metal wiring 16, a portion of the first metal wiring 16 of the pad region is formed by using a dual damascene pattern (not shown). The second trench 20 to be opened is formed. At this time, the second insulating film is an insulating film such as SiO 2 , TEOS, SiN.

이어서, 도 2에 도시된 바와같이, 상기 제2트렌치(20)를 포함한 제2절연막(18) 상에 제2트렌치(20)내에 제2금속배선(22a)(22b)을 형성한후 전체 구조의 상면에 감광물질을 도포한후 이를 선택적으로 제거하여 MIM 캐패시터 트렌치 형성용 감광막패턴(24)을 형성한다. 이때, 제2 금속배선은 구리를 사용하며, 무전해 또는 전기도금법으로 매립하여 형성한다. 또한, 감광막패턴의 개구되는 부위에는 하부 금속배선과 오버랩되거나 금속배선의 일부를 포함한다. 또한, 개구되는 부위는 여러 금속배선들 사이의 스페이스일 수도 있고 넓은 스페이스를 가지는 두 금속배선 사이 또는 한 금속배선과 옆의 공간일 수도 있다. 이때, 상기 금속배선과 오버랩되도록 MIM 캐패시터 트렌치 형성용 감광막패턴이 형성되어야 한다. Subsequently, as shown in FIG. 2, after the second metal wirings 22a and 22b are formed in the second trenches 20 on the second insulating layer 18 including the second trenches 20, the entire structure. After the photosensitive material is applied to the upper surface of the film, the photosensitive material is selectively removed to form the photosensitive film pattern 24 for forming the MIM capacitor trench. In this case, the second metal wiring is made of copper, and is formed by being embedded by electroless or electroplating. In addition, the opening portion of the photoresist pattern may overlap the lower metal wiring or include a part of the metal wiring. In addition, the opening portion may be a space between several metal wires, or may be a space between two metal wires having a wide space or one metal wire and a side space. At this time, the photoresist pattern for forming the MIM capacitor trench should be formed so as to overlap the metal wiring.                     

그다음, 도 3에 도시된 바와같이, 상기 MIM 캐패시터 트렌치 형성용 감광막패턴(24)을 마스크로 후속공정에서 MIM 캐패시터가 형성될 영역이 개방되도록 제2절연막이 드러나지 않을 정도의 소정의 식각공정을 실시하여 제3트렌치(26)를 형성한후 감광막패턴(24)을 제거한다. 이때, 식각공정으로 제2금속배선 일부의 측벽이 개방되어 후속 MIM 캐패시터 하부전극과 연결된다.Next, as shown in FIG. 3, a predetermined etching process is performed such that the second insulating layer is not exposed so that the region where the MIM capacitor is to be formed is opened in a subsequent process using the photosensitive film pattern 24 for forming the MIM capacitor trench. After the third trench 26 is formed, the photoresist pattern 24 is removed. At this time, a sidewall of a part of the second metal wiring is opened by an etching process and connected to a subsequent MIM capacitor lower electrode.

이어서, 도 4에 도시된 바와같이, 상기 제3트렌치(26)을 포함한 제2금속 배선(22a)(22b) 및 제2절연막(18)상에 캐패시터를 이루는 하부전극물질층(28), 유전체물질층(30) 및 상부전극 물질층(32) 및 MIM 캐패시터의 금속배선인 제3금속 배선용 금속층(34)을 차례로 증착한다. 이때, 상기 하부전극 또는 상부전극 물질층 으로는 TiN, Pt, 혹은 W을 사용하며, 상기 유전체 물질층으로는 Ta 산화막, Ba-Sr-Ti 산화물, Zr산화물, Pb-Zn-Ti 산화물 또는 Sr-Bi-Ta 산화물을 사용한다.Subsequently, as shown in FIG. 4, the lower electrode material layer 28 forming a capacitor on the second metal wirings 22a and 22b and the second insulating layer 18 including the third trench 26 and the dielectric material. The material layer 30, the upper electrode material layer 32, and the third metal wiring metal layer 34, which is a metal wiring of the MIM capacitor, are sequentially deposited. In this case, TiN, Pt, or W is used as the lower electrode or upper electrode material layer, and Ta oxide film, Ba-Sr-Ti oxide, Zr oxide, Pb-Zn-Ti oxide, or Sr- is used as the dielectric material layer. Bi-Ta oxide is used.

그다음, 도 5에 도시된 바와같이, 화학적 기계적 연마(chemical mechanical polishing; CMP)에 의해 상기 제2금속배선(22a)(22b)의 높이이상에 있는 부분들을 모두 제거하여 MIM 캐패시터 및 제3금속배선(34a)을 형성한다. 이때, 상기 MIM 캐패시터는 하부전극 물질층(28a), 유전체막(30a) 및 상부전극(32a)을 포함한다. 또한, 상기 제3 금속배선은 구리를 사용하며 , 무전해 또는 전기도금법으로 매립하여 형성한다. Next, as shown in FIG. 5, all parts above the height of the second metal wirings 22a and 22b are removed by chemical mechanical polishing (CMP) to remove the MIM capacitor and the third metal wiring. 34a is formed. In this case, the MIM capacitor includes a lower electrode material layer 28a, a dielectric film 30a, and an upper electrode 32a. In addition, the third metal wiring is copper, and is formed by being buried by an electroless or electroplating method.

이어서, 도 6에 도시된 바와같이, 제3금속배선(34a)과 MIM 캐패시터를 포함한 전체 구조의 상면에 제3절연막(36)을 형성한후 듀얼다마신패턴(미도시)을 사용하여 상기 제3절연막(36)내에 상기 제2금속배선(22a)과 제3금속배선(34a)을 노출 시키는 제4트렌치(38)를 형성하고 이어 상기 제4트렌치(38)내에 제4금속배선 (40a)(40b)을 형성한다. 이때, 상기 제4 금속배선은 구리를 사용하며 , 무전해 또는 전기도금법으로 매립하여 형성한다. 또한, 상기 제3절연막은 SiO2, FSG 또는 유전율이 3.0 이하인 저유전율의 절연막을 이용한다.Subsequently, as shown in FIG. 6, after forming the third insulating layer 36 on the upper surface of the entire structure including the third metal wiring 34a and the MIM capacitor, the second damascene pattern (not shown) is used. A fourth trench 38 is formed in the third insulating layer 36 to expose the second metal wiring 22a and the third metal wiring 34a. Then, the fourth metal wiring 40a is formed in the fourth trench 38. 40b is formed. In this case, the fourth metal wiring is copper, and is formed by embedding by electroless plating or electroplating. In addition, the third insulating film may be formed of SiO 2 , FSG, or an insulating film having a low dielectric constant of 3.0 or less.

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 제조방법에 의하면, 금속배선과 금속배선사이의 스페이서를 활용하므로써 MIM 캐패시터를 위해 별도로 층을 형성할 필요가 없고 MIM 캐패시터의 하부전극과 금속배선의 측벽을 용이하게 연결할 수 있다.As described above, according to the method of manufacturing a semiconductor device according to the present invention, there is no need to separately form a layer for the MIM capacitor by utilizing the spacer between the metal wiring and the metal wiring, and the bottom electrode and the metal wiring of the MIM capacitor Side walls can be easily connected.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (7)

반도체기판상에 제1절연막을 형성한후 상기 제1절연막의 소정영역내에 제1트렌치를 형성하는 단계;Forming a first trench in a predetermined region of the first insulating film after forming the first insulating film on the semiconductor substrate; 상기 제1트렌치내에 제1금속배선을 형성한후 전체 구조의 상면에 제2절연막을 형성한후 이를 선택적으로 제거하여 상기 제1금속배선 상면을 노출시키는 제2트렌치를 형성하는 단계; Forming a second trench for exposing the upper surface of the first metal interconnection by forming a first insulating layer on the first trench and then removing a second insulating layer on the upper surface of the entire structure; 상기 제2트렌치내에 제2금속배선을 형성한후 상기 제2절연막내에 적어도 상기 제2금속배선의 일부와 오버랩되는 제3트렌치를 형성하는 단계;Forming a third trench in the second trench and overlapping at least a portion of the second metal interconnect in the second insulating layer; 상기 제3트렌치내에 하부전극과 유전체막 및 상부전극 및 제3금속배선을 형성하는 단계;Forming a lower electrode, a dielectric film, an upper electrode, and a third metal wiring in the third trench; 상기 제3금속배선을 포함한 전체 구조의 상면에 제3절연막을 형성한후 상기 제2금속배선과 제3금속배선을 노출시키는 제4트렌치를 형성하는 단계; 및Forming a fourth trench for exposing the second metal wiring and the third metal wiring after forming a third insulating film on the upper surface of the entire structure including the third metal wiring; And 상기 제4트렌치내에 제4금속배선을 형성하는 단계를 포함하며,Forming a fourth metal wiring in the fourth trench, 상기 제3트렌치는 상기 제2금속배선과 오버랩되거나 상기 제2금속배선일부를 포함하는 것을 특징으로하는 반도체소자의 제조방법.And the third trench overlaps the second metal wiring or includes a portion of the second metal wiring. 제1항에 있어서, 상기 제1, 2, 3, 4 금속배선은 구리를 사용하며, 무전해 또는 전기도금법으로 매립하여 형성하는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 1, wherein the first, second, third, and fourth metal wires are formed of copper and are embedded by electroless plating or electroplating. 제1항에 있어서, 상기 제1, 2, 3 절연막은 SiO2, FSG 또는 유전율이 3.0 이하인 저유전율의 절연막을 이용하는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 1, wherein the first, second, and third insulating films are formed of SiO 2 , FSG, or an insulating film having a low dielectric constant of 3.0 or less. 제1항에 있어서, 상기 하부전극 또는 상부전극은 TiN, Pt, 혹은 W을 증착하여 형성하는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 1, wherein the lower electrode or the upper electrode is formed by depositing TiN, Pt, or W. 6. 제1항에 있어서, 상기 유전체막은 Ta 산화막, Ba-Sr-Ti 산화물, Zr산화물, Pb-Zn-Ti 산화물 또는 Sr-Bi-Ta 산화물을 증착하여 사용하는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 1, wherein the dielectric layer is formed by depositing a Ta oxide layer, Ba—Sr—Ti oxide, Zr oxide, Pb—Zn—Ti oxide, or Sr—Bi—Ta oxide. 삭제delete 제1항에 있어서, 상기 하부전극은 상기 제2금속배선과 전기적으로 연결되어 있는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 1, wherein the lower electrode is electrically connected to the second metal wiring.
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KR950024340A (en) * 1994-01-11 1995-08-21 문정환 Capacitor of semiconductor device and manufacturing method thereof
KR19980078493A (en) * 1997-04-29 1998-11-16 윤종용 Thin film capacitors and manufacturing method thereof
KR20000053453A (en) * 1999-01-12 2000-08-25 루센트 테크놀러지스 인크 Integrated circuit device having dual damascene interconnect structure and metal electrode capacitor and associated method for making
KR20030053550A (en) * 2001-12-22 2003-07-02 주식회사 하이닉스반도체 method for fabricating capacitor in semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950024340A (en) * 1994-01-11 1995-08-21 문정환 Capacitor of semiconductor device and manufacturing method thereof
KR19980078493A (en) * 1997-04-29 1998-11-16 윤종용 Thin film capacitors and manufacturing method thereof
KR20000053453A (en) * 1999-01-12 2000-08-25 루센트 테크놀러지스 인크 Integrated circuit device having dual damascene interconnect structure and metal electrode capacitor and associated method for making
KR20030053550A (en) * 2001-12-22 2003-07-02 주식회사 하이닉스반도체 method for fabricating capacitor in semiconductor device

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