KR100926054B1 - Active harmonic filter with fast reset integrator - Google Patents

Abstract

In the present invention, the non-inverting terminal of the OP amplifier is grounded, a resistor R1 is connected between the input terminal and the inverting terminal, and an active harmonic filter including an integrator connected to the capacitor C1 between the inverting terminal and the output terminal, the inverting terminal and the output terminal The resistor R2 and the JFET are further connected in parallel with the capacitor C1, and the capacitor C1 is discharged by applying a pulse between the gate and the source of the JFET, so that the fast reset and the offset error correction are provided. It relates to an active harmonic filter.

Description

ACTIVE HARMONICS FILTER HAVING HIGH-SPEED RESET INTERGRATOR}

The present invention relates to an active harmonic filter, and more particularly, to an active harmonic filter having a fast reset (initialization) integrator (integrating circuit) to enable fast switching and offset error correction through a semiconductor switch.

Inverters, converters, rectifiers, and power devices that have non-linear load characteristics are connected to AC power, and harmonic currents including fundamental waves are generated. These harmonic currents are electrical / electronic devices such as medical devices, elevators, and PCs connected to the surroundings. It affects and causes malfunction.

Accordingly, many harmonic filters have been developed for removing harmonic currents. Harmonic filters developed so far are largely classified into passive filters consisting of passive elements such as resistors, inductors and capacitors, and active filters composed of active elements such as transistors.

Passive filter has the advantage that it is simple to implement for the purpose of removing a specific harmonic, but there is a problem that can not adapt to the variation of the load, the active filter has been used a lot recently.

The active filter detects the load current and removes the harmonic current, which removes the fundamental wave current, back into the power supply to remove it (that is, the current generated from the load is generated as a current having a reverse phase and inputted to the power supply to cancel both currents). Harmonics), which has the advantage of removing any harmonics at the same time.

One example of an active filter is illustrated in FIG. 1. In Fig. 1, reference numeral 1 denotes an AC power source, 2 a load generating a harmonic current, 3 a current detector for detecting a current of the load 2, 4 an inverter, 5 a reactor, 6 a capacitor, 7 an inverter 4 AC current detector for detecting the AC current of the current, 12 is a voltage detector for detecting the voltage of the AC power supply 1, 13 is a phase signal (θ) connected to the output side of the voltage detector 12 in synchronization with the AC power supply (1) ) / PLL circuit for generating reset signal (Q _R ) / hold signal ([theta] _H ), 14A and 14B are ROMs for converting the phase signal? Circuits 15A and 15B are first multipliers 16A multiplying the output signals sinθ and cosθ of the ROM circuits 14A and 14B by the detection signal i _L of the load current I _L of the load 2. And 16B are integrators integrating the output signals of the first multipliers 15A, 15B until a reset signal Q _R is generated, which is one of the outputs of the PLL circuit, and 17A and 17B are the integrators 16A, 16B. Print Sample heuldeu for holding a call whenever one of the hold signal (θ _H) of the PLL circuit circuit, 18A and 18B is a sample-and-hold circuit (17A, 17B) output the fundamental wave component (a1, b1) and the A second multiplier for multiplying the output signals sin θ and cos θ of the ROM circuits 14A and 14B, 19 is a second multiplier that adds the output signals ip and iq of the second multiplier to obtain a basic current signal iL1. 3 is an adder (see Korean Patent Publication No. 1992-0007408).

In FIG. 1, the detection signal i _L of the load current I _L can be developed as a Fourier series as in Equation 1.

[Equation 1]

Here, it is well known that b _o represents a direct current component, an and bn represent peak values of the nth harmonic component, and a1 and b1, which are fundamental wave components, can be obtained from the following equations (2) and (3), respectively.

[Equation 2]

[Equation 3]

The calculation of the fundamental wave components a1 and b1 is performed in the integrators 16A and 16B in FIG. 1, which is a reset signal Q _R output from the PLL circuit 13 every one cycle of the AC power source 1. Is integrated until is given, and the output of integrators 16A and 16B should be zero if reset signal Q _R is applied near phases 0 and 2π.

Therefore, designing an active harmonic filter using an analog device has been one of the major technical challenges in designing an accurate integrator (integral circuit) that can be quickly reset and has a very small error.

Integral circuits can be implemented by supplying a constant current to the capacitor, and adding a reset function requires a circuit that quickly discharges the capacitor. In particular, the conventional integrating circuit configured using the OP amplifier has been required for a high-speed floating switch for fast discharge due to the structure in which a constant current capacitor is floating.

On the other hand, although the high-speed switch is made of a semiconductor, in order to implement a floating switch with a semiconductor switch, a complicated control circuit is required, and there is a limit in improving the switching speed. Applying voltage to the existing reset integrator caused an offset error, and it was very difficult to correct the offset and maintain the linearity of the integrator.

Due to the problems of the analog method as described above, the harmonic filter of the digital method is mainly used.

Digital harmonic filters have better performance than analog methods, but they need to be converted to digital signals to process them.

The present invention provides an analog active harmonic filter with a fast reset integrator to enable high-speed switching and offset error correction through a semiconductor switch to solve the problems of the conventional analog harmonic filter while providing a performance comparable to that of a digital method. For that purpose.

In order to achieve the above object, in the active harmonic filter having the fast reset integrator according to the present invention, the non-inverting terminal of the OP amplifier is grounded, a resistor R1 is connected between the input terminal and the inverting terminal, and a capacitor is connected between the inverting terminal and the output terminal. In an active harmonic filter including an integrator connected to C1, a resistor R2 and a JFET are further connected in parallel with the capacitor C1 between the inverting terminal and the output terminal, and a pulse is applied between the gate and the source of the JFET to connect the capacitor C1. It is characterized by resetting by discharging.

In addition, an inverting amplifier is further connected to an input terminal of the integrator, and an adder having the input terminal voltage and the output terminal voltage as an input signal is further connected between the input terminal and the output terminal of the integrator.

In addition, the inverting amplifier changes only the polarity of the input voltage, and the adder is configured to add the input terminal voltage of the integrator and the output terminal voltage of the integrator by simply changing the polarity.

In addition, it is another feature of the present invention that the period Ts of the pulse applied between the gate and the source of the JFET is equal to twice the product of the resistor R1 and the capacitor C1.

The JFET has a P-channel, and the driving circuit for applying a pulse between the gate and the source of the JFET uses FAN7382.

According to the configuration of the present invention, there is an effect capable of fast reset (initialization) and offset error correction through fast discharge.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

FIG. 2 is a conventional integrator circuit, FIG. 3 is an improved integrator circuit in which a capacitor C1 discharge resistor R2 is connected in parallel with a capacitor C1 in a conventional integrator circuit, and FIG. 4 is a JFET capacitor for implementing a fast reset integrator according to the present invention. Further connected in parallel with C1, Figure 5 is further connected to the inverting amplifier, adder and JFET drive for implementing the fast reset integrator according to the present invention, Figure 6 shows the output waveform by the fast reset integrator according to the present invention FIG. 7 is an exemplary circuit diagram of the JFET driver of FIG. 5.

First, according to the conventional integrator circuit as shown in Fig. 2, the output terminal voltage Vo is as follows.

Vo (t) = (-1 / RC) ∫Vi (t) dt

However, in order to configure the reset integrator, as shown in FIG. 3, when the capacitor C1 discharge resistor R2 is simply connected in parallel with the capacitor C1 in the conventional integrator circuit, it takes a long time to discharge.

Therefore, in this embodiment, as shown in FIG. 4, by further connecting a JFET, which is a semiconductor switching element, to the circuit according to FIG. 3 in parallel with the capacitor C1, to quickly completely discharge the voltage of the capacitor C1 by the switching operation of the JFET. It was.

Here, the switching operation of the JFET is implemented by applying a pulse between the gate and the source of the JFET. In the case of a P-channel JFET, when a positive voltage pulse is applied between the gate and the source, the switching is turned off. When is applied, it is ON.

The driving circuit 22 for driving the P-channel JFET, that is, the pulse between the gate and the source of the JFET, may be implemented using a known FAN7382 device as shown in FIG. 5.

FIG. 5 shows a specific example of the fast reset integrator according to the present embodiment by further connecting the inverting amplifier 10 and the adder 30 to the circuit of FIG. 4.

That is, the inverting amplifier 10 is connected to the input terminal of the integrator circuit 20 according to FIG. 4, and the adder 30 is connected between the input terminal voltage Va and the input terminal and the output terminal of the integrator circuit 20 according to FIG. 4. The output terminal voltage Vb is connected as an input signal.

Here, for the purpose of this embodiment, the inverting amplifier 10 changes only the polarity of the input voltage, and the adder 30 sums the input terminal voltage Va and the output terminal voltage Vb by simply changing the polarity. It is preferred that each is configured to.

This can be implemented by equalizing the resistances constituting the inverting amplifier 10 and the adder 30, respectively, as shown in FIG.

Therefore, as shown in FIG. 5, in the case of configuring the fast reset integrator circuit according to the present embodiment, when the DC voltage is applied to the input voltage Vm, the output voltage Vsaw becomes as shown in FIG.

This is based on the following facts.

Va = -Vm

Vb = [-1 / (R1C1)] ∫ (-Vm) dt = 1 / (R1C1) ∫ (Vm) dt

Vsaw =-(Va + Vb) = Vm-1 / (R1C1) ∫ (Vm) dt

At this time, the integral section of the Vsaw is when the P-channel JFET is turned off during the switching period Ts, and this is when a positive voltage pulse is applied to the JFET.

Therefore, if the duty rate of the pulse applied to the JFET is 50%, it is preferable that the resistor R1 and the capacitor C1 are determined by the following relationship, so that the Vsaw falls to zero so that there is no need to perform offset correction. Do.

R1C1 = Ts / 2

However, even after discharge, a minute voltage remains across the capacitor C1 of the integrator circuit 20 according to FIG. 4, and when offset correction is required, the duty rate of the pulse applied to the JFET is adjusted according to the remaining voltage. You can get an ideal Vsaw waveform such as 6.

One method of adjusting the duty rate of the pulse applied to the JFET may be based on the driving circuit of the JFET exemplarily illustrated in FIG. 7.

7 exemplarily illustrates a driving circuit of the JFET, that is, a driving circuit 22 for applying a pulse between the gate and the source of the JFET.

According to FIG. 7, it can be seen that the duty rate of the input pulse is changed and output as a reset signal.

Lastly, in FIG. 6, the point of time when the Vsaw becomes zero (the point of time of complete reset) has the advantage of being controllable by adjusting the period Ts of the input pulse.

In other words, reducing the period of the pulse (which is the same as the input pulse period of the driving circuit of the JFET) Ts applied between the gate and the source of the JFET has the advantage that the time of full reset in the integrator can be advanced.

Although the preferred embodiment of the present invention has been described above, the technical idea according to the present invention is not limited to the above embodiment, and can be easily variously applied based on the embodiment, and the description thereof will be omitted. .

1 is an exemplary circuit diagram of a conventional active harmonic filter,

2 is a conventional integrator circuit,

3 is an improved integrator circuit in which a resistor R2 for discharging a capacitor C1 is connected in parallel with a capacitor C1 in a conventional integrator circuit,

4 is a further connection of the JFET in parallel with the capacitor C1 to implement a fast reset integrator according to the present invention,

Figure 5 is further connected to the inverting amplifier, the adder and the JFET driver for implementing the fast reset integrator according to the present invention,

Figure 6 shows the output waveform by the fast reset integrator according to the present invention,

FIG. 7 is an exemplary circuit diagram of the JFET driver of FIG. 5.

<Description of the symbols for the main parts of the drawings>

10: inverting amplifier 20: integrator

22: JFET driver 30: adder

Claims (5)

In an active harmonic filter including a non-inverting terminal of the OP amplifier is grounded, a resistor R1 is connected between the input terminal and the inverting terminal, and an integrator connected to the capacitor C1 between the inverting terminal and the output terminal, Resistor R2 and JFET are further connected in parallel with the capacitor C1 between the inverting terminal and the output terminal, And a pulse having a period Ts that is twice the product of the resistor R1 and the capacitor C1 between the gate and the source of the JFET and reset by discharging the capacitor C1. The method of claim 1, An inverting amplifier is further connected to an input terminal of the integrator, And an adder having an input terminal voltage and an output terminal voltage as an input signal between an input terminal and an output terminal of the integrator. The method of claim 2, The inverting amplifier only changes the polarity of the input voltage, And said adder is configured to add the input terminal voltage of said integrator and the output terminal voltage of said integrator by simply changing polarity. delete The method according to any one of claims 1 to 3, The JFET has a P-channel, And a driving circuit for applying a pulse between the gate and the source of the JFET using a FAN7382 active harmonic filter with a fast reset integrator.

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