KR100905922B1 - 패키지용 인쇄회로기판 및 그 제조방법 - Google Patents
패키지용 인쇄회로기판 및 그 제조방법 Download PDFInfo
- Publication number
- KR100905922B1 KR100905922B1 KR1020080013912A KR20080013912A KR100905922B1 KR 100905922 B1 KR100905922 B1 KR 100905922B1 KR 1020080013912 A KR1020080013912 A KR 1020080013912A KR 20080013912 A KR20080013912 A KR 20080013912A KR 100905922 B1 KR100905922 B1 KR 100905922B1
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- South Korea
- Prior art keywords
- solder
- pad
- resist layer
- substrate
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910000679 solder Inorganic materials 0.000 claims abstract description 117
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000007747 plating Methods 0.000 claims abstract description 25
- 238000004381 surface treatment Methods 0.000 claims abstract description 19
- 238000002679 ablation Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 63
- 238000000034 method Methods 0.000 claims description 38
- 239000010931 gold Substances 0.000 claims description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 14
- 229910052737 gold Inorganic materials 0.000 claims description 14
- 239000011247 coating layer Substances 0.000 claims description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- 229910052718 tin Inorganic materials 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 6
- 239000011135 tin Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- 230000008569 process Effects 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000002335 surface treatment layer Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 210000004185 liver Anatomy 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0391—Using different types of conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/282—Applying non-metallic protective coatings for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
Claims (5)
- 일면에 솔더패드 및 가이드패드가 형성된 기판을 제공하는 단계;상기 기판의 일면에 솔더레지스트층을 형성하는 단계;상기 가이드패드가 노출되도록 상기 솔더레지스트층의 일부를 오프닝하는 단계;상기 노출된 가이드패드에 대해 표면처리를 수행하는 단계;상기 솔더패드가 노출되도록 상기 솔더레지스트층의 일부를 오프닝하는 단계; 및상기 노출된 솔더패드에 솔더범프를 형성하는 단계를 포함하는 패키지용 인쇄회로기판 제조방법.
- 제1항에 있어서,상기 솔더범프를 형성하는 단계는,상기 기판의 일면에 시드층을 형성하는 단계;상기 기판의 일면에 상기 솔더패드에 상응하는 개구부가 형성된 도금레지스트층을 형성하는 단계; 및전해도금을 통하여, 상기 솔더패드에 솔더를 도금하는 단계;상기 도금레지스트층을 제거하는 단계;상기 시드층의 노출된 부분이 제거되도록 플래시 에칭을 수행하는 단계; 및상기 도금된 솔더에 대하여 리플로우를 수행하는 단계를 포함하는 것을 특징으로 하는 패키지용 인쇄회로기판 제조방법.
- 제1항에 있어서,상기 가이드패드에 대해 표면처리를 수행하는 단계는, 상기 가이드패드의 상면에 직접 금, 은, 주석 또는 유기보호피막(OSP)으로 이루어지는 코팅층을 형성함으로써 수행되는 것을 특징으로 하는 패키지용 인쇄회로기판 제조방법.
- 제1항에 있어서,상기 솔더패드가 노출되도록 상기 솔더레지스트층의 일부를 오프닝하는 단계는 LDA(Laser Direct Ablation) 기술을 이용하여 수행되는 것을 특징으로 하는 패키지용 인쇄회로기판 제조방법.
- 기판;상기 기판의 일면에 형성되는 솔더패드 및 가이드패드;상기 기판의 상기 일면을 커버하되, 상기 솔더패드 및 상기 가이드패드에 상 응하는 개구부가 형성된 솔더레지스트층;상기 가이드패드의 상면에 직접 형성되며, 금, 은, 주석 또는 유기보호피막(OSP)으로 이루어지는 코팅층; 및상기 솔더패드의 상면에 직접 형성되는 솔더범프를 포함하는 패키지용 인쇄회로기판.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080013912A KR100905922B1 (ko) | 2008-02-15 | 2008-02-15 | 패키지용 인쇄회로기판 및 그 제조방법 |
US12/219,140 US20090205854A1 (en) | 2008-02-15 | 2008-07-16 | Printed circuit board for a package and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080013912A KR100905922B1 (ko) | 2008-02-15 | 2008-02-15 | 패키지용 인쇄회로기판 및 그 제조방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR100905922B1 true KR100905922B1 (ko) | 2009-07-02 |
Family
ID=40954063
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020080013912A Expired - Fee Related KR100905922B1 (ko) | 2008-02-15 | 2008-02-15 | 패키지용 인쇄회로기판 및 그 제조방법 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20090205854A1 (ko) |
KR (1) | KR100905922B1 (ko) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101140978B1 (ko) | 2010-08-20 | 2012-05-03 | 삼성전기주식회사 | 인쇄회로기판의 제조방법 |
KR101255954B1 (ko) | 2011-12-22 | 2013-04-23 | 삼성전기주식회사 | 인쇄회로기판 및 인쇄회로기판 제조 방법 |
CN111970849A (zh) * | 2019-05-20 | 2020-11-20 | 鹏鼎控股(深圳)股份有限公司 | 电路板及其制作方法 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20190014128A (ko) * | 2010-08-02 | 2019-02-11 | 아토테크더치랜드게엠베하 | 기판 상에 솔더 성막 및 비용융 범프 구조들을 형성하는 방법 |
EP2506690A1 (en) * | 2011-03-28 | 2012-10-03 | Atotech Deutschland GmbH | Method to form solder deposits and non-melting bump structures on substrates |
KR101131288B1 (ko) * | 2010-12-06 | 2012-03-30 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US20130113118A1 (en) * | 2011-11-04 | 2013-05-09 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning Layer |
US8847078B2 (en) * | 2012-09-27 | 2014-09-30 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing printed wiring board |
CN103607848A (zh) * | 2013-11-27 | 2014-02-26 | 广东成德电路股份有限公司 | 一种用于提高印制电路板阻焊对位精度的方法 |
CN103997853A (zh) * | 2014-05-26 | 2014-08-20 | 蔡新民 | 一种超长铝基电路板的制作方法 |
JP2017034059A (ja) * | 2015-07-31 | 2017-02-09 | イビデン株式会社 | プリント配線板、半導体パッケージおよびプリント配線板の製造方法 |
US10204889B2 (en) * | 2016-11-28 | 2019-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of forming thereof |
US20200205295A1 (en) * | 2017-06-15 | 2020-06-25 | Jabil Inc. | System, Apparatus and Method for Utilizing Surface Mount Technology on Metal Substrates |
CN112566352A (zh) * | 2019-09-25 | 2021-03-26 | 李家铭 | 具有抗雷射填缝层的电路结构及其制法 |
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JP2007214534A (ja) | 2006-02-09 | 2007-08-23 | Phoenix Precision Technology Corp | 導電構造を具備する回路基板の製造方法 |
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JP2004012803A (ja) * | 2002-06-06 | 2004-01-15 | Fujitsu Ltd | 光伝送用プリント板ユニット及び実装方法 |
TWI286372B (en) * | 2003-08-13 | 2007-09-01 | Phoenix Prec Technology Corp | Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same |
TWI255158B (en) * | 2004-09-01 | 2006-05-11 | Phoenix Prec Technology Corp | Method for fabricating electrical connecting member of circuit board |
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2008
- 2008-02-15 KR KR1020080013912A patent/KR100905922B1/ko not_active Expired - Fee Related
- 2008-07-16 US US12/219,140 patent/US20090205854A1/en not_active Abandoned
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JP2004200412A (ja) | 2002-12-18 | 2004-07-15 | Kyocera Corp | 半田バンプ付き配線基板およびその製造方法 |
JP2007214534A (ja) | 2006-02-09 | 2007-08-23 | Phoenix Precision Technology Corp | 導電構造を具備する回路基板の製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101140978B1 (ko) | 2010-08-20 | 2012-05-03 | 삼성전기주식회사 | 인쇄회로기판의 제조방법 |
KR101255954B1 (ko) | 2011-12-22 | 2013-04-23 | 삼성전기주식회사 | 인쇄회로기판 및 인쇄회로기판 제조 방법 |
CN111970849A (zh) * | 2019-05-20 | 2020-11-20 | 鹏鼎控股(深圳)股份有限公司 | 电路板及其制作方法 |
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