KR100897349B1 - Semiconductor device test device - Google Patents

Abstract

The present invention relates to a semiconductor device test apparatus for testing a plurality of DUTs. According to the present invention, when sharing a signal such as an address or a command signal to test a larger number of DUTs simultaneously, the command / address signal and the clock signal are prevented in order to prevent quality deterioration in terms of signal integrity and timing accuracy. By applying to a plurality of DUT in a daisy chain method it is possible to minimize the malfunction of the semiconductor device test due to the delay between the command / address signal and the clock signal.

Command / Address Signals, Clock Signals, Daisy Chains, Fly-by, Delays, Loading Effects

Description

Semiconductor Device Test Equipment {TESTER FOR TESTING SEMICONDUCTOR DEVICE}

1 is an exemplary block diagram of a semiconductor device test apparatus according to the present invention.

2 is a diagram showing an exemplary configuration of a command / address path section and a clock signal path section of a semiconductor device test apparatus according to the present invention.

3 is a view showing an exemplary configuration of a data input signal path portion and a data output signal path portion of a semiconductor device test apparatus according to the present invention.

<Description of the symbols for the main parts of the drawings>

110: test pattern generation unit 120: command / address path unit

123: first deskew portion 125: first driver portion

127: first termination unit 130: clock signal path unit

133: second deskew section 135: second driver section

137: second termination part 140: data input signal path part

143: third deskew unit 145: third driver unit

150: data output signal path section 153: output delay compensation section

155: data output receiver 160: data comparator

200: DUT board 210: socket

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device testing apparatus, and more particularly to preventing quality deterioration in terms of signal integrity and timing accuracy when sharing a signal such as an address or command signal to test a larger number of DUTs simultaneously. The present invention relates to a semiconductor device test apparatus for minimizing a malfunction of a semiconductor device test due to a delay between a command / address signal and a clock signal by applying a command / address signal and a clock signal to a plurality of DUTs in a daisy chain manner.

The semiconductor device test apparatus is a device for testing whether a manufactured semiconductor device is defective. Since the semiconductor device test apparatus is often used for testing a memory device, the semiconductor device test apparatus is designed and developed according to the development situation of a memory device, in particular, a DRAM development which occupies a substantial portion of the memory device.

Current DRAM developments are being developed into DRAMs with Extended Data Output (EDO), Synchronous DRAM (SRAM), Rambus (DRAM) DRAM, and Double Data Rate (DDR) DRAM.

In order to test such DRAMs, semiconductor device test apparatuses are required to have high speed and high precision in response to high speeds of memory. In addition, since the test time increases with the increase of the memory, the test speed must also be faster. In addition, miniaturized and economical semiconductor device test devices must be implemented to reduce test costs.

Semiconductor device test devices, particularly memory test devices, among others, are used to test and verify memory modules typically in memory components or SIMM or DIMM configurations. The semiconductor device test apparatus detects whether a functional defect on a memory module or component exists before the memory module or memory component is mounted and used in an actual computer system.

The semiconductor device test apparatus can be broadly classified into a hardware semiconductor device test apparatus and a software diagnostic program executed in a PC environment. However, since a software diagnostic program diagnoses a memory state when a memory module or component is mounted on a real computer and used, a hardware memory test apparatus is mainly used in the semiconductor memory production process.

The hardware semiconductor device test apparatus may be classified into a high-class test apparatus called an ATE (automatic test equipment), a medium range memory test apparatus, a low-end memory test apparatus, and the like.

To perform the test process of memory devices, ATE, a high-end test device, is typically used. Such conventional ATE includes a DC test that tests the DC parameters for the digital operation of the circuit, an AC margin test related to the signal propagation delay time, the set-up time and the hold time, etc. It has various functions such as test pattern generation and timing generation.

Meanwhile, in the test of the semiconductor device, the semiconductor test apparatus is configured to apply a data signal to each device under test (DUT) to be tested and to receive a response signal corresponding to the data signal from the DUT to test the operation of the DUT. . It is also configured to test multiple DUTs simultaneously for test efficiency.

The data signal may include, for example, a clock signal for operating the DUT, a command / address signal, a data input signal as data, and the like.

Meanwhile, a configuration including a plurality of sockets for mounting the DUT for testing the plurality of DUTs, that is, a DUT board (also referred to as a socket board) is used.

In this case, the DUT is mounted in a plurality of sockets on the DUT board through a handler or the like, and the semiconductor device test apparatus applies the clock signal, the command / address signal, and the data input signal to the plurality of DUTs through the socket.

However, in particular, when a memory device that performs high-speed operation such as DDR2 or DDR3 is a DUT, when a clock signal, a command / address signal, or a data input signal is applied to each socket, it is different for each DUT according to the configuration of the DUT board. Delays may occur.

In particular, sharing a signal, such as an address or command signal, for example to test a larger number of DUTs simultaneously will result in quality degradation in terms of signal integrity and timing accuracy.

If quality degradation occurs in the integrity of the signal and timing accuracy, the ATE device design must compensate for this problem. However, if these compensations are not performed correctly, you will not be able to correctly test the DUT.

In particular, if a delay occurs between a clock signal applied to the DUT and a command / address signal, compensation is required. However, a complicated configuration is required for such compensation. For example, compensation is required for the problem that the signal delay varies according to the deviation in manufacturing the DUT board.

An object of the present invention is to provide a command / address signal and a clock signal in order to prevent quality deterioration in terms of signal integrity and timing accuracy when sharing a signal such as an address or command signal to test a larger number of DUTs simultaneously. The present invention provides a semiconductor device test apparatus which minimizes malfunction of semiconductor device tests due to a delay between a command / address signal and a clock signal by applying to a plurality of DUTs in a daisy chain manner.

In order to achieve the above technical problem, the present invention provides a semiconductor device test apparatus for testing a plurality of DUT, and a test pattern generator for generating a clock signal, a command / address signal and a data input signal for testing the plurality of DUT; And a command / address path unit for daisy-chaining the command / address signal input terminals of each of the plurality of DUTs, and applying the command / address signal to the command / address signal input terminal, and each of the plurality of DUTs A clock signal input unit connected to the clock signal input terminal having the daisy chain method, the clock signal path unit applying the clock signal to the clock signal input terminal, and applying the data input signal to a data signal input terminal included in each of the plurality of DUTs. A data input signal path section and the plurality of DUTs Examine whether each of the plurality of DUTs is defective on the basis of a data output signal path unit for receiving data output signals respectively output from the data signal output terminal provided in each of the data output signals received through the data output signal path unit. A semiconductor device test apparatus including a data comparison unit is provided.

In the semiconductor device test apparatus according to the present invention, the command / address path part includes a first termination part connected to an end of the command / address signal input terminal connected in the daisy chain manner, and the clock signal path part includes: And a second termination part connected to an end of the clock signal input terminal connected in a daisy chain manner.

In the semiconductor device test apparatus according to the present invention, the command / address path unit may include a first deskew unit for removing skew of the command / address signal generated by the test pattern generator, and a command / address from which the skew is removed. And a first driver unit for applying a signal to the command / address signal input terminal connected in the daisy chain manner.

In the semiconductor device test apparatus according to the present invention, the clock signal path unit may include a second deskew unit for removing skew of the clock signal generated by the test pattern generator, and the daisy chain of the clock signal from which the skew is removed. It may include a second driver for applying to the clock signal input terminal connected in a manner.

In the semiconductor device test apparatus according to the present invention, the data input signal path unit may include a third deskew unit configured to set a delay of the data input signal generated by the test pattern generator input to each of the plurality of DUTs; The third driver may include a third driver configured to apply a data input signal having a delay corresponding to each of the plurality of DUTs.

In the semiconductor device test apparatus according to the present invention, the third deskew unit may delay the delay of the data input signal in response to the delay of the command / address signal and the clock signal input to each of the plurality of DUTs. Can be set.

In the semiconductor device test apparatus according to the present invention, the data output signal path unit may include a data output receiver configured to receive the data output signals output from each of the plurality of DUTs, and an output delay configured to set a delay of the data output signal. It may include a compensation unit.

In the semiconductor device test apparatus according to the present invention, the delay of the data output signal may be set so that the data output signals of each of the plurality of DUTs are compared at the same time.

In the semiconductor device test apparatus according to the present invention, the data output receiver may receive the data output signals output from the data signal output terminals of each of the plurality of DUTs, and if the data output signal is equal to or greater than a predetermined value, the H ( and a logic comparator for outputting a high logic value and outputting an L (low) logic value when the logic value is less than or equal to the predetermined value.

In the semiconductor device test apparatus according to the present invention, the test pattern generation unit may further generate a test expectation signal for the data input signal, and the data comparator compares the test expectation signal with the data output signal. Each of the plurality of DUTs may be inspected for defects.

Hereinafter, an embodiment of a semiconductor device test apparatus of the present invention will be described in more detail with reference to the accompanying drawings.

1 is an exemplary block diagram of a semiconductor device test apparatus according to the present invention.

As illustrated, the semiconductor device test apparatus according to the present invention includes a test pattern generator 110, a command / address path unit 120, a clock signal path unit 130, a data input signal path unit 140, And a data output signal path unit 150 and a data comparator 160.

The test pattern generator 110 generates a clock signal, a command / address signal, and a data input signal for testing a plurality of DUTs. The clock signal, command / address signal and data input signal are then applied to the DUT.

The test pattern generator 110 may include, for example, an algorithm pattern generator (ALPG). ALPG is a device that outputs a signal of a desired pattern according to a program stored by a user. ALPG can be implemented using a field programmable gate array (FPGA).

The command / address path unit 120 connects the command / address signal input terminals of each of the plurality of DUTs in a daisy chain manner, and connects the command / address signals generated by the test pattern generator 110 to the command / address signal input terminals. Is authorized.

Each of the plurality of DUTs has a command / address signal input.

In this case, a socket or the like is disposed in correspondence with each of the plurality of DUTs for the test, and the command / address path unit 120 performs a fly-by structure, that is, a daisy chain method, on the command / address input terminal of the socket. In connection, the command / address signal may be configured to be applied to a plurality of DUT signals. The daisy chain refers to a configuration of hardware devices connected in series and will be described in more detail with reference to FIG. 2.

In the semiconductor device test apparatus according to the present invention, in the case of the command / address signal, two or four or more DUTs share a signal for testing more DUTs, and at this time, a conventional star-stub Daisy chains, rather than stubs, improve signal integrity.

The clock signal path unit 130 connects the clock signal input terminals of each of the plurality of DUTs in a daisy chain manner to apply the clock signals generated by the test pattern generator 110 to the plurality of DUTs.

Each of the plurality of DUTs includes a clock signal input terminal.

In this case, a socket or the like is disposed to correspond to each of the plurality of DUTs for the test, and the clock signal path unit 130 connects the clock input terminal of the socket in a fly-by structure, that is, in a daisy chain manner, so that the clock signals are provided in the plurality of DUTs. It can be configured to be applied to a signal.

In the semiconductor device test apparatus according to the present invention, in the case of a clock signal, two or four or more DUTs share a signal to test more DUTs, and in this case, daisy, not a conventional star-stub method, is used. Connections can be chained to improve signal integrity.

In addition, both the clock signal and the command / address signal are applied to the plurality of DUTs through a daisy chain method.

Applying both the clock signal and the command / address signal through the daisy chain method is because a delay occurs between the clock signal and the command / address signal when the clock signals are not daisy chained.

This delay increases with the number of DUTs to which a signal is applied, especially via daisy chaining.

Therefore, in order not to compensate for this delay, the clock signal is applied to the clock signal input terminals connected in a daisy chain manner as in the command / address signal.

The command / address path unit 120 and the clock signal path unit 130 will be described in more detail with reference to FIG. 2.

The data input signal path unit 140 applies data input signals generated by the test pattern generator 110 corresponding to each data signal input terminal of the plurality of DUTs.

Each of the plurality of DUTs has a data signal input terminal.

The data input signal path unit 140 is configured to apply a data input signal to each DUT separately from the command / address path unit 120 or the clock signal path unit 130.

The data output signal path unit 150 receives data output signals output from respective data signal output terminals of the plurality of DUTs.

Each of the plurality of DUTs has a data signal output stage.

The data output signal path unit 150 is configured to receive the data output signal separately for each DUT similarly to the data input signal path unit 140.

The data input signal path unit 140 and the data output signal path unit 150 will be described in more detail with reference to FIG. 3.

The data comparator 160 checks whether each of the plurality of DUTs is defective based on the data output signal received by the data output signal path unit 150.

For example, when the test pattern generator 110 generates a test expectation signal for the data input signal, the data comparator 160 may generate the test expectation signal and the data output signal path unit generated by the test pattern generator 110. The 150 compares the received data output signal to check whether each of the plurality of DUTs is defective.

2 is a diagram illustrating an exemplary configuration of a command / address path unit and a clock signal path unit of the semiconductor device test apparatus according to the present invention.

In FIG. 2, the DUT board 200, the command / address path unit 120 (FIG. 1) and the clock signal path unit 130 (FIG. 1) are shown.

As shown, a plurality of sockets 210a to 210d for mounting a plurality of DUTs are provided on the DUT board 200. Each socket is provided with a connection configuration corresponding to each input terminal or output terminal of the DUT. For example, a connection configuration corresponding to a command / address signal input terminal or a clock signal input terminal in a circle form is illustrated.

Although four sockets 210a to 210d are shown in FIG. 2, for example, 16 or more sockets may be mounted on the DUT board 200.

As shown in FIG. 1, the command / address path unit 120 of FIG. 1 is connected in a daisy chain manner to correspond to the command / address signal input terminal of the DUT during the connection configuration of the sockets 210a to 210d.

That is, the connection configuration corresponding to the command / address signal input terminal of the socket 210a, the connection configuration corresponding to the command / address signal input terminal of the socket 210b, and the connection configuration corresponding to the command / address signal input terminal of the socket 210c. And the connection configuration corresponding to the command / address signal input terminal of the socket 210d are daisy chained with each other.

The command / address path unit 120 of FIG. 1 may include a first deskew unit 123 and a first driver unit 125. In addition, the command / address path unit 120 of FIG. 1 may include a first termination unit 127 as shown.

The first deskew unit 123 removes the skew of the command / address signal generated by the test pattern generation unit 110 of FIG. 1.

The first deskew unit 123 is for removing skew occurring before the command / address signal generated by the test pattern generator 110 (in FIG. 1) is applied to the DUT board 200. In addition, the first deskew unit 123 may set a delay in consideration of a user delay setting.

The first driver unit 125 applies a command / address signal from which skew is removed to the command / address signal input terminal connected in a daisy chain manner through the first deskew unit 123.

Meanwhile, the command / address path unit 120 of FIG. 1 may include a first termination unit 127 connected to an end of the command / address signal input terminal connected in a daisy chain manner.

That is, the first termination unit 127 may include a termination resistor and prevent the command / address signal from being reflected at the end of the daisy chain.

The clock signal path unit 130 of FIG. 1 is daisy-chained to correspond to the clock signal input terminal of the DUT during the connection configuration of the sockets 210a to 210d.

That is, the connection configuration corresponding to the clock signal input terminal of the socket 210a, the connection configuration corresponding to the clock signal input terminal of the socket 210b, the connection configuration corresponding to the clock signal input terminal of the socket 210c, and the socket 210d. The connection configurations corresponding to the clock signal input terminals of are daisy chained with each other.

The clock signal path unit 130 of FIG. 1 may include a second deskew unit 133 and a second driver unit 135 as shown. In addition, the clock signal path unit 130 of FIG. 1 may include a second termination unit 137 as shown.

The second deskew unit 133 removes the skew of the clock signal generated by the test pattern generator 110 of FIG. 1.

The second deskew unit 133 is for removing skew generated before the clock signal generated by the test pattern generator 110 (in FIG. 1) is applied to the DUT board 200. Also, the second deskew unit 133 may set a delay in consideration of a user delay setting.

The second driver 135 applies a clock signal from which skew is removed through the second deskew unit 123 to a clock signal input terminal connected in a daisy chain manner.

Meanwhile, the clock signal path unit 130 of FIG. 1 may include a second termination unit 137 connected to an end of the clock signal input terminal connected in a daisy chain manner.

That is, the second termination unit 137 may include a termination resistor and prevent the clock signal from being reflected at the end of the daisy chain.

Meanwhile, as shown in FIG. 2, a configuration for applying a command / address signal or a clock signal generated by the test pattern generator 110 to the DUT board 200, that is, a command / address path unit (120 of FIG. 1) and a clock The signal path units 130 of FIG. 1 correspond to each other. The reason for taking this corresponding configuration is to reduce the loading effect that can occur when a command / address signal or clock signal is applied to each DUT. That is, if the paths for the clock signal and the command / address signal are not the same, the load may be different for each of the clock signal and the command / address signal in each DUT. Therefore, the clock signal may have a delay for the command / address signal. have. The delay caused by this change in load is called the loading effect.

However, in the present invention, as described above, the configuration of the command / address path unit 120 and the clock signal path unit 130 may correspond to each other to minimize the loading effect.

In addition, it is possible to minimize the delay component that occurs during the manufacturing of the DUT board 200 through this configuration.

That is, when the configuration of applying the command / address signal or the clock signal to the DUT board 200 does not correspond to each other, fine calibration is required separately for the delay component generated when the DUT board 200 is manufactured. As described above, the configuration of the command / address path unit 120 and the clock signal path unit 130 correspond to each other, so that fine correction of delay components due to variations in manufacturing the DUT board 200 is not required. have.

3 is a diagram illustrating an exemplary configuration of a data input signal path unit and a data output signal path unit of the semiconductor device test apparatus according to the present invention.

In FIG. 3, the DUT board 200, the data input signal path unit 140 (FIG. 1), and the data output signal path unit 150 (FIG. 1) are shown.

As shown, a plurality of sockets 210a to 210d for mounting a plurality of DUTs are provided on the DUT board 200. In each socket, a connection configuration corresponding to each data signal input terminal or data signal output terminal of the DUT is arranged. For example, a connection configuration corresponding to the data signal input terminal or the data signal output terminal in a circle shape is illustrated. In addition, the data signal input terminal and the data signal output terminal are shown in the same circle form.

As shown in FIG. 1, the data input signal path unit 140 may generate a data input signal generated by the test pattern generator 110 for each connection configuration of the sockets 210a to 210d corresponding to the data signal input terminals of the plurality of DUTs. Apply each.

That is, while the command / address path section 120 (FIG. 1) or the clock signal path section 130 (FIG. 1) daisy-chains, the data input signal path section 140 (FIG. 1) has a socket 210a to 210d, respectively. Each data input signal is configured to be applied separately.

As illustrated, the data input signal path unit 140 may include third deskew units 143a to 143d and third driver units 145a to 145d.

The third deskew units 143a to 143d set delays of the data input signals for each of the plurality of DUTs.

The third deskew units 143a to 143d are for removing skews generated before the data input signal generated by the test pattern generator 110 (in FIG. 1) is applied to the DUT board 200. Also, the third deskew units 143a to 143d may set a delay in consideration of user delay setting and the like.

In addition, the third deskew units 143a to 143d may remove the skew, and the command / address signal input terminal and the clock signal input terminal of the DUT may include the command / address path unit (120 in FIG. 1) and the clock signal path unit (130 in FIG. 1). According to the daisy chain method, the delay of the data input signal may be set to compensate for the transmission delay for the command / address signal or the clock signal generated for each DUT.

This will be described in more detail as follows. As shown in FIG. 2, the sockets 210a to 210d are connected by, for example, signal wires. Accordingly, when the command / address signal or the clock signal is applied to the DUT corresponding to the socket 210a, when the command / address signal or clock signal is applied to the DUT corresponding to the socket 210b, when the command / address signal or clock signal is applied to the DUT corresponding to the socket 210c, and the socket ( The difference occurs at the time when the DUT corresponding to 210d) is applied.

Therefore, it is preferable to set the delay of the data input signal in response to the transmission delay of the command / address signal or the clock signal.

This will be described in more detail as follows.

For example, as illustrated, the third deskew unit 143a corresponding to the socket 210a does not have to consider transmission delay of the command / address signal or the clock signal, and the data input signal generated by the test pattern generator (110 of FIG. 1). It will be sufficient to eliminate the skew that occurs before is applied to the DUT board 200.

As illustrated, the third deskew unit 143b corresponding to the socket 210b should additionally consider a transmission delay of a command / address signal or a clock signal according to the transmission between the socket 210a and the socket 210b.

Accordingly, the third deskew unit 143b performs compensation by additionally setting the transmission delay of the command / address signal or the clock signal between the socket 210a and the socket 210b as well as removing skew of the third deskew unit 143a. .

Similarly, the third deskew unit 143c corresponding to the socket 210c additionally performs a command according to the transmission between the socket 210b and the socket 210c in addition to the delay compensation of the third deskew unit 143b corresponding to the socket 210b. Compensation is performed by additionally setting the transmission delay of the address signal or the clock signal.

Similarly, the third deskew unit 143d corresponding to the socket 210d may further include a command according to transmission between the socket 210c and the socket 210d in addition to the delay compensation of the third deskew unit 143c corresponding to the socket 210c. Compensation is performed by additionally setting the transmission delay of the address signal or the clock signal.

As such, the third deskew units 143a to 143d may set a delay of the data input signal to have different delay values for each of the plurality of DUTs.

The third driver units 145a to 145d apply data input signals differently set to each of the plurality of DUTs from the third deskew units 143a to 143d to each of the plurality of DUTs.

As illustrated, the data output signal path unit 150 of FIG. 1 receives a data output signal output from each of the connection configurations of the sockets 210a to 210d corresponding to the data signal output terminals of the plurality of DUTs.

The data output signal path section 150 of FIG. 1 is configured to receive data output signals separately from each of the sockets 210a to 210d, similarly to the data input signal path section 140 of FIG. 1.

The data output signal path unit 150 of FIG. 1 may include output delay compensators 153a to 153d and data output receivers 155a to 155d as shown.

The output delay compensators 153a to 153d set the delay of the data output signal for each of the plurality of DUTs.

That is, as shown in FIG. 2, the sockets 210a to 210d are connected by, for example, signal wires. Accordingly, when the command / address signal or the clock signal is applied to the DUT corresponding to the socket 210a, when the command / address signal or clock signal is applied to the DUT corresponding to the socket 210b, when the command / address signal or clock signal is applied to the DUT corresponding to the socket 210c, and the socket ( A difference occurs at a time point applied to the DUT corresponding to 210d), and thus, a time point at which the data output signal is output also occurs for each DUT, that is, for an output from the sockets 210a to 210d.

That is, when the data output signal is output from the socket 210a, when the data output signal is output from the socket 210b, when the data output signal is output from the socket 210c, and when the data output signal is output from the socket 210d. There is a difference between the time points.

Therefore, it is desirable to set a delay of the data output signal to compensate for this.

In this case, it is preferable to set the delay of the data output signal for each of the plurality of DUTs in order to compare outputs from the plurality of DUTs, that is, data output signals at the same time.

That is, the command / address signal input terminal of the command / address path unit (120 of FIG. 1) and the clock signal path unit (130 of FIG. 1) and the clock signal input terminal are daisy-chained to output data output signals output from each DUT. Differences in viewpoints occur. Accordingly, the output delay compensators 153a to 153d may set the delay of the data output signal to compensate for the difference in the output time point of the data output signal generated for each DUT so that the data output signals can be compared at the same time point.

This will be described in more detail as follows.

For example, suppose that after a data output signal is output from each of the sockets 210a to 210d, the output delay compensation units 153a to 153d are compensated to perform the test at the same time.

As shown in the drawing, the output delay compensator 153a corresponding to the socket 210a has a delay caused by the transmission between the socket 210a and the socket 210d to compensate for the same time as the data output signal output from the socket 210d. You can additionally set

In addition, the output delay compensator 153b corresponding to the socket 210b additionally compensates for the delay caused by the transmission between the socket 210b and the socket 210d to compensate for the same time as the data output signal output from the socket 210d. Can be set.

Also, the output delay compensator 153c corresponding to the socket 210c additionally compensates for the delay caused by the transmission between the socket 210c and the socket 210d to compensate for the same time as the data output signal output from the socket 210d. Can be set.

In addition, the output delay compensation unit 153d corresponding to the socket 210d may not need a separate delay setting.

However, instead of compensation due to the transmission delay, a delay may be set, for example, by a user setting.

The delay caused by the user setting may be equally set in the output delay compensators 153a to 153c corresponding to the other sockets 210a to 210c.

As described above, the output delay compensators 153a to 153d may set the delays of the data output signals to have different delay values for each of the plurality of DUTs so that the data output signals can be compared at the same time.

The data output receivers 155a to 155d receive data output signals for each of the plurality of DUTs.

That is, a configuration for receiving a data output signal output from the corresponding connection configuration of the socket (210a to 210d).

In this case, the data output receivers 155a to 155d respectively receive data output signals output from the data signal output terminals of the plurality of DUTs, and output H (high) logic values when the data output signals are greater than or equal to a predetermined value. It may include a logic comparison unit (not shown) for outputting an L (low) logic value below the value.

That is, the data output receivers 155a to 155d may further include a logic comparator (not shown) to restore the digital signal.

Although the configuration of the present invention has been described in detail, these are merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. This will be possible.

Therefore, the embodiments disclosed herein are not intended to limit the present invention but to describe the present invention, and the spirit and scope of the present invention are not limited by these embodiments. It is intended that the scope of the invention be interpreted by the following claims, and that all descriptions within the scope equivalent thereto will be construed as being included in the scope of the present invention.

As described above, according to the present invention, when sharing a signal such as an address or a command signal to test a larger number of DUTs simultaneously, the command / address signal is prevented in order to prevent quality deterioration in terms of signal integrity and timing accuracy. By applying the clock signal to the plurality of DUTs in a daisy chain manner, malfunction of the semiconductor device test due to the delay between the command / address signal and the clock signal can be minimized.

Claims (10)

A semiconductor device test device for testing a plurality of device under test (DUT), A test pattern generator configured to generate a clock signal, a command / address signal, and a data input signal for testing the plurality of DUTs; A command / address path unit for daisy-chaining the command / address signal input terminals of each of the plurality of DUTs, and applying the command / address signal to the command / address signal input terminals; A clock signal path unit connecting the clock signal input terminals of each of the plurality of DUTs in the daisy chain manner, and applying the clock signal to the clock signal input terminal; A data input signal path unit for applying the data input signal to a data signal input terminal of each of the plurality of DUTs; A data output signal path unit for receiving a data output signal respectively output from a data signal output terminal included in each of the plurality of DUTs; A data comparison unit checking whether each of the plurality of DUTs is defective based on the data output signal received through the data output signal path unit; Semiconductor device test apparatus comprising a. The method of claim 1, The command / address path unit may include a first termination unit connected to an end of the command / address signal input terminal connected in the daisy chain manner. The clock signal path unit may include a second termination unit connected to an end of the clock signal input terminal connected in the daisy chain manner. The method of claim 1, The command / address path unit A first deskew unit for removing skew of the command / address signal generated by the test pattern generator; A first driver unit applying the command / address signal from which the skew is removed to the command / address signal input terminal connected in the daisy chain manner Semiconductor device test apparatus comprising a. The method of claim 1, The clock signal path unit, A second deskew unit configured to cancel skew of the clock signal generated by the test pattern generator; A second driver unit applying the clock signal from which the skew is removed to the clock signal input terminal connected in the daisy chain manner; Semiconductor device test apparatus comprising a. The method of claim 1, The data input signal path unit, A third deskew unit configured to set a delay of the data input signal generated by the test pattern generator input to each of the plurality of DUTs; A third driver unit applying the delayed data input signal to each of the plurality of DUTs Semiconductor device test apparatus comprising a. The method of claim 5, And the third deskew unit sets a delay of the data input signal in response to a delay of the command / address signal input to each of the plurality of DUTs and a delay of the clock signal. The method of claim 1, The data output signal path unit, A data output receiver configured to receive the data output signals output from each of the plurality of DUTs; An output delay compensator for setting a delay of the data output signal Semiconductor device test apparatus comprising a. The method of claim 7, wherein The output delay compensation unit, And setting a delay of the data output signal such that the data output signals of each of the plurality of DUTs are compared at the same time point. The method of claim 7, wherein The data output receiving unit receives the data output signals output from the data signal output terminals of each of the plurality of DUTs, and outputs a high logic value when the data output signal is greater than or equal to a predetermined value. Logic comparator to output L (low) logic value Semiconductor device test apparatus comprising a. The method of claim 1, The test pattern generator is to generate a test expectation signal for the data input signal. The data comparison unit compares the test expectation signal and the data output signal to check whether each of the plurality of DUTs is defective.

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