KR100893959B1 - Processing method and plasma etching method - Google Patents

Abstract

An object of the present invention is to provide a plasma etching method capable of preventing the occurrence of pits and controlling the etching shape when performing silicon etching using SF ₆ / O ₂ / SiF ₄ as an etching gas.

In a processing chamber of a plasma processing apparatus, a silicon oxide is formed on a etching target layer via a silicon oxide layer, and a resist layer formed in advance is formed as a mask from a processing gas containing SF ₆ , O _2, and SiF ₄ . The first silicon etching step of etching the etching target layer by the plasma to be formed, and the second silicon etching etching the etching target layer by the plasma using the silicon oxide layer as a mask after the resist layer is scraped off. Carry out the process.

Description

Processing Method and Plasma Etching Method {PROCESSING METHOD AND PLASMA ETCHING METHOD}

1 is a flowchart showing an outline of a processing method according to the first embodiment of the present invention,

2 is a schematic diagram showing a cross-sectional structure near the surface of a semiconductor wafer to which the method of the present invention is applied;

3 is a view showing a state of the semiconductor wafer after etching the SiO ₂ layer,

4 is a view showing a state in which a semiconductor wafer is processed by plasma in a first silicon etching step;

5 is a diagram showing a state of the semiconductor wafer after the first silicon etching process;

FIG. 6 is a diagram showing a state in which a semiconductor wafer is processed by plasma in a second silicon etching step;

7 is a view showing a state of the semiconductor wafer after the second silicon etching process;

FIG. 8 is a cross-sectional view showing a magnetron RIE plasma etching apparatus suitable for implementing the etching method of the present invention.

FIG. 9 is a horizontal cross-sectional view schematically illustrating the dipole ring magnet in a state disposed around the chamber of the apparatus of FIG. 8, FIG.

10 is a schematic diagram for explaining the electric and magnetic fields formed in the chamber,

11 is a flowchart showing an outline of a processing method according to the second embodiment of the present invention;

It is a schematic diagram which shows the cross-sectional structure of the surface vicinity of the semiconductor wafer of each process which concerns on 2nd Embodiment,

13 is a flowchart showing an outline of a processing method according to the third embodiment of the present invention;

It is a schematic diagram which shows the cross-sectional structure of the surface vicinity of the semiconductor wafer of each process which concerns on 3rd Embodiment,

It is a figure explaining the outline | summary of the plasma etching of a prior art.

(Explanation of symbols about main parts of drawing)

1: chamber (processing container) 2: support table (electrode)

12: exhaust system 15: high frequency power source

17: refrigerant chamber 18: gas introduction mechanism

20: shower head (electrode) 23: process gas supply system

24: dipole ring magnet 101: silicon substrate

102: SiO ₂ layer 103: resist

W: wafer

 Patent Document 1: Japanese Patent Publication No. 2004-87738

TECHNICAL FIELD This invention relates to a processing method and a plasma etching method in detail regarding the processing method and the plasma etching method including the process of etching a to-be-processed object using a plasma.

In the manufacturing process of a semiconductor device, etching is performed on a silicon substrate for the purpose of forming a trench for element isolation or a trench for capacitor, for example. For example, in trench formation for deep trench isolation or trench formation for memory cells and capacitors, grooves and holes having a high aspect ratio of about 0.8 to 1.2 μm and about 5 to 8 μm in depth are formed on the Si substrate. Silicon etching is performed for the purpose of doing so. Also in a three-dimensional mounting device or MEMS (Micro Electro Mechanical System), etching is performed to form through holes for wiring, grooves for mechanical structures, and the like in a Si substrate at a depth of 100 μm or more.

In the silicon etching, as the etching gas with the oxide mask such as SiO ₂ film has been used a lot of SF ₆ / O ₂ gas.

However, SF ₆ / O ₂ gas has a problem that undercut is likely to occur immediately below the mask and that the selectivity with the oxide film mask is not sufficiently obtained. In order to improve this problem, it is proposed to use SF ₆ / O ₂ / SiF ₄ as an etching gas. (For example, patent document 1).

As shown in the patent document 1, inhibit the undercut by using a SF ₆ / O ₂ / SiF ₄ as the etching gas, it is possible to improve the non-selective film. By the way, when plasma etching is performed using the said etching gas, it turned out that many small holes called "pits" are formed on an oxide film mask. If the pit grows in the process of silicon etching and reaches the silicon through the oxide film mask, it causes a bad effect on the semiconductor device.

15A to 15E show a cross-sectional structure near the surface of a semiconductor wafer, and show the formation and growth of pits when silicon etching is performed using SF ₆ / O ₂ / SiF ₄ as an etching gas. The process is schematically illustrated. In the state of FIG. 15A, a SiO ₂ layer 202 is formed on the silicon substrate 201, and a resist 203 is formed thereon. The SiO ₂ layer 202 is etched according to the pattern of the resist 203, and the opening 210 is formed. The etching of the SiO ₂ layer 202 is performed by a gas system such as Ar / CxFy / O ₂ containing a fluorocarbon compound such as C ₄ F ₆ , C ₅ F ₈ , for example. Reaction products, such as SiO, SiOF, and SiCF, are affixed to the side wall or the surface of the resist 203 as the deposit 204 (x, y in the CxFy means a stoichiometric number. .

Although FIG. 15B shows a state after the resist 203 is peeled off by ashing, wet treatment, or the like, the deposit 204 is not completely removed on the semiconductor wafer, and the SiO ₂ layer 202 is removed. It remains on the surface of the, which becomes the nucleus of the pit. That is, as shown in FIG. 15C, when the etching resistance of the deposit 204 is stronger than that of the SiO ₂ layer 202, in the process of etching the silicon substrate 201, the periphery of the deposit 204 is increased. Is selectively etched to form the micro trench 211. When such a micro trench 211 is formed, the reaction product (deposit) at the time of etching becomes difficult to attach, and ion concentration to the bottom of the micro trench 211 occurs, whereby a SiO ₂ layer ( Etch rate is higher than other portions of 202). As a result, as shown in Fig. 15D, the micro trench 211 deepens as the silicon etching proceeds, and grows into the pits 212. As shown in Fig. 15E, when the deep pits 212, which reach the silicon substrate 201, are formed, it causes damage to the reliability of the semiconductor device.

Formation of the pit 212 is performed by etching the SiO ₂ layer 202 using the patterned resist 203 as a mask and then nucleating the pit 212 on the SiO ₂ layer 202 even if the resist 203 is peeled off. This is because the deposit 204 to be used remains and the micro trench 211 is formed. For this reason, the thickness of the resist 203 is set sufficiently thick in advance, and the resist 203 remains as a mask until the end of the silicon etching, thereby preventing the formation of the micro trenches 211 to the pits 212. It is thought that it is possible to prevent growth. However, if only the resist 203 is used as a mask to perform silicon etching to the end point, it is difficult to control the shape of the high aspect ratio trench formed in silicon, and the sidewalls of the trench are inclined to become a bowing shape. there is a problem. This phenomenon uses the resist 203 instead of the oxide film (SiO ₂ layer 202) as a mask, so that the carbon in the resist reacts with the protective films (SiO, SiOF) on the trench sidewalls to etch it, so that the horizontal direction is used. It is considered that the cause is due to the progress of silicon etching.

SUMMARY OF THE INVENTION An object of the present invention has been carried out in view of the above circumstances, and when performing silicon etching using SF ₆ / O ₂ / SiF ₄ as an etching gas, plasma etching can be prevented and the etching shape can be controlled. To provide a way.

MEANS TO SOLVE THE PROBLEM In order to solve the said subject, the 1st viewpoint of this invention is the etching target layer which has silicon as a main component, the silicon oxide layer formed on this etching target layer, and the patterning resist previously formed on this silicon oxide layer. A silicon oxide etching step of performing a plasma etching treatment on the silicon oxide layer using the resist layer as a mask for a target object having a layer;

A deposit removal step of removing the deposit formed by the silicon oxide etching step and adhering to the workpiece;

Provided is a processing method including a silicon etching step of performing a plasma etching treatment on an etching target layer using a plasma generated from a processing gas containing SF ₆ , O _2, and SiF ₄ , using the silicon oxide layer as a mask.

In the first aspect, the deposit removing step is performed by using a plasma generated from a processing gas containing SF ₆ , O _2, and SiF ₄ , using the resist layer as a mask before the silicon etching revolution. The etching target layer may be etched until the chipping is completed. Alternatively, the deposit removing step may include a resist peeling process for peeling the resist layer and a surface etching process for etching the surface of the silicon oxide layer after the resist peeling process. Alternatively, the deposit removal step may be performed by simultaneously removing the resist layer and deposit removal by plasma of a processing gas containing an O ₂ gas and a fluorocarbon gas (gas containing a CxFy compound). In this case, it is preferable to use CF ₄ , C ₄ F ₈ as the fluorocarbon gas.

A second aspect of the present invention relates to an etching target layer containing silicon as a main component in a processing chamber of a plasma processing apparatus.

Plasma etching using a process gas containing SF ₆ , O _2, and SiF ₄ as a processing gas generating plasma, using a silicon oxide layer formed on the etching target layer and a resist layer formed on the silicon oxide layer as a mask. A plasma etching method is provided, comprising a plasma etching step of performing a process to form a recess in an etching target layer.

It is preferable that the film thickness of the said resist layer at the start time of the said plasma etching process is 300 nm or more and 1 micrometer or less from a said 2nd viewpoint. Further, even after the resist layer is cut off, etching is continued using the silicon oxide layer as a mask. In this case, it is preferable that the ratio D / L of the depth D and the width L of the concave portion at the time when the resist layer is scraped off is 1 or less. Moreover, it is preferable that ratio (D / L) of the depth D and the width L of the said recessed part after completion | finish of the said plasma etching process is 1-50.

The plasma etching step includes a first silicon etching step of etching the etching target layer using the resist layer as a mask, and etching the etching target layer using the silicon oxide layer as a mask after the resist layer has been scrapped. It is preferable to include a 2nd silicon etching process. In this case, it is preferable to distribute the time of the first silicon etching process and the time of the second silicon etching process so that the sidewall of the concave portion is formed substantially vertically corresponding to the opening width of the mask.

According to a third aspect of the present invention, there is provided a process for generating plasma from a processing gas containing SF ₆ , O _2, and SiF ₄ in a processing chamber of a plasma processing apparatus,

A first silicon etching step of etching the etching target layer by the plasma using a resist layer having a pattern formed in advance on the etching target layer having silicon as a main component as a mask;

A plasma etching method is provided, including a second silicon etching step of etching the etching target layer by the plasma after the resist layer is scraped off, using the silicon oxide layer as a mask.

It is preferable that the film thickness of the said resist layer at the time of starting a said 1st silicon etching process is 300 nm or more and 1 micrometer or less from a said 3rd viewpoint. Further, at the start of the second silicon etching step, it is preferable that the ratio D / L of the depth D and the width L of the concave portion formed in the etching target layer by etching is 1 or less.

Moreover, it is preferable that ratio (D / L) of the depth D and the width L of the said recessed part after completion | finish of a said 2nd silicon etching process is 1-50.

Moreover, it is preferable from a said 2nd viewpoint and a 3rd viewpoint that the said etching target layer is a silicon substrate or a silicon layer.

A fourth aspect of the present invention provides a control program that operates on a computer and controls the plasma processing apparatus such that, when executed, the plasma etching method of the second and third aspects is executed.

According to a fifth aspect of the present invention, in a computer-readable storage medium in which a control program operating on a computer is stored,

The control program provides a computer readable storage medium which, when executed, controls the plasma processing apparatus such that the plasma etching method of the second and third aspects is executed.

According to a sixth aspect of the present invention, there is provided a processing chamber for performing a plasma etching process on a target object;

A support for mounting a target object in the processing chamber;

Exhaust means for reducing the pressure inside the processing chamber;

Gas supply means for supplying a processing gas into the processing chamber;

And a controller for controlling the plasma etching method of the second and third aspects to be executed in the processing chamber.

Provided is a plasma processing apparatus.

EMBODIMENT OF THE INVENTION Hereinafter, the preferred form of this invention is described, referring drawings.

<1st embodiment>

1 is a flowchart showing an outline of a processing method according to a first embodiment of the present invention, and FIG. 2 is a semiconductor wafer (hereinafter, simply referred to as "wafer") to which the processing method of the first embodiment is applied (W). It is a figure which shows typically the cross-sectional structure of the to-be-processed object 110, such as). The workpiece 110 may be a SiO ₂ layer 102 is formed on the silicon substrate 101, and is provided with a resist 103, the pattern formed in advance thereon.

First, even for the object to be processed 110 in the condition of Figure 2, using the plasma etching apparatus 100 to be described later, according to the pattern of the resist 103, is etched SiO ₂ layer 102 (step S1). 3 shows the state after etching the SiO ₂ layer 102 until the surface of the silicon substrate 101 is exposed in the pattern opening. By etching, an opening 120 is formed in the SiO ₂ layer 102, and the silicon substrate 101 is exposed at the bottom thereof. In addition, with the etching of the SiO ₂ layer 102, the resist 103 is also shaved and consumed from the surface side thereof, and the film thickness thereof is reduced from To to T ₁ . The etching of the SiO ₂ layer 102 is performed by using a plasma etching apparatus 100 (see FIG. 8), which will be described later, as an etching gas, for example, a gas containing carbon fluoride compound (CxFy) that does not produce much deposits. This can be done using Ar / CF ₄ / O ₂ or Ar / C ₄ F ₈ / O ₂ .

FIG. 4 is a plasma etching apparatus 100 (FIG. 8) described below with respect to the object to be processed 110 shown in FIG. 3 using the resist 103 remaining on the SiO ₂ layer 120 as a mask. (See step S2; first silicon etching step) using the plasma generated using SF ₆ / O ₂ / SiF ₄ as the processing gas. The etching conditions at this time will be described later.

By silicon etching of the first silicon etching step, the silicon substrate 101 is recessed to a predetermined depth D ₁ having a width L corresponding to the pattern shape of the resist 103 as shown in FIG. 5. A portion (trench or hole) 121 is formed. This first silicon etching step is performed until the resist 103 on the SiO ₂ layer 102 is shaved and exhausted.

In this manner, by performing the silicon etching of the first silicon etching step as a mask on the resist 103 remaining on the SiO ₂ layer 102, deposits that become nuclei of the pits can be removed. That is, a 1st silicon etching process has a meaning as a deposit removal process. The deposits formed by the reaction product upon etching the SiO ₂ layer 102 and adhered on the resist 103 are removed during the first silicon etching process, and thus remain on the surface of the SiO ₂ layer 102. There is no work. Thereby, formation of a pit can be suppressed.

Subsequently to the first silicon etching step, as shown in FIG. 6, the silicon substrate (using a plasma generated using SF ₆ / O ₂ / SiF ₄ as the processing gas using the SiO ₂ layer 102 as an etching mask) 101 is etched (step S3; second silicon etching step). The etching conditions at this time will be described later.

2, the silicon substrate 101 by a silicon etching process, and is formed with a recess (trench or hole) 122 of the depth (D ₂₎ of interest as shown in Fig. In, adhered material removal process is also a first silicon etching step as described above, the formation of micro-trenches in the because the deposit is the core of the pits formed is removed from the surface SiO ₂ layer 102, a second silicon etch process And its growth can be suppressed to prevent the occurrence of pits.

The angle formed by the sidewall of the etching groove (the concave portion 122) with respect to the horizontal direction (hereinafter referred to as &quot; side wall angle &quot;) is approximately 90 °, so that the accuracy of the etching shape is secured.

Thus, by performing these two processes continuously, appropriately controlling the switching timing from a 1st silicon etching process to a 2nd silicon etching process, an etching shape can be made favorable, preventing formation of a pit. do. Here, the timing of the transition from the first silicon etching step to the second silicon etching step can be controlled according to, for example, the initial film thickness To of the resist 103. The initial film thickness To of the resist 103 is determined in consideration of the following matters.

First, the film thickness T ₁ of the resist 103 that must remain at the start of the first silicon etching process (after the etching of the SiO ₂ layer 102 is finished) has a process time of the first silicon etching process being SiO. _It should be set so as to have a sufficient time to remove the adhered adhering to the surface of the resist layer 103 by etching the _two layers 102. In addition, in order to remove a deposit by a 1st silicon etching process, since supply of carbon from the organic resist 103 plays an important role, it is necessary to remain a resist until removal of a deposit is completely performed. In a separate test conducted by the present inventors, the resist 103 was subjected to SF ₆ / O ₂ / SiF ₄ under the same conditions by taking time to etch the SiO ₂ layer 102 by approximately 100 nm. Etching with plasma has confirmed that deposits can be removed. This corresponds to about 300 nm in terms of the thickness of the resist 103 from the difference in etching rate. Therefore, it is preferable that the film thickness T ₁ of the resist 103 at the time of starting a 1st silicon etching process shall be 300 nm or more, for example.

On the other hand, if the film thickness T ₁ of the resist 103 is too thick, the time of the second silicon etching process performed by using the SiO ₂ film 102 as a mask is reduced (there is no second silicon etching process at the extreme), Since the resist 103 is etched as a mask as it is, it is difficult to control the shape of the recess 122, and the recess 122 may be formed in a boeing shape. Therefore, the film thickness of the resist 103, that is, the time of the first silicon etching process, sets the upper limit to a range that does not adversely affect the shape controllability of the recess 122 of the silicon substrate 101 finally formed. It is desirable to. In the knowledge of the present inventors, the resist mask (first silicon etching) is performed while the aspect ratio D ₁ / L of the recess 121 (see FIG. 5) formed by etching of the first silicon etching step is 1 or less. When switching to a SiO ₂ mask (second silicon etching step) in the step), it is considered that the influence on the etching shape hardly occurs. For example, in the recess 121 having a pattern of 5 μm width (L = 5 μm), the aperture ratio is also influenced, but since the etching rate of silicon by the gas system is considered to be about 5 to 15 μm / min, the depth is 5 μm (D _One = 5 mu m), the etching is required for 20 to 60 seconds. Considering this maximum time of 60 seconds, when the resist rate of the resist 103 is 1 µm / min, if the resist residual film is about 1 µm or less, the influence on the etching shape can be largely ignored. Therefore, it is preferable that the film thickness T ₁ of the resist 103 at the time of starting a 1st silicon etching process shall be ₁ micrometer or less, for example.

From the above, the residual thickness of the first resist 103 is required at the time of starting of the silicon etching step (T ₁₎ is preferably not more than 300nm at least 1μm (1000nm).

In addition, the film thickness (To) of the resist 103 in the beginning of the SiO ₂ layer etching process, considering the etching rate of the resist 103 in the SiO ₂ layer etching step, the first silicon etching step at the start of It is preferable to set the resist film thickness so that the remaining film thickness T ₁ of the resist 103 is within the above range.

Next, the present embodiment will be described in more detail with a magnetron RIE plasma etching apparatus as an example. FIG. 8: is sectional drawing which shows the magnetron RIE plasma etching apparatus 100 which can be used suitably in order to implement the 1st and 2nd silicon etching process in this embodiment. The plasma etching apparatus 100 is hermetically sealed and has an end-fitting cylindrical shape consisting of a small diameter upper portion 1a and a large diameter lower portion 1b, wherein the wall portion is made of, for example, an aluminum chamber (processing vessel). ) (1).

In this chamber 1, the support table 2 which horizontally supports the wafer W which is a single crystal Si substrate as a to-be-processed object is provided. The support table 2 is made of aluminum, for example, and is supported by the support 4 of the conductor via the insulating plate 3. In addition, a focus ring 5 formed of a material other than Si, such as quartz, is provided on the outer periphery above the support table 2. The support table 2 and the support stand 4 are capable of lifting up and down by a ball screw mechanism including the ball screw 7, and the driving portion below the support stand 4 is made of stainless steel (SUS) bellows. Covered with (8). The bellows cover 9 is provided outside the bellows 8. Moreover, the baffle plate 10 is provided in the outer side of the said focus ring 5, and is electrically conductive with the chamber 1 via this baffle plate 10, the support stand 4, and the bellows 8. The chamber 1 is grounded.

An exhaust port 11 is formed on the side wall of the lower portion 1b of the chamber 1, and an exhaust system 12 is connected to the exhaust port 11. By operating the vacuum pump of the exhaust system 12, the chamber 1 can be reduced in pressure to a predetermined degree of vacuum. On the other hand, at the upper side of the side wall of the lower part 1b of the chamber 1, the gate valve 13 which opens and closes the carrying-out opening of the wafer W is provided.

The high frequency power supply 15 for plasma formation is connected to the support table 2 via the matcher 14, and the high frequency power of predetermined frequency is supplied to the support table 2 from this high frequency power supply 15. It is. On the other hand, the shower head 20 which is demonstrated later in detail above and facing the support table 2 is provided in parallel with each other, and this shower head 20 is earth | grounded. Thus, the support table 2 and the showerhead 20 function as a pair of electrodes.

On the surface of the support table 2, an electrostatic chuck 6 for electrostatically holding and holding the wafer W is provided. The electrostatic chuck 6 is configured with an electrode 6a interposed between the insulators 6b, and a DC power supply 16 is connected to the electrode 6a. When the voltage is applied from the power supply 16 to the electrode 6a, the wafer W is attracted by the electrostatic force, for example, a coulomb force.

Inside the support table 2, a coolant chamber 17 is provided. In this coolant chamber 17, a coolant is introduced through the coolant inlet pipe 17a, discharged from the coolant discharge pipe 17b, and circulated. Cooling heat is conducted to the wafer W via the support table 2, whereby the processing surface of the wafer W is controlled to a desired temperature.

In addition, even if the chamber 1 is exhausted by the exhaust system 12 and maintained in a vacuum, the cooling gas is introduced into the gas so that the wafer W can be effectively cooled by the refrigerant circulated in the refrigerant chamber 17. It is introduced by the mechanism 18 between the surface of the electrostatic chuck 6 and the back surface of the wafer W via the gas supply line 19. By introducing the cooling gas in this way, the cooling heat of the refrigerant can be effectively transmitted to the wafer W, so that the cooling efficiency of the wafer W can be increased. As the cooling gas, for example, He can be used.

The shower head 20 is provided to face the support table 2 on the ceiling wall portion of the chamber 1. The shower head 20 is provided with a plurality of gas discharge holes 22 in the lower surface thereof, and has a gas introduction portion 20a thereon. A space 21 is formed therein. A gas supply pipe 23a is connected to the gas introduction portion 20a, and a processing gas supply system 23 for supplying a processing gas consisting of an etching gas and a dilution gas is provided at the other end of the gas supply pipe 23a. Connected.

Such processing gas reaches the space 21 of the shower head 20 from the processing gas supply system 23 via the gas supply pipe 23a and the gas introducing part 20a, and is discharged from the gas discharge hole 22. .

On the other hand, the dipole ring magnet 24 is disposed concentrically around the upper portion 1a of the chamber 1. As shown in a horizontal sectional view of FIG. 9, the dipole ring magnet 24 is configured by attaching a plurality of anisotropic segment columnar (column) magnets 31 to a casing 32 of a ring-shaped magnetic body. In this example, sixteen anisotropic segment columnar magnets 31 having a cylindrical shape are arranged in a ring shape. In FIG. 9, arrows in the anisotropic segment columnar magnet 31 indicate the direction of magnetization. As shown in this figure, the directions of magnetization of the plurality of anisotropic segment columnar stones 31 are shifted little by little, and the overall direction is one direction. A uniform horizontal magnetic field B directed toward is formed.

Therefore, in the space between the support table 2 and the shower head 20, the electric field EL in the vertical direction is formed by the high frequency power supply 15, as shown schematically in FIG. The horizontal magnetic field B is formed by the magnet 24, and the magnetron discharge is generated by the orthogonal electromagnetic field thus formed. As a result, plasma of the etching gas in a high energy state is formed, and the wafer W is etched.

Each component of the plasma etching apparatus 100 is configured to be connected to and controlled by a process controller 50 having a CPU. The process controller 50 includes a user interface including a keyboard for performing a command input operation or the like for the process manager to manage the plasma etching apparatus 100, or a display for visualizing and displaying the operation status of the plasma etching apparatus 100. 51 is connected.

The process controller 50 further includes a storage unit 52 which stores recipes in which control programs, processing condition data, and the like, for realizing various processes executed by the plasma etching apparatus 100 are controlled by the process controller 50. Is connected.

Then, if necessary, an arbitrary recipe is retrieved from the storage unit 52 by an instruction from the user interface 51 or the like and executed by the process controller 50, thereby controlling the plasma etching apparatus (under the control of the process controller 50). The desired processing in 100) is executed. The recipe may be stored in a computer-readable storage medium such as a CD-ROM, a hard disk, a flexible disk, or a flash memory, or may be frequently transmitted from another device via, for example, a dedicated line. It is also possible to use.

Next, the etching method of this invention which performs a plasma etching with respect to silicon (a single crystal silicon substrate or a polysilicon layer) using the plasma etching apparatus comprised in this way is demonstrated.

First, the gate valve 13 is opened, and the wafer W is loaded into the chamber 1, mounted on the support table 2, and then raised to the position showing the support table 2, and the exhaust system ( The chamber 1 is exhausted via the exhaust port 11 by the vacuum pump of 12).

Then, the processing gas containing the etching gas and the dilution gas is introduced into the chamber 1 from the processing gas supply system 23 at a predetermined flow rate, and the chamber 1 is at a predetermined pressure, and the high frequency power supply ( The predetermined high frequency electric power is supplied to the support table 2 from 15). At this time, the wafer W is adsorbed and held by the electrostatic chuck 6 by a coulomb force, for example, by applying a predetermined voltage from the DC power supply 16 to the electrode 6a of the electrostatic chuck 6. A high frequency electric field is formed between the showerhead 20 as the upper electrode and the support table 2 as the lower electrode. Since the horizontal magnetic field B is formed by the dipole ring magnet 24, an orthogonal electromagnetic field is formed in the processing space between the electrodes where the wafer W exists, and the magnetron discharge is generated by the drift of the electrons generated thereby. . The wafer W is etched by the plasma of the etching gas formed by the magnetron discharge.

As the etching gas, it is preferable to use a gas containing SF ₆ , O _2, and SiF ₄ . SF ₆ gas has a density of F atoms generated in the plasma in multiples of other fluorine-based gases, but since S atoms contained in SF ₆ have a movement to prevent oxidation of the Si surface and promote Si etching, they can be used appropriately for silicon etching. Can be.

In addition, the O ₂ gas reacts with silicon in the silicon substrate 101 to form a silicon oxide film (SiOx) on the sidewall, and there is a movement to promote anisotropic etching in the vertical direction.

In addition, since SiF ₄ dissociates in the plasma to generate Si in a gaseous state, the Si is O _2. By reacting with molecules and oxygen radicals, the silicon oxide film (SiOx) is deposited on the mask (SiO ₂ layer 102), and the sidewall protective film (SiOx) is enhanced to improve the mask selectivity and improve the side etching. It has the effect of inhibiting progression.

In order to improve the shape of the etching, it is also effective to adjust the temperature of the wafer W. Therefore, the refrigerant chamber 17 is provided, and the refrigerant | coolant circulates through this refrigerant chamber 17, and the cool heat is heat-conducted with respect to the wafer W through the support table 2, and the process of the wafer W is thereby performed. The face is controlled to the desired temperature.

The high frequency power supply 15 for plasma generation is suitably set in frequency and output in order to form a desired plasma. In silicon etching, it is preferable to set the frequency to 13.56 MHz or more from the viewpoint of increasing the plasma density immediately above the wafer W, for example.

The dipole ring magnet 24 applies a magnetic field to the processing space between the support table 2 and the showerhead 20, which are opposite electrodes, in order to increase the plasma density just above the wafer W, but the effect is effectively applied. In order to exert, it is preferable that the magnet has a strength sufficient to form a magnetic field of 10000 µT (100 G) or more in the processing space. The stronger the magnetic field is, the stronger the effect of increasing the plasma density is considered. However, from the viewpoint of safety, the magnetic field is preferably 100000 µT (1 kG) or less.

In addition, the plasma etching apparatus 100 can also be used when etching the SiO ₂ layer 102. In addition, although the plasma etching apparatus 100 can be used also for the plasma ashing for peeling the resist 103, you may perform ashing with the exclusive plasma ashing apparatus.

The preferable conditions at the time of performing each process from step S1 to step S3 using the plasma etching apparatus 100 are as follows.

First, as etching conditions in the SiO ₂ layer etching step of Step S1, for example, the flow rate of the processing gas is Ar = 0 to 1000 mL / min (sccm), CF ₄ = 1 to 100 mL / min (sccm), and O ₂ = 1 to 100 mL / min (sccm), the flow rate ratio is, for example, Ar / CF ₄ / O ₂ = 30/1/1, the processing pressure is 1.3 to 6.7 Pa (10 to 50 mTorr), and the high frequency frequency of the high frequency power supply 15 Is 13.56 MHz, the high frequency power is preferably 0.5 to 1 kW, the temperature of the wafer (W) is adjusted to about 0 to 60 ℃, for example.

The first silicon etching step of step S2 and the second silicon etching step of step S3 can be performed under the same conditions except that the etching masks are different.

In these silicon etchings, for example, the flow rate of the etching gas is SF ₆ = 1-1000 mL / min (sccm), O ₂ = 1-100 mL / min (sccm), SiF ₄ = 1-1000 mL / min (sccm) From the viewpoint of suppressing the formation of the undercut, the flow rate ratio is preferably about SF ₆ / O ₂ / SiF ₄ = 1/1/2.

The processing pressure is preferably set to 13.3 to 133.3 Pa (100 to 1000 mTorr) from the viewpoint of increasing the etchant density generated by dissociation of the etching gas.

In addition, from the viewpoint of increasing the dissociation degree of the etching gas, it is preferable that the high frequency power of the high frequency power supply 15 is 40 MHz, and the high frequency power is 1 to 3 kW (for a 200 mm diameter wafer).

Moreover, it is preferable to adjust the temperature of the wafer W to about -15-30 degreeC from a viewpoint of favorable control of an etching shape, ie, anisotropy.

Example 1

2-layer mask Si etching:

A feature having a SiO ₂ layer 102 and a resist layer 103 on a silicon substrate 101 using SF ₆ / O ₂ / SiF ₄ as an etching gas using the plasma etching apparatus 100 of FIG. 8. The silicon substrate 101 is successively subjected to the first silicon etching step using the resist 103 as a mask and the second silicon etching step using the SiO ₂ layer 102 as a mask for the liche (see FIG. 2). The recessed part 122 was formed.

Etching conditions are as follows.

Resist: film thickness = 1000 nm, resist material = organic resist material containing carbon, hydrogen and oxygen

SiO ₂ layer: film thickness = 2000 nm, CVD oxide film

SF ₆ / O ₂ / SiF ₄ Ratio = 150/80/400 mL / min (sccm)

Pressure = 24 Pa (180 mTorr)

RF frequency (high-frequency power (15)) = 40 MHz

RF power = 1500 W (4.77 W / cm ² )

Back pressure (center / edge) = 1333 Pa / 4000 Pa (10/30 Torr; He gas)

Distance between upper and lower electrodes = 37mm

Temperature (lower electrode / upper electrode / chamber sidewall) =-10 C / 60 C / 60 C

Etching Time = 375 Seconds (First Silicon Etching Process = 60 Seconds; Second Silicon Etching Process = 315 Seconds)

Comparative Example 1

Oxide Monolayer MaskSi Etching:

The recess 122 was formed in the silicon substrate 101 in the same manner as in Example 1 except that only a SiO ₂ layer (film thickness = 2000 nm) was used as a mask without using a resist mask.

Comparative Example 2

Resist Single Layer MaskSi Etching:

The object to be processed having the SiO ₂ layer 102 and the resist layer 103 on the silicon substrate by using the SF ₆ / O ₂ / SiF ₄ as an etching gas using the plasma etching apparatus 100 of FIG. 8 (FIG. 2), etching was performed using only the resist layer 103 as a mask to form a recess 122 in the silicon substrate. The etching conditions at this time are as follows.

Resist: film thickness = 5000 nm, resist material = organic resist material containing carbon, hydrogen and oxygen

SF ₆ / O ₂ / SiF ₄ ratio: It was changed as follows.

1) 300/80/0 mL / min (sccm); 5 minutes

2) 0/80/300 mL / min (sccm); 5 minutes

3) 300/80/0 mL / min (sccm); 4.5 minutes

Pressure = 13.3 Pa (100 mTorr)

RF frequency = 40 MHz (high-frequency power (15))

RF power = 500 W (1.59 W / cm ² )

Back pressure (center / edge) = 2666/2666 Pa (20/20 Torr; He gas)

Distance between upper and lower electrodes = 27 mm

Temperature (lower electrode / upper electrode / chamber sidewall) =-10 C / 60 C / 60 C

Etching Time = 900 sec

Table 1 shows the Si etching depth, the Si etching rate, the remaining thickness of the mask, the sidewall angle of the etching grooves (concave portion 122), and the pit generation conditions in Example 1 and Comparative Examples 1 and 2. In addition, the side wall angle and the pit generation | occurrence | production situation were evaluated by the imaging of a transmission electron microscope.

division Measurement item Center part Edge Example 1 Resist Mask + SiO ₂ Mask Etch Depth (μm) 31.80 37.80 Etch Rate (μm / min) 5.10 5.96 Mask Remaining (μm) 1.10 0.79 Sidewall Angle (°) 89.8 89.5 feet Does not occur Comparative Example 1 SiO ₂ Mask only Etch Depth (μm) 35.80 38.70 Etch Rate (μm / min) 5.73 6.21 Mask Remaining (μm) 0.81 0.62 Sidewall Angle (°) 90.0 89.5 feet Occur Comparative Example 2 Resist mask only Etch Depth (μm) 57.50 57.40 Etch Rate (μm / min) 4.00 4.00 Mask Remaining (μm) 1.40 2.31 Sidewall Angle (°) 88.3 88.0 feet Does not occur

As shown in Table 1, in Comparative Example 1 in which only the SiO ₂ layer 102 was used as a mask (oxide single layer mask), Si etching was performed, the sidewalls of the recesses 122 were approximately vertical, and the controllability of the etching shape Although excellent, pits occurred. In addition, in Comparative Example 2 in which only the resist 103 was used as a mask (resist single-layer mask), the etching conditions were different from those in Example 1 and Comparative Example 1, but a simple comparison could not be made. The side wall of 122) was inclined and formed in a boeing shape, and the etching shape was not controlled.

In contrast to the above, the embodiments subjected to a second silicon etch process using the first silicon etching step and, SiO ₂ layer 102 using the resist 103 as a mask as a mask continuously in Example 1 (two-layer mask), the recess The side wall of 122 was almost vertical, and was excellent in controllability of the etching shape, and no pits were observed. Therefore, it was confirmed that the suppression of the pit and the control of the etching shape can be made compatible by the two-step process combining the silicon etching of the resist mask and the silicon etching of the SiO ₂ mask.

<2nd embodiment>

Next, with reference to FIG. 11 and FIG. 12, the processing method which concerns on 2nd Embodiment of this invention is demonstrated. In the processing method of the first embodiment, the etching mask is changed from the resist 103 to the SiO ₂ layer 102 in the middle of etching by using a plasma of SF ₆ / O ₂ / SiF ₄ gas during silicon etching. Although the deposit which caused a pit was removed by this, in this 2nd Embodiment, in order to remove the deposit which causes a pit as shown in the flowchart of FIG. 11 and FIG. 12, the resist peeling process of peeling a resist mask is carried out. Thereafter, the surface etching treatment of the SiO ₂ layer 102 is performed as a deposit removal step.

First, in step S11, using the resist 103 as a mask, the SiO ₂ layer 102 is etched to form the recess 120. The process it is possible to the same manner as in step S1 of the SiO ₂ layer etching step of the processing method of the first embodiment, so that explanation thereof is omitted.

Next, in step S12, the resist is peeled off. Here, a resist peeling, for example, there may be employed any method such as a plasma ashing treatment by plasma of the wet process, O ₂ gas. After the resist is peeled off, the surface of the SiO ₂ layer 102 is exposed.

In step S13 after the resist peeling, the surface of the SiO ₂ layer 102 is slightly etched by the plasma of the etching gas as a deposit removing step. In other words, etching is performed so that the surface of the SiO ₂ layer 102 is thinly cut by an etching amount of about 100 nm by plasma. Here, it is preferable to use a fluorocarbon gas comprises difficult to generate a deposition Castle reaction product as an etching gas, such as Ar / CF ₄ / O ₂ or _{Ar / C 4 F 8 / O} 2.

SiO ₂ layer surface etching of step S13 which is a deposit removal process may be performed using the plasma etching apparatus 100 similar to FIG. 8, or another plasma etching apparatus may be used. The preferable conditions at the time of performing the etching of step S13 using the plasma etching apparatus 100 are as follows.

The flow rate of the processing gas is, for example, Ar = 0 to 1000 mL / min (sccm), C ₄ F ₈ = 1 to 100 mL / min (sccm), O ₂ = 1 to 100 mL / min (sccm), and the flow rate ratio is it is preferred that enough _{Ar / C 4 F 8 / O} 2 = 30/1/1.

The processing pressure is preferably set to 1.3 to 6.7 Pa (10 to 50 mTorr), for example.

It is preferable that the high frequency frequency of the high frequency power supply 15 is 13.56 MHz, and the high frequency power is 0.5-2 kW, for example.

It is preferable to adjust the temperature of the wafer W to about 0-60 degreeC, for example.

Next, in step S14, the silicon substrate 101 is etched using the SiO ₂ layer 102 as a mask by a plasma generated using SF ₆ / O ₂ / SiF ₄ as a processing gas to form the recess 122. . Since this silicon etching process can be performed similarly to the 2nd silicon etching process of step S3 in the processing method of 1st Embodiment, description is abbreviate | omitted here.

In this embodiment, by depositing the etching gas containing the carbon fluoride gas, the surface of the SiO ₂ layer 102 after the resist peeling can be etched to efficiently remove the deposits, and the silicon etching process is subsequently performed. It is possible to prevent the formation of pits at. The silicon etch process of step S14 is executed, because the SiO ₂ layer 102 as a mask, it is superior in control of the castle-like etching.

Third Embodiment

Next, with reference to FIG. 13 and FIG. 14, the processing method which concerns on 3rd Embodiment of this invention is demonstrated. In this embodiment, in order to remove the deposit which causes a pit, plasma ashing which peels a resist mask using plasma is performed, and carbon fluoride gas is added to the processing gas of plasma ashing, and it has an etching effect. By doing so, removal of a deposit is aimed at.

As shown in the flowchart of FIG. 13 and FIG. 14, in step S21, the SiO ₂ layer 102 is etched using the resist 103 as a mask to form the recess 120. This process will be omitted, since it is possible to describe the same manner as in SiO ₂ layer etching process in the step (S1) of the method of the first embodiment.

Next, in step S22, resist stripping and deposit removal are simultaneously performed using plasma. That is, the resist 103 is peeled off by the plasma of the ashing gas, and the surface of the SiO ₂ layer 102 is lightly etched. In this ashing, the resist is removed, and more preferably, the SiO ₂ layer 102 is thinned with an etching amount of about 100 nm. Here, it is preferable to use a gas containing a fluorocarbon compound, such as O ₂ / CF ₄ , O ₂ / C ₄ F _8, or the like, which is unlikely to generate a deposition reaction product as the processing gas. In addition, a rare gas such as Ar may be added to the processing gas.

Plasma ashing in step S22 for simultaneously performing resist stripping and deposit removal may be performed using the same plasma etching apparatus 100 as in FIG. 8, or a separate plasma ashing apparatus may be used. The preferable conditions at the time of performing plasma ashing of step S22 using the plasma etching apparatus 100 are as follows.

The flow rate of the processing gas is, for example, O ₂ = 100 to 1000 mL / min (sccm) and C ₄ F ₈ = 1 to 50 mL / min (sccm), and the flow rate ratio is O ₂ / C ₄ F ₈ = 10/1 It is preferable to make it to an extent.

The treatment pressure is preferably set to 6.7 to 133.3 Pa (50 to 1000 mTorr), for example.

It is preferable that the high frequency frequency of the high frequency power supply 15 is 13.56 MHz, and the high frequency power is 0.5-2 kW, for example.

It is preferable to adjust the temperature of the wafer W to about 0-60 degreeC, for example.

Next, in step S23, the recessed portion 122 is formed by etching the silicon substrate 101 using the SiO ₂ layer 102 as a mask by plasma generated using SF ₆ / O ₂ / SiF ₄ as the processing gas. . Since this process can be performed similarly to the 2nd silicon etching process of step S3 in the processing method of 1st Embodiment, description is abbreviate | omitted.

In the present embodiment, since the surface of the SiO ₂ layer 102 is lightly etched by using an ashing gas containing carbon fluoride gas, the resist is peeled off, and the etching effect of the added carbon fluoride gas is used. It becomes possible to remove, and can reliably prevent the formation of pits in a subsequent silicon etching process.

As described above, in the processing method according to the first to third embodiments of the present invention, it is possible to satisfactorily control the etching shape while preventing the formation of pits. In addition, by using SF ₆ / O ₂ / SiF ₄ as the etching gas, the aspect ratio D ₂ / L of the concave portion 122 (hole or trench) of 1 to 50 with respect to the silicon to be etched is used. Etc.) can be formed while preventing the high mask selectivity and undercut directly under the mask.

Therefore, the processing method of the present invention is, for example, in trench formation for deep trench isolation (DTI) for the purpose of device isolation, trench formation for memory cell capacitors, three-dimensional mounting devices and MEMS (Micro Electro Mechanical System). Can be suitably used for forming trenches for interlayer contacts.

As mentioned above, although embodiment of this invention was mentioned, various deformation | transformation are possible for this invention, without restrict | limiting to the said embodiment. For example, although the dipole ring magnet was used as the magnetic field forming means of the magnetron RIE plasma etching apparatus in the above embodiment, the formation of the magnetic field is not essential. In addition, as long as the plasma can be formed by the gas type of the present invention, various plasma etching apparatuses such as capacitive coupling type and inductive coupling type can be used regardless of the apparatus.

The present invention can be suitably used in the process of manufacturing various semiconductor devices such as transistors, for example.

According to the processing method of the present invention, by using SF ₆ / O ₂ / SiF ₄ as the etching gas, it is possible to precisely control the etching shape of the recess formed in the silicon while preventing the occurrence of pits during silicon etching. . In addition, by using the etching gas, it is possible to suppress the occurrence of the undercut which can be placed directly under the mask and to perform silicon etching at a high mask (silicon oxide film mask) selection ratio. Therefore, this processing method can be advantageously used for manufacturing highly reliable semiconductor devices, and can cope with miniaturization and high integration of design rules of semiconductor devices.

Claims (22)

A resist layer is used as a mask for an object to be treated having a silicon-based etching target layer, a silicon oxide layer formed on the etching target layer, and a patterned resist layer formed on the silicon oxide layer. A silicon oxide etching process of plasma etching the silicon oxide layer; A deposit removal step generated in the silicon oxide etching step to remove deposits adhered to the workpiece; And a silicon etching step of plasma etching the etching target layer using plasma generated from a processing gas containing SF ₆ , O _2, and SiF ₄ , using the silicon oxide layer as a mask. Treatment method. The method of claim 1, The deposit removal step is performed by using a plasma generated from a processing gas containing SF ₆ , O _2, and SiF ₄ , using the resist layer as a mask, before the silicon etching revolution for etching the etching target layer. The etching target layer is etched until the layer is cut.  Treatment method. The method of claim 1, The deposit removal step includes a resist stripping process for peeling the resist layer and a surface etching process for etching the surface of the silicon oxide layer after the resist stripping process.  Treatment method. The method of claim 1, The deposit removal step is to perform peeling of the resist layer and removal of deposits at the same time by plasma of a processing gas containing an O ₂ gas and a fluorocarbon gas.  Treatment method. The method of claim 4, wherein The fluorocarbon gas is CF ₄ gas or C ₄ F ₈ gas Treatment method. In the processing chamber of the plasma processing apparatus, with respect to the etching target layer mainly containing silicon, As a processing gas for generating plasma, plasma etching is performed using a processing gas containing SF ₆ , O _2, and SiF ₄ as a mask using a silicon oxide layer formed on the etching target layer and a resist layer formed on the silicon oxide layer as a mask. Performing a process to form a recess in the etching target layer; The plasma etching step includes a first silicon etching step of etching the etching target layer using the resist layer as a mask, and an etching step of etching the etching target layer using the silicon oxide layer as a mask after the resist layer has been scrapped. 2 silicon etching process, characterized in that  Plasma etching method. The method of claim 6, The film thickness of the said resist layer at the start of the said plasma etching process is 300 nm or more and 1 micrometer or less.  Plasma etching method. delete The method of claim 6, The ratio D / L of the depth D and the width L of the concave portion at the time when the resist layer is scraped is 1 or less  Plasma etching method. The method of claim 9, The ratio D / L of the depth D and the width L of the concave portion after the completion of the plasma etching step is 1 to 50.  Plasma etching method. delete The method of claim 6, In response to the opening width of the mask, the time of the first silicon etching process and the time of the second silicon etching process are distributed so that the sidewalls of the concave portions are formed vertically.  Plasma etching method. Generating a plasma from a processing gas containing SF ₆ , O _2, and SiF ₄ in a processing chamber of the plasma processing apparatus, A first silicon etching process provided on the etching target layer containing silicon as a main component through a silicon oxide layer, and etching the etching target layer by the plasma using a resist layer having a pattern formed in advance as a mask; A second silicon etching process of etching the etching target layer by the plasma using the silicon oxide layer as a mask after the resist layer is finished.  Plasma etching method. The method of claim 13, The film thickness of the said resist layer at the time of starting the said 1st silicon etching process is 300 nm or more and 1 micrometer or less.  Plasma etching method. The method according to any one of claims 13 to 14, At the start of the second silicon etching step, the ratio D / L of the depth D and the width L of the concave portion formed in the etching target layer by etching is 1 or less.  Plasma etching method. The method of claim 15, The ratio D / L of the depth D and the width L of the concave portion after the second silicon etching process is completed is 1 to 50.  Plasma etching method. The method of claim 13, The etching target layer is a silicon substrate or a silicon layer, Plasma etching method. delete In a computer-readable storage medium storing a control program running on a computer, The control program, when executed, controls the plasma processing apparatus such that the plasma etching method according to claim 13 is executed. Storage media. A processing chamber for performing plasma etching processing on the target object; A support for mounting a target object in the processing chamber; Exhaust means for reducing the pressure inside the processing chamber; Gas supply means for supplying a processing gas into the processing chamber; A control unit for controlling the plasma etching method according to claim 13 to be executed in the processing chamber. Plasma processing apparatus. The method of claim 6, Flow rate ratio of the processing gas is characterized in that SF ₆ / O ₂ / SiF ₄ = 1/1/2 Plasma etching method. The method of claim 13, Flow rate ratio of the processing gas is characterized in that SF ₆ / O ₂ / SiF ₄ = 1/1/2 Plasma etching method.

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