KR100872301B1 - Light emitting device and manufacturing method - Google Patents

Abstract

The present invention provides a first and a second semiconductor laminate having a first and a second conductivity type semiconductor layer and an active layer located therebetween, and the first and second contacts so as to be connected to the first and second conductivity type semiconductor layers, respectively. The first and second contacts respectively formed on opposite surfaces of the second semiconductor laminate, and the first and second surfaces disposed opposite to each other, and the first conductive semiconductor layer is exposed through the first surface. A substrate structure in which the first and second semiconductor laminates are separated from each other and embedded; a first insulating layer formed in a region other than the second contact formation region among the embedded surfaces of the first and second semiconductor laminates; And first and second conductive layers formed to be connected to second contacts of the second semiconductor laminate, respectively, and extending along the first insulating layer to have regions exposed on the first surface of the substrate structure. Is formed on the first side of the substrate structure, First and second wiring layers connecting the exposed regions of the first and second conductive layers and the first contacts of the second and first semiconductor laminates, respectively, and the first and second contacts of the first semiconductor laminate. A light emitting device including first and second external connection terminals formed to be electrically connected to each other is provided.

Description

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME}

1A and 1B are top plan views and side cross-sectional views, respectively, illustrating an example (horizontal electrode structure) of a zener diode integrated light emitting device according to an aspect of the present invention.

2A to 2F are cross-sectional views of processes for explaining a manufacturing process of the zener diode integrated light emitting device shown in FIGS. 1A and 1B.

3 is a side cross-sectional view showing another example (vertical electrode structure) of a zener diode-integrated light emitting device according to an aspect of the present invention.

4A to 4F are cross-sectional views of processes for explaining a manufacturing process of the zener diode integrated light emitting device shown in FIG.

5 is a side cross-sectional view showing an example of a light emitting device having a new bonding pad structure according to another aspect of the present invention.

6A through 6F are cross-sectional views illustrating processes of manufacturing the light emitting device illustrated in FIG. 5.

7A and 7B show a layout and an equivalent circuit diagram of a monolithic light emitting diode array, respectively, as a preferred application according to another aspect of the present invention.

8A to 8D are side cross-sectional views showing a wiring structure that can be employed in the monolithic light emitting diode array shown in Fig. 7A.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device and a method of manufacturing the same, and more particularly, to a light emitting device having various functions added by using an array and a wiring structure of a semiconductor laminate for a light emitting structure.

Since semiconductor light emitting diodes have advantageous advantages as light sources in terms of output, efficiency and reliability, they are being actively researched and developed as high power and high efficiency light sources that can replace backlights of lighting devices or display devices.

In general, a semiconductor light emitting device may be used in combination with a protective element such as a zener diode to prevent breakdown due to a voltage such as static electricity exceeding an allowable voltage. However, as the zener diode is additionally mounted, the required area may be increased and the structure may be complicated.

In particular, this problem can be exacerbated in LED arrays with complex wiring connections that can also drive AC voltage. That is, since a plurality of devices have a complicated structure in which an array is arranged, and complicated wiring connection for AC driving is required, it is difficult to install additional protection devices and may act as a barrier to realizing miniaturization. In addition, it is difficult to secure the position of the bonding pad for connection with an external circuit that requires a certain area.

SUMMARY OF THE INVENTION In order to solve the above problems of the prior art, an object of the present invention is to provide a light emitting device having a new wiring connection structure capable of integrating a protection device and a method of manufacturing the same.

Another object of the present invention is to provide a light emitting device having a bonding pad structure which can be usefully provided for complicated wiring connection structure and high integration, and a manufacturing method thereof.

In order to realize the above technical problem, the first aspect of the present invention,

First and second semiconductor laminates each having a first and a second conductivity type semiconductor layer and an active layer disposed therebetween, and the first and second semiconductors so as to be connected to the first and second conductivity type semiconductor layers, respectively. First and second contacts formed on opposite surfaces of the laminate, respectively, and first and second surfaces disposed opposite to each other, and the first conductive semiconductor layer is exposed through the first surface. A substrate structure in which a second semiconductor laminate is separated from each other and embedded; a first insulating layer formed in a region other than the second contact formation region among the buried surfaces of the first and second semiconductor laminates; First and second conductive layers formed to be respectively connected to the second contacts of the semiconductor laminate, the first and second conductive layers extending along the first insulating layer to have areas exposed to the first surface of the substrate structure, and the substrate structure. Is formed on a first side of the first And first and second wiring layers connecting the exposed region of the second conductive layer and the first contacts of the second and first semiconductor laminates, and the first and second contacts of the first semiconductor laminate, respectively. Provided is a light emitting device including first and second external connection terminals formed to be connected to each other.

In certain embodiments, the substrate structure may be made of a conductive material. In this case, the semiconductor substrate further includes a second insulating layer formed between the light emitting stack and the substrate structure such that the second contact and the first and second conductive layers are electrically insulated from the substrate structure. This conductive substrate structure may be a metal layer obtained from the plating process.

Alternatively, the substrate structure may be made of a material having electrical insulation.

Preferably, the first semiconductor laminate has a larger footprint on the substrate structure than the second semiconductor laminate.

In a preferred embodiment of the present invention, the first semiconductor laminate is plural, and the plurality of first semiconductor laminates may further include at least one wiring layer formed to be electrically connected to each other.

The at least one wiring layer may be a wiring layer connecting an exposed area of a conductive layer related to a specific first semiconductor laminate and a first contact related to another specific first semiconductor laminate. Alternatively, the at least one wiring layer may be a wiring layer connecting an exposed region of a conductive layer related to a specific first semiconductor laminate and an exposed region of a conductive layer related to another specific first semiconductor laminate.

The display device may further include a third insulating layer formed in a region where the wiring layer is to be formed among the first surfaces of the first and second semiconductor laminates.

Preferably, the plurality of semiconductor laminates may be electrically connected to each other by the additional wiring layer so that the corresponding active layer may emit light at an alternating voltage.

The present invention also provides a method of manufacturing a light emitting device according to the first aspect described above.

The manufacturing method includes the steps of forming a first and a second semiconductor laminate having a first and a second conductive semiconductor layer and an active layer located therebetween on a growth substrate, and forming an upper surface of the second conductive semiconductor layer. Forming a second contact in at least some regions, and forming a first insulating layer on the surfaces of the first and second semiconductor laminates except for the region in which the second contact is formed, and forming the first and second semiconductors. Forming first and second conductive layers formed to be connected to the second contacts of the laminate, respectively, and extending toward the upper surface of the growth substrate along the first insulating layer; Forming a substrate structure surrounding the first and second semiconductor laminates, and extending from the first and second semiconductor laminates and the substrate structure such that an extended region of the first and second conductive layers is partially exposed; Growth substrate Removing, forming a first contact on the exposed surfaces of the first and second semiconductor laminates so as to be connected to the first conductive semiconductor layer, and exposing the exposed areas of the first and second conductive layers and the Forming first and second wiring layers on exposed surfaces of the substrate structure such that first contacts of the second and first semiconductor laminates are connected respectively, and first and second contacts of the first semiconductor laminate; And forming the first and second external connection terminals to be electrically connected to the contact.

The forming of the second contact and the first insulating layer may include forming a first insulating layer in which a region in which the second contact is to be formed is opened, and forming the second contact in the open region. Can be run as.

Preferably, the first semiconductor laminate has a larger footprint on the substrate structure than the second semiconductor laminate.

Preferably, the forming of the first and second semiconductor laminates may include sequentially forming the first conductivity-type semiconductor layer, the active layer, and the second conductivity-type semiconductor layer on the growth substrate; Mesa etching may be performed to separate the separated layers into the first and second semiconductor laminates.

In a particular embodiment, the first insulating layer extends to an upper surface of a region between the first and second semiconductor laminates, and after separating the first and second semiconductor laminates, the first and second The method may further include removing the portion of the first insulating layer positioned between the two semiconductor stacks.

The mesa etching may be implemented in two types of methods depending on the etching depth.

In one embodiment, the growth substrate portion may be exposed in a region between the first and second semiconductor laminates. In this case, the forming of the conductive layer may include forming a conductive layer connected to the second contact and extending along the sides of the first and second semiconductor laminates to the exposed growth substrate portion. Can be.

In another aspect, the mesa etching may be performed such that at least a portion of the first conductivity type semiconductor layer remains in a region between the first and second semiconductor laminates. In this case, the forming of the conductive layer may include forming a conductive layer connected to the second contact and extending along the side surfaces of the first and second semiconductor laminates to the remaining first conductive semiconductor layer. It may be a step.

A second aspect of the present invention provides a first and a second semiconductor laminate having a first and a second conductivity type semiconductor layer and an active layer located therebetween, and the first and second conductive layers of the first semiconductor laminate, respectively. First and second contacts respectively formed on opposite surfaces of the first semiconductor laminate so as to be connected to the semiconductor semiconductor layer, respectively, and first and second surfaces positioned opposite to each other, and the first through the first surface. A substrate structure in which the first and second semiconductor laminates are separated from each other so as to expose a conductive semiconductor layer, and a region other than the second contact formation region and the second of the buried surfaces of the first semiconductor laminate; A conductive layer formed along the insulating layer formed on the buried surface of the semiconductor laminate and connected to the second contact of the first semiconductor laminate, the conductive layer extending along the insulating layer to have an area exposed on the first surface of the substrate structure; Layer, and the substrate sphere A wiring layer formed on the first surface of the structure and extending from an exposed area of the conductive layer of the first semiconductor laminate onto an exposed surface of the second semiconductor laminate, and a first contact of the first semiconductor laminate A light emitting device includes a first external connection terminal formed to be connected, and a second external connection terminal formed in an area of a wiring layer positioned on an exposed surface of the second semiconductor laminate.

The present invention provides a method of manufacturing a light emitting device according to the second aspect described above. The manufacturing method includes the steps of forming a first and a second semiconductor laminate having a first and a second conductive semiconductor layer and an active layer located therebetween on a growth substrate, and forming an upper surface of the second conductive semiconductor layer. Forming a second contact on at least a portion of the region, forming an insulating layer on a surface of the first semiconductor laminate except for the region where the second contact is formed, and connecting the second contact to the second contact of the first semiconductor laminate, respectively. Forming a conductive layer to extend toward the upper surface of the growth substrate along the insulating layer, and forming a substrate structure on the growth substrate to surround the first and second semiconductor laminates; Removing the growth substrate from the first and second semiconductor laminates and the substrate structure such that an extended region of the conductive layer is partially exposed to the first conductive semiconductor layer. Forming a first contact on an exposed surface of the first semiconductor laminate such that the first contact is connected to the exposed surface of the first semiconductor laminate; Forming first and second interconnection layers on the first interconnection layer; and forming the first and second external connection terminals to be connected to the first and second interconnection layers.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 1A is a top plan view illustrating an example (planner structure) of a zener diode integrated light emitting device according to an aspect of the present invention, and FIG. 1B is a side view of the zener diode integrated light emitting device shown in FIG. 1A taken along line XY. It is a cross section.

As shown in FIG. 1B together with FIG. 1A, the light emitting device 20 according to the present embodiment includes a semiconductor laminate having n-type and p-type semiconductor layers 12 and 17 and an active layer 15 positioned therebetween. 10 and a substrate structure 25 formed to surround the bottom and side surfaces of the semiconductor laminate 10. The semiconductor laminate 10 that can be employed in this embodiment can be composed of not only AlGaInN but also various known semiconductor materials such as AlGaAs, AlGaInP, ZnO.

In this embodiment, the semiconductor laminate 10 is divided into first and second semiconductor laminates 10A and 10B. The first and second semiconductor laminates 10A and 10B may be formed of the same semiconductor layer. By the wiring structure, the first semiconductor laminate 10A acts as the light emitting diode portion 20A, and the second semiconductor laminate 10B acts as a zener diode portion 20B.

Preferably, as shown in FIG. 1A, in order to secure an effective light emitting area relatively large, an area of the first semiconductor laminate 10A provided to the light emitting diode portion 20A is provided to the zener diode portion 20B. It can design larger than the area of the 2nd semiconductor laminated body 10B used.

First and second contacts 26 and 23 are formed on upper and lower surfaces of the first and second semiconductor laminates 10A and 10B so as to be connected to the n-type and p-type semiconductor layers 12 and 17, respectively. As described above, the first semiconductor laminate 10A acts as a light emitting diode. Since the light generated from the active layer 15 is emitted through the upper surface (n-type semiconductor layer 12) of the first semiconductor laminate 10A, the n-side contact so as to ensure effective light emission and uniform current distribution. Reference numeral 26 may be used an electrode material having a suitable structure or light transmissive. That is, as in the present embodiment, it is possible to have a structure that can ensure a more uniform current distribution over the entire light emitting area using the electrode finger.

The first insulating layer 22a is formed on regions and sides of the lower surfaces of the first and second semiconductor laminates 10A and 10B where the second contact 23 is not formed. The first insulating layer 22a may be a high resistance oxide or nitride such as SiO ₂ , Si ₃ N ₄ , AlN, Al ₂ O ₃ .

The light emitting device 10 includes first and second conductive layers 24a for drawing the p-side contacts 23 of the first and second semiconductor laminates 10A and 10B to the upper surface of the substrate structure 25, respectively. , 24b). The first and second conductive layers 24a and 24b are formed to extend from the p-side contact 23 to near the upper surface along side surfaces of the first and second semiconductor laminates 10A and 10B. The first and second conductive layers 24a and 24b may be electrically insulated from the first and second semiconductor laminates 10A and 10B by the first insulating layer 22a.

In the present embodiment, the substrate structure 25 may be made of a conductive material. Since such a conductive material generally has excellent thermal conductivity, it can be preferably employed as a substrate of the light emitting device 10. The substrate structure 25 may be a metal layer, and may be preferably formed by a plating process in order to easily obtain a sufficient thickness as a support.

Since the substrate structure 25 is electrically conductive, a second insulating layer 22b formed between the first and second semiconductor laminates 10A and 10B and the substrate structure 25 may be additionally provided. . The p-side contact 23 and the first and second conductive layers 24a and 24b of the first and second semiconductor laminates 10A and 10B are formed by the second insulating layer 22b to form the substrate structure 25. ) Can be electrically insulated.

Unlike the present embodiment, the substrate structure 25 may be a material having electrical insulation. In this case, the second insulating layer 22b may not be required.

As such, the p-side contact 23 embedded in the substrate structure 25 is formed in the electrode lead-out structure including the first and second conductive layers 24a and 24b and the first and second insulating layers 22a and 22b. By drawing out the upper surface of the substrate structure 25 can provide a wiring structure for connecting the contacts of both polarities on the same surface.

In this embodiment, an appropriate wiring structure is formed on the substrate structure 25 so that the first and second semiconductor laminates 10A and 10B can be driven by light emitting diodes and zener diodes, respectively. That is, as shown in FIG. 1B, the first wiring layer 27a connects the first conductive layer 24a and the n-side contact 26 of the second semiconductor laminate 10B. The second wiring layer 27b connects the second conductive layer 24b and the n-side contact 26 of the first semiconductor laminate 10A. As a result, the first and second semiconductor laminates 10A and 10B may be connected to each other in reverse polarity.

The light emitting device 20 includes first and second external connection terminals 28 and 29 formed to be electrically connected to the n-side and p-side contacts 26 and 23 of the first semiconductor laminate 10A, respectively. Include. In the present embodiment, the first and second external connection terminals 28 and 29 are formed on the n-side contact 26 of the first and second semiconductor laminates 10A and 10B, respectively. If necessary, the formation positions of the first and second external connection terminals 28 and 29 may be changed in various ways.

2A to 2G are cross-sectional views of processes for explaining a manufacturing process of the zener diode integrated light emitting device shown in FIGS. 1A and 1B.

First, as shown in FIG. 2A, first and second semiconductor stacks in which an n-type semiconductor layer 12, an active layer 15, and a p-type semiconductor layer 17 are sequentially stacked on a growth substrate 11 are formed. Sieves 10A and 10B are formed.

In the first and second semiconductor laminates 10A and 10B, the n-type semiconductor layer 12, the active layer 15, and the p-type semiconductor layer 17 are sequentially grown on the entire upper surface of the growth substrate 11. This can be obtained by applying a mesa etching process. The n and p-type semiconductor layers 12 and 17 and the active layer 15 may be made of various known semiconductor materials such as AlGaInN, AlGaAs, AlGaInP, and ZnO. In this embodiment, the mesa etching process is performed at a depth at which the growth substrate 11 is exposed to completely separate the epitaxial layer into a plurality of semiconductor laminates 10A and 10B.

As described above, it is preferable to design the area of the first semiconductor laminate 10A provided as the light emitting diode portion larger than the area of the second semiconductor laminate 10B provided as the zener diode portion (see FIG. 1A).

2B, a p-side contact 23 connected to the p-type conductive semiconductor layer 17 is formed on the first and second semiconductor laminates 10A and 10B, and the p-side contact ( The first insulating layer 22a is formed on the surfaces of the first and second semiconductor laminates 10A and 10B except 23.

In this step, after the insulator is deposited on the entire upper surface of the substrate 11 on which the first and second semiconductor laminates 10A and 10B are formed, the desired contact forming region is selectively removed, and the p-side contact is formed on the removed region. 23) can be implemented. The first insulating layer 22a may be a high resistance oxide or nitride such as SiO ₂ , Si ₃ N ₄ , AlN, and Al ₂ O ₃ .

In the present embodiment, not only the contact forming region but also the insulator portions around the first and second semiconductor laminates 10A and 10B are removed, but the first insulating layer 22a may be formed as necessary. It may extend to an upper surface area around the first and second semiconductor laminates 10A and 10B.

Next, as shown in FIG. 2C, the first and second parts connected to the p-side contact 23 and extended to the substrate 11 along side surfaces of the first and second semiconductor laminates 10A and 10B. 2 conductive layers 24a and 24b are formed.

The first and second conductive layers 24a and 24b are provided as lead structures for the p-side contacts 23 of the first and second semiconductor laminates 10A and 10B. More specifically, although the p-side contact 23 is buried by the substrate structure 25 in a subsequent process, the first and second conductive layers 24a and 24b connected to the p-side contact 23 may be formed of the substrate 11. Since the region may be exposed on the removed surface, wiring connection between the first and second semiconductor laminates 10A and 10B in the final structure may be easily realized.

Subsequently, as illustrated in FIG. 2D, a second insulating layer 22b may be formed on the surfaces of the first and second semiconductor laminates 10A and 10B.

The second insulating layer 22b electrically insulates the substrate structure (25 of FIG. 2E) and the first and second conductive layers 24a and 24b to be formed in a subsequent process. Therefore, the second insulating layer 22b is formed to cover at least the first and second conductive layers 24a and 24b and the p-side contact 23. Similar to the first insulating layer 22a, the second insulating layer 22b may be a high resistance oxide or nitride such as SiO ₂ , Si ₃ N ₄ , AlN, or Al ₂ O ₃ .

Since the second insulating layer 22b is required when the conductive material is used as the substrate structure 25, the process of forming the second insulating layer 22b when the substrate structure 25 is formed of a material having electrical insulation. May be omitted.

Next, as shown in FIG. 2E, the substrate structure 25 is formed on the upper surface of the growth substrate 11 to surround the first and second semiconductor laminates 10A and 10B, and the growth substrate is formed. The first and second semiconductor laminates 10A and 10B are separated from (11).

In this embodiment, the substrate structure 25 can be obtained by forming a seed layer (not shown) for the plating process on the second insulating layer 22b and then performing a plating process. The substrate structure 25 is illustrated as a metal material formed by a plating process, but is not limited thereto. As described above, the substrate structure 25 may be provided as an insulating substrate other than a conductive substrate such as a metal.

After the substrate structure 25 is formed, the growth substrate 10 is separated from the first and second semiconductor laminates 10A and 10B. As the separation process, a known process such as mechanical or mechanochemical polishing or chemical etching for removing the growth substrate 11 may be used, but preferably, a laser lift-off process may be performed. have.

Through this process, the first and second conductive layers 24a and 24b may have regions exposed at the surface from which the substrate 11 is removed. Exposed regions of the first and second conductive layers 24a and 24b may be provided as an external connection structure for the buried p-side contact 23.

2F, an n-side contact 26 is formed on exposed surfaces of the first and second semiconductor laminates 10A and 10B so as to be connected to the n-type semiconductor layer 12. First and second wiring layers 27a and 27b are formed to which the exposed regions of the first and second conductive layers 24a and 24b and the first contacts of the second and first semiconductor laminates 10A and 10B connect. .

This process corresponds to a process for the surface exposed by the separation of the growth substrate 11. The desired n-side contact 26 is formed on the first and second semiconductor laminates 10A and 10B so as to be connected to the n-type semiconductor layer 12. Subsequently, the first and second semiconductor laminates 10A and 10B connect the first and second semiconductor laminates 10A and 10B in reverse polarity so that the first and second semiconductor laminates 10A and 10B act as light emitting diode portions and zener diode portions, respectively. Wiring layers 27a and 27b are formed. That is, the first and second wiring layers 27a and 27b are exposed regions of the first and second conductive layers 24a and 24b and the n-side contacts of the second and first semiconductor laminates 10B and 10A, respectively. It is formed to connect the 26.

If necessary, before forming the first and second wiring layers 27a and 27b as in the present embodiment, the first and second semiconductor laminates 10A and 10B are formed on the first and second semiconductor laminates 10A and 10B in order to prevent connection. The process of forming the 3 insulating layers 22c can be performed further.

The above manufacturing process exemplifies a form (deep-mesa etching) in which the epitaxial layer is completely separated so that the etching process for forming the first and second semiconductor laminates is exposed to the growth substrate. Alternatively, the mesa etching process for the light emitting laminate may be implemented in such a manner as to leave some regions of the epitaxial layer.

In this case, it is possible to prevent the first and second conductive layers from being damaged in a separation process such as laser lift-off.

Unlike the above-described embodiment, the light emitting device and the method of manufacturing the same according to the present invention can be implemented in other forms. For example, in the above-described embodiment, the light emitting device is illustrated in a form having a horizontal electrode structure, but may be formed to have a vertical electrode structure.

On the other hand, the mesa etching process for obtaining a semiconductor laminate exemplified the deep etching process so that the upper surface of the substrate is exposed, otherwise shallow etching may be applied. This embodiment can be described with reference to other embodiments of the present invention shown in Figs. 3A and 3B.

3 is a side cross-sectional view showing another example (vertical electrode structure) of a zener diode integrated light emitting device according to an aspect of the present invention, which can be understood as a side cross-sectional view of a light emitting device having a structure similar to that of the top view shown in FIG.

As shown in Fig. 3, the light emitting device 40 according to the present embodiment includes a semiconductor laminate 30 having n and p-type semiconductor layers 32 and 37 and an active layer 35 disposed therebetween. And a substrate structure 45 formed to surround the bottom and side surfaces of the semiconductor laminate 30. The semiconductor laminate 30 employed in the present embodiment is divided into first and second semiconductor laminates 30A and 30B similarly to the previous embodiment. The semiconductor layers constituting the first and second semiconductor laminates 30A and 30B may be formed of the same layer, respectively.

By the wiring structure, the first semiconductor laminate 30A acts as the light emitting diode portion 40A, and the second semiconductor laminate 30B acts as a zener diode portion 40B. Preferably, in order to secure an effective light emitting area relatively large, the area of the first semiconductor laminate 30A provided to the light emitting diode portion 40A is provided to the zener diode portion 40B. It can be designed larger than the area of).

N-side and p-side contacts 46 and 43 are formed on the upper and lower surfaces of the first and second semiconductor laminates 30A and 30B so as to be connected to the n-type and p-type semiconductor layers 32 and 37, respectively. As described above, the first semiconductor laminate 30A functions as a light emitting diode. Since the light generated from the active layer 35 is emitted through the upper surface (n-type semiconductor layer 32) of the first semiconductor laminate 30A, the n-side is so as to ensure effective light emission and uniform current distribution The contact 46 may be an electrode material having a suitable structure or light transmissive. That is, as in the present embodiment, it is possible to have a structure that can ensure a more uniform current distribution over the entire light emitting area using the electrode finger.

The first insulating layer 42a is formed in the region and the side surface of the lower surfaces of the first and second semiconductor laminates 30A and 30B where the p-side contact 43 is not formed. The first insulating layer 42a may be a high resistance oxide or nitride such as SiO ₂ , Si ₃ N ₄ , AlN, Al ₂ O ₃ .

The light emitting device 40 includes first and second conductive layers 44a for drawing the p-side contacts 43 of the first and second semiconductor laminates 30A and 30B to the upper surface of the substrate structure 45, respectively. , 44b). The first and second conductive layers 44a and 44b are formed to extend from the p-side contact 43 to near the upper surface along side surfaces of the first and second semiconductor laminates 30A and 30B.

In the embodiment shown in FIG. 1B, the first and second conductive layers 24a, 24b extend to almost the same level as the exposed surfaces of the first and second semiconductor laminates 10A, 10B, whereas the present embodiment In this case, the extended regions of the first and second conductive layers 44a and 44b have lower levels than the exposed surfaces of the first and second semiconductor laminates 30A and 30B. This is a result of applying shallow etching in the mesa etching process for forming the first and second semiconductor laminates 30A and 30B, which will be described in detail with reference to FIGS. 4A to 4F.

In the present embodiment, the substrate structure 45 may be made of a conductive material. Since such a conductive material generally has excellent thermal conductivity, it can be preferably employed as a substrate of the light emitting device. The substrate structure 45 may be a metal layer, and may be preferably formed by a plating process in order to easily obtain a sufficient thickness as a support. When the substrate structure 45 is a conductive material, the light emitting device may have a vertical electrode structure as in the present embodiment.

In order to have such a vertical electrode structure, the second insulating layer 42b is formed only between the second semiconductor laminate 30B and the substrate structure 45. More specifically, the p-side contact 43 and the second conductive layer 44b of the second semiconductor laminate 30A are electrically insulated from the substrate structure 45 by the second insulating layer 42b. The p-side contact 43 of the first semiconductor laminate 30A may have a structure in which the p-side contact 43 is electrically connected to the bottom surface of the first semiconductor layer 30A through the conductive substrate structure 45 together with the first conductive layer 44a.

As such, the p-side contact 43 embedded in the substrate structure 45 is formed in the electrode lead-out structure including the first and second conductive layers 44a and 44b and the first and second insulating layers 42a and 42b. By drawing out the upper surface of the substrate structure 45 can provide a wiring structure for connecting the contacts of both polarities on the same surface.

In this embodiment, an appropriate wiring structure is formed on the substrate structure 45 so that the first and second semiconductor laminates 30A and 30B can be driven by light emitting diodes and zener diodes, respectively. That is, as shown in FIG. 3, the first wiring layer 47a connects the first conductive layer 44a and the n-type contact 46 of the second semiconductor laminate 30B. The second wiring layer 47b connects the second conductive layer 44b and the n-type contact 46 of the first semiconductor laminate 30A. As a result, the first and second semiconductor laminates 30A and 30B may be connected to each other in reverse polarity.

The light emitting device 40 includes first and second external connection terminals 48 and 49 formed to be electrically connected to the n-side and p-side contacts 46 and 43 of the first semiconductor laminate 30A, respectively. Include. In the present exemplary embodiment, the first and second external connection terminals 48 and 49 may be formed on the n-side contact 46 and the lower surface of the substrate structure 45 of the first semiconductor laminate 30A, respectively. .

4A to 4F are cross-sectional views of processes for explaining a manufacturing process of the zener diode integrated light emitting device shown in FIG.

First, as shown in FIG. 4A, first and second semiconductor stacks in which an n-type semiconductor layer 32, an active layer 35, and a p-type semiconductor layer 37 are sequentially stacked on a growth substrate 31 are formed. Sieves 30A and 30B are formed.

Similar to the previous embodiment, the n-type semiconductor layer 32, the active layer 35, and the p-type semiconductor layer 37 are sequentially grown on the entire upper surface of the growth substrate 31, and then a mesa etching process is applied. Can be realized. In this embodiment, however, shallow mesa etching is applied to leave a semiconductor laminate (particularly, the n-type semiconductor layer 32 region) of a constant thickness. Therefore, in the present process, the first and second semiconductor laminates 30A and 30B are not completely separated, but the remaining semiconductor layer can be easily removed by the laser lift-off or subsequent process. .

4B, a p-side contact 43 connected to the p-type semiconductor layer 37 is formed on upper surfaces of the first and second semiconductor laminates 30A and 30B, and the p-side contact 43 is formed. A first insulating layer 42a is formed on the surfaces of the first and second semiconductor laminates 30A and 30B except for the above.

In this step, after the insulator is deposited on the entire upper surface of the substrate 31 on which the first and second semiconductor laminates 30A and 30B are formed, the desired contact forming region is selectively removed, and the p-side contact is formed on the removed region. 43). The first insulating layer 42a may be a high resistance oxide or nitride such as SiO ₂ , Si ₃ N ₄ , AlN, and Al ₂ O ₃ .

Next, as shown in FIG. 4C, the first and second portions connected to the p-side contact 43 and extended to the substrate 31 along side surfaces of the first and second semiconductor laminates 30A and 30B. 2 conductive layers 44a and 44b are formed.

The first and second conductive layers 44a and 44b are provided as lead-out structures for the p-side contacts 43 of the first and second semiconductor laminates 30A and 30B. More specifically, although the p-side contact 43 is buried by the substrate structure 45 to be formed in a subsequent process, the first and second conductive layers 44a and 44b connected to the p-side contact 43 may be formed of a substrate ( Since 31) may have an exposed area on the removed surface, wiring connection between the first and second semiconductor laminates 30A and 30B in the final structure can be easily realized.

Subsequently, as shown in FIG. 4D, a second insulating layer 42b may be formed on the surfaces of the first and second semiconductor laminates 30A and 30B.

The second insulating layer 42b electrically insulates the substrate structure 45 of FIG. 4E and the second conductive layer 44b to be formed in a subsequent process. Therefore, the second insulating layer 42b is formed to cover the second conductive layer 44b and the p-side contact 43 of the second semiconductor laminate 30B. Similar to the first insulating layer 42a, the second insulating layer 42b may be a high resistance oxide or nitride such as SiO ₂ , Si ₃ N ₄ , AlN, or Al ₂ O ₃ .

Next, as illustrated in FIG. 4E, a conductive substrate structure 45 is formed on the upper surface of the growth substrate 31 to surround the first and second semiconductor laminates 30A and 30B, and the growth for The first and second semiconductor laminates 30A and 30B are separated from the substrate 31.

After the conductive substrate structure 45 is formed, the growth substrate 31 is separated from the first and second semiconductor laminates 10A and 10B. As such a separation process, a known process such as mechanical or mechanochemical polishing or chemical etching for removing the growth substrate 31 may be used, but preferably, may be performed by a laser lift-off process. have.

In particular, in the present embodiment, the semiconductor remaining between the first and second semiconductor laminates 30A and 30B is completely separated in the process of separating the growth substrate 31 or through an additional process thereafter. The layer is removed. Since the first and second conductive layers 44a and 44b are protected by the remaining epitaxial layer portions, the first and second conductive layers 44a and 44b can effectively prevent damages caused by mechanochemical or laser irradiation in the separation process.

In addition, the remaining epitaxial layer portions need to be removed together with a portion of the first insulating layer 42a to expose portions of the first and second conductive layers 44a and 44b. Preferably, spontaneous removal is preferably performed by laser irradiation or the like in a separation process. However, a portion of the first and second conductive layers 44a and 44b required for wiring connection may be exposed through an additional etching process as necessary. have.

Accordingly, the first and second conductive layers 44a and 44b may have regions exposed to a level slightly lower than the surface from which the substrate 31 is removed. Exposed areas of the first and second conductive layers 44a and 44b may be provided as an external connection structure for the buried p-side contact 43.

Next, as shown in FIG. 4F, an n-side contact 46 is formed on exposed surfaces of the first and second semiconductor laminates 30A and 30B so as to be connected to the n-type semiconductor layer 32. First and second wiring layers 47a and 47b connecting the exposed regions of the first and second conductive layers 44a and 44b and the n-type contacts 46 of the second and first semiconductor laminates 30A and 30B. To form.

This process corresponds to the process for the surface exposed by the separation of the growth substrate 31. The desired n-side contact 46 is formed on the first and second semiconductor laminates 30A and 30B so as to be connected to the n-type semiconductor layer 32.

Subsequently, the first and second semiconductor laminates 30A and 30B connect the first and second semiconductor laminates 30A and 30B in reverse polarity so that the first and second semiconductor laminates 30A and 30B act as light emitting diode portions and zener diode portions, respectively. The wiring layers 47a and 47b are formed. That is, the first and second wiring layers 47a and 47b are exposed regions of the first and second conductive layers 44a and 44b and the n-side contacts of the second and first semiconductor laminates 30B and 30A, respectively. It is formed to connect 46.

If necessary, before forming the first and second wiring layers 47a and 47b as in the present embodiment, the first and second semiconductor laminates 30A and 30B are formed on the first and second semiconductor laminates 30A and 30B in order to prevent connection. The process of forming the 3 insulating layers 42c can be performed further.

In the present embodiment, a first external connection terminal 48 is formed on the first contact 46 of the first semiconductor laminate 30A, and the second external connection terminal 49 is the substrate structure 45. Is formed on the lower surface of the As a result, a light emitting device having a desired vertical electrode structure can be realized. Here, the second external connection terminal 49 may be electrically connected to the second contact 43 of the first semiconductor laminate 30A through the conductive substrate structure 45.

By applying the semiconductor laminate structure and wiring structure similar to the above-described embodiment, it is possible to provide a bonding pad structure which can be usefully provided for complicated wiring connection structure and high integration. That is, another aspect of the present invention may provide a specific semiconductor laminate region as a structure for a bonding pad.

5 is a side sectional view showing an example of a light emitting device 60 having a new bonding pad structure according to another aspect of the present invention.

As shown in Fig. 5, the light emitting device 60 according to the present embodiment, similarly to the previous embodiment, has the first and second conductivity-type semiconductor layers 52 and 57 and the active layer 55 disposed therebetween. And first and second semiconductor laminates 50A and 50B having a structure and a substrate structure 65 formed to surround lower surfaces and side surfaces of the first and second semiconductor laminates 50A and 50B. The semiconductor layers constituting the first and second semiconductor laminates 50A and 50B may be formed of the same layer, respectively.

However, in the present embodiment, the first semiconductor laminate 50A is provided as a light emitting diode portion, and the second semiconductor laminate 50B provides a bonding pad region. Therefore, the area of the second semiconductor laminate 50B is limited to the area for the external connection structure, and it is preferable to design a large area of the first semiconductor laminate 50A to ensure a sufficient light emitting area. .

First and second contacts 66 and 63 are formed on the upper and lower surfaces of the first semiconductor laminate 50A provided as the light emitting diode so as to be connected to the first and second conductive semiconductor layers 52 and 57, respectively. . A first insulating layer 62a is formed on side and bottom surfaces of the first and second semiconductor laminates 50A and 50B to expose the second contact 63. The first insulating layer 62a may be a high resistance oxide or nitride such as SiO ₂ , Si ₃ N ₄ , AlN, and Al ₂ O ₃ .

In addition, the light emitting device 60 includes a conductive layer 64 for drawing out the second contact 63 of the first semiconductor laminate 50A to the top surface of the substrate structure 65, respectively. The conductive layer 64 is formed to extend from the second contact 63 to the vicinity of the upper surface along the side surface of the first semiconductor laminate 50A.

In the present embodiment, the substrate structure 65 may be made of a conductive material. Since such a conductive material generally has excellent thermal conductivity, it can be preferably employed as a substrate of the light emitting device 60. The substrate structure 65 may be a metal layer, and may be preferably formed by a plating process in order to easily obtain a sufficient thickness as a support.

Since the substrate structure 65 is electrically conductive, a second insulating layer 62b formed between the first and second semiconductor laminates 50A and 50B and the substrate structure 65 may be additionally provided. . The second contact 63 and the conductive layer 64 and the second semiconductor laminate 50B of the first semiconductor laminate 50A are electrically connected to the substrate structure 65 by the second insulating layer 62b. Can be insulated.

Alternatively, the substrate structure 65 may be considered a material having electrical insulation. In this case, the second insulating layer 62b may not be required.

The second contact 63 embedded in the substrate structure 65 has an upper surface of the substrate structure 65 by an electrode drawing structure including a conductive layer 64 and first and second insulating layers 62a and 62b. By drawing out, it is possible to provide a wiring structure for connecting the contacts of both polarities in the same plane. Here, the wiring layer 67 extends from the exposed area of the conductive layer 64 to the upper surface of the second semiconductor laminate 50B. The first external connection terminal 68 is formed to be electrically connected to the first contact 66 of the first semiconductor laminate 50A. In addition, the second external connection terminal 69 is formed in an area of the wiring layer 67 positioned on the exposed surface of the second semiconductor laminate 50B.

In the present embodiment, the conductive layer 64 is illustrated as extending to substantially the same level as the exposed surfaces of the first and second semiconductor laminates 50A and 50B, but as described with reference to FIGS. 3 and 4. The extended region of the conductive layer 64 may have a lower level than the exposed surface according to the kind of mesa etching process for separating the first and second semiconductor laminates 50A and 50B.

6A to 6F are cross-sectional views illustrating processes of manufacturing a light emitting device having the new bonding pad structure shown in FIG. 5.

First, as shown in FIG. 6A, first and second semiconductor stacks in which an n-type semiconductor layer 52, an active layer 55, and a p-type semiconductor layer 57 are sequentially stacked on a growth substrate 51 are formed. Sieves 50A and 50B are formed.

In the first and second semiconductor laminates 50A and 50B, the n-type semiconductor layer 52, the active layer 55, and the p-type semiconductor layer 57 are sequentially grown on the entire upper surface of the growth substrate 51. This can be obtained by applying a mesa etching process. The n and p-type semiconductor layers 52 and 57 and the active layer 55 may be formed of various known semiconductor materials such as AlGaInN, AlGaAs, AlGaInP, and ZnO. In this embodiment, the mesa etching process is performed to a depth at which the growth substrate 51 is exposed to completely separate the epitaxial layer into a plurality of semiconductor laminates 50A and 50B. Of course, this process may use shallow mesa etching, as described in Figure 4a.

6B, a p-side contact 63 connected to the p-type conductive semiconductor layer 57 is formed on the first and second semiconductor laminates 50A and 50B, and the p-side contact ( A first insulating layer 62a is formed on the surfaces of the first and second semiconductor laminates 50A and 50B except for 63.

In this step, after depositing an insulator on the entire upper surface of the substrate 51 on which the first and second semiconductor laminates 50A and 50B are formed, the desired contact forming region is selectively removed, and the p-side contact 63 is removed. Can be implemented by forming The first insulating layer 62a may be a high resistance oxide or nitride such as SiO ₂ , Si ₃ N ₄ , AlN, and Al ₂ O ₃ .

In the present embodiment, not only the contact forming region but also the insulator portions around the first and second semiconductor laminates 50A and 50B are removed, but the first insulating layer 62a may be formed as necessary. It may extend to an upper surface area around the first and second semiconductor laminates 50A and 50B.

Next, as shown in FIG. 6C, a conductive layer 64 connected to the p-side contact 63 and extending to the substrate 51 along the side surface of the first semiconductor laminate 50A is formed.

The conductive layer 64 is provided as a lead structure for the p-side contact 63 of the first semiconductor laminate 60A. More specifically, even though the p-side contact 63 is buried by the substrate structure 65 in a subsequent process, the conductive layer 64 connected to the p-side contact 63 may be exposed at the surface from which the substrate 51 is removed. It can have an area. Desired wiring connection can be easily implemented.

Subsequently, as illustrated in FIG. 6D, a second insulating layer 62b may be formed on the surfaces of the first and second semiconductor laminates 50A and 50B.

The second insulating layer 62b electrically insulates the substrate structure (65 of FIG. 6E) and the conductive layer 64 to be formed in a subsequent process. Therefore, the second insulating layer 62b is formed to cover at least the second conductive layer 64 and the p-side contact 63. Similar to the first insulating layer 62a, the second insulating layer 62b may be a high resistance oxide or nitride such as SiO ₂ , Si ₃ N ₄ , AlN, and Al ₂ O ₃ .

Next, as shown in FIG. 6E, a substrate structure 65 is formed on an upper surface of the growth substrate 51 to surround the first and second semiconductor stacks 50A and 50B, and the growth substrate is formed. The first and second semiconductor laminates 50A and 50B are separated from 51.

In this embodiment, the substrate structure 65 can be obtained by forming a seed layer (not shown) for the plating process on the second insulating layer 62b and then performing a plating process. The substrate structure 65 is illustrated as a metal material formed by a plating process, but is not limited thereto. As described above, the substrate structure 65 may be provided as an insulating substrate other than a conductive substrate such as a metal.

After the substrate structure 65 is formed, the growth substrate 51 is separated from the first and second semiconductor stacks 50A and 50B. As the separation process, a known process such as mechanical or mechanochemical polishing or chemical etching for removing the growth substrate 51 may be used, but a laser lift off process may be preferably used.

Through the substrate separation process, the conductive layer 64 may have an exposed area on the surface from which the substrate 51 is removed.

6F, an n-side contact 66 is formed on the exposed surface of the first semiconductor laminate 50A so as to be connected to the n-type semiconductor layer 62, and the conductive layer 64 The wiring layer 67 is formed to extend from the exposed region to the upper surface of the second semiconductor laminate 50B.

The desired n-side contact 66 is formed on the first semiconductor laminate 50A so as to be connected to the n-type semiconductor layer 52. Subsequently, the first external connection terminal 68 and the second electrical connection electrically connected to the first contact 66 of the first semiconductor laminate 50A such that the first semiconductor laminate 50A functions as a light emitting diode portion. The second external connection terminal 69 is formed in the region of the wiring layer 67 positioned on the exposed surface of the semiconductor laminate 50B.

If necessary, the third insulating layer 62c is disposed on the first and second semiconductor laminates 50A and 50B to prevent the connection with the undesired region before the wiring layer 67 is formed as in the present embodiment. The forming process can be further performed.

In the light emitting device according to the present embodiment, a sufficient area for the external connection region drawn out from the buried contact can be provided. This external connection structure can be very usefully applied as a bonding pad structure for external connection in a form in which a plurality of light emitting diodes, that is, a plurality of first semiconductor stacks are highly integrated.

The monolithic LED array proposed in the present invention can easily implement a complicated wiring connection between a plurality of LED cells by providing an external connection structure connected to both contacts on the same plane which is almost planar. In particular, a monolithic light emitting device connected to an AC voltage requires a complicated wiring structure in many cases. In this case the present invention can be applied very advantageously.

FIG. 7A is a layout of a monolithic light emitting diode array that may be implemented by the present invention, illustrating a form implemented according to the equivalent circuit shown in FIG. 7B.

The monolithic light emitting diode array according to the layout shown in FIG. 7A includes first and second LED cells A1 and A2 and third and fourth LED cells C1 and C2 formed on opposite sides of each other. Three fifth LED cells B1, B2, and B3 located therebetween are included.

Referring to Fig. 7B, the wiring structure of the monolithic light emitting diode array will be described.

The n-side contact of the first LED cell A1 and the p-side contact of the second LED cell A2 are connected to a first AC power supply terminal P1. The p-side contact of the third LED cell C1 and the n-side contact of the fourth LED cell C2 are connected to the second AC power supply terminal P2. The first and second AC power supply terminals P1 and P2 are regions provided as external connection terminals, and correspond to the second semiconductor laminate described with reference to FIG. 5. That is, the conductive layer extending from the n-side contact of the second LED cell A2 is drawn toward the semiconductor stack of the first AC power supply terminal P1, and the wiring layer connected to the drawn conductive layer is the first AC power source. It extends so that it may be located on the semiconductor laminated body of the stage P1. Similarly, a conductive layer extending from the n-side contact of the fourth LED cell C2 is drawn toward the semiconductor stack of the second AC power terminal P2, and the wiring layer connected to the extracted conductive layer is It extends so that it may be located on the semiconductor laminated body of 2nd AC power supply terminal P2. This will be described in more detail with reference to FIG. 8.

The three fifth LED cells B1, B2, and B3 have a structure connected in series with each other. The n-side contact of the fifth LED cell B1 located on one side, that is, located between the first and fourth LED cells A1 and C2, is the p-side of the first and fourth LED cells A1 and C2. The p-side contact of the fifth LED cell B3, which forms a common contact with the contact and is located on the other side, ie, located between the second and third LED cells A2 and C1, is the second and third LED cells. A common contact is formed with the n-side contact of (A2, C1).

In the LED array according to this layout, when an AC voltage is applied to the power terminals P1 and P2, the three fifth LED cells B1, B2, and B3 are always driven, and according to the cycle of the AC voltage. The first and third LED cells A1 and C1 and the second and fourth LED cells A2 and C2 may be driven alternately, and the three LED cells B1, B2, and B3 may be driven at full cycles. It can be driven continuously. As a result, driving of five LED cells can be guaranteed.

In addition, the layout of the monolithic light emitting diode array according to the present example has an advantage in terms of breakdown voltage. In consideration of the immunity of the breakdown voltage, it is more preferable to design such that the voltage applied to the LED cell is almost similar. This design can be effectively implemented by implementing each LED cell in about the same area. In addition, for this purpose, the number of the fifth LED cells can be appropriately adjusted. The preferred number of fifth LED cells can be considered in the range of 1 to 4.

The above-described monolithic LED array for AC has a complicated wiring structure, as shown in the layout of FIG. 7A, and thus it is difficult to implement monolithically. However, such a wiring structure can also be very easily implemented through the wiring structure proposed in the present invention. In addition, in a structure in which a plurality of LED cells are integrated, a required area for providing an external connection terminal connected to an AC power source can be ensured.

8A to 8D are side cross-sectional views of the monolithic light emitting diode array shown in FIG. 8A, respectively, cut into X1-X1 ', X2-X2', Y1-Y1 'and Y2-Y2'. However, in the present embodiment, with reference to the description of the various embodiments described above with respect to the mesa etching process and the extraction structure and the wiring structure forming the semiconductor laminate, it will be understood with reference to.

8A-8D, a substrate structure 116 is shown with three LED cells selected according to the cutting direction. The LED cell includes a semiconductor stack 110 having n-type and p-type semiconductor layers 112 and 117 and an active layer 115 disposed therebetween, and a substrate structure formed to surround the bottom and side surfaces of the semiconductor stack 110. 116.

Although not shown in part depending on the cutting direction, n and p-side contacts 126 and 123 connected to the n-type and p-type semiconductor layers 112 and 117 are formed on the top and bottom surfaces of the semiconductor laminate 110, respectively. . The first insulating layer 122a is formed on a region and a side surface of the lower surface of the semiconductor laminate 110 where the p-side contact 123 is not formed.

A conductive layer 124 connected to the p-side contact 123 and extending along the side surface of the semiconductor laminate 110 is formed. The conductive layer 124 may be electrically insulated from the semiconductor laminate 110 by the first insulating layer 122a.

First, referring to FIG. 8A, the conductive layer 124 provided to each of the LED cells A1 and C2 is extended by selecting a side adjacent to an object (another LED cell and contact type) to which the p-side contact is connected. That is, in the structure shown in FIG. 7A (that is, X1-X1 'of FIG. 7A), the conductive layers 124 of the first and fourth LED cells A1 and C2 are connected to the fifth LED cell B1. It may extend along adjacent sides.

The conductive layer 124 has an exposed area at a position adjacent to an upper surface of the semiconductor laminate 110 for wiring connection. The exposed areas of the conductive layers 124 of the first and fourth LED cells A1 and C2 are electrically connected to the n-side contact 126 of the fifth LED cell B1 by the wiring layer 127. do. As a result, the p-side contact 123 of the first and fourth LED cells A1 and C2 may have a common contact with the n-side contact 126 of the fifth LED cell B1 disposed therebetween.

Referring to FIG. 8B (a cutaway view in the X2-X2 'direction), the conductive layer 124 of the fifth LED cell B3 positioned between the second and third LED cells A2 and C1 may be formed by the second and third LED cells B3. It extends in two directions along side surfaces adjacent to the third LED cells A2 and C1 and has an exposed area at a position adjacent to the top surface of the semiconductor laminate 110 for wiring connection.

The exposed area of the conductive layer 124 of the fifth LED cell B3 is electrically connected to the n-side contact 126 of the second and third LED cells A2 and C1 by the wiring layer 127. do. Accordingly, the n-side contact 136 of the second and third LED cells A2 and C1 may have a common contact with the p-side contact 123 of the fifth LED cell B3 disposed therebetween.

Referring to FIG. 8C (a cutaway view in the Y1-Y1 'direction), a structure in which the three fifth LED cells B1, B2, and B3 are connected in series is shown. The conductive layers 124 of the fifth LED cells B1 and B2 extend to sides adjacent to the other fifth LED cells B2 and B3, respectively, and are adjacent to the top surface of the semiconductor stack 110 for wiring connection. Has an exposed area.

The exposed area of the conductive layer 124 of the fifth LED cells B1 and B2 is electrically connected to the n-side contact 126 of the other fifth LED cells B2 and B3 by the wiring layer 127. do. As a result, the three fifth LED cells B1, B2, and B3 may be connected in series.

As such, according to the position of the conductive layer 124 that leads the p-side contact 123 embedded in the substrate structure 116 and the wiring layer 127, a desired connection between the LED cells may be easily implemented. In particular, although described separately according to the cutting direction, each corresponding component is formed through the same process, it is possible to more effectively manufacture a monolithic light emitting diode array having a complicated wiring structure shown in Figure 7a.

Although not described in the above-described example, the third insulating layer 122c may be additionally formed according to the formation position of the wiring layer 127. The third insulating layer 122c mainly serves to protect the semiconductor stack 110 by preventing contact with an external element such as the wiring layer 127.

Referring to FIG. 8D (an incision in the Y2-Y2 'direction), there is shown a structure in which the first and second LED cells A1 and A2 and a first AC power terminal P1 region are disposed therebetween. . The conductive layer 124 of the second LED cell A2 is drawn toward the semiconductor stack of the first AC power supply terminal P1 and extends to the upper surface of the semiconductor stack of the first AC power supply terminal P1 by the wiring layer. do. In addition, the wiring layer extending from the n-side contact 126 of the second LED cell A2 extends on the upper surface of the semiconductor stack of the first AC power supply terminal P1. As a result, the semiconductor laminate region of the first AC power supply terminal P1 may have an appropriate wiring connection structure, and may provide a necessary area for an external connection terminal.

The monolithic light emitting diode array structure having a plurality of LED cells described in FIGS. 7 and 8 is similar to the zener diode integrated structure described in FIGS. 1 to 4 as well as the light emitting device structure for securing an external connection terminal region. Can be applied.

In this case, the first semiconductor stack is composed of a plurality, and the plurality of first semiconductor stacks further includes at least one wiring layer formed to electrically connect with each other similarly to the manner described in FIGS. 8A to 8C. do.

The at least one wiring layer may be a wiring layer connecting an exposed area of a conductive layer related to a specific first semiconductor laminate and a first contact related to another specific first semiconductor laminate. Alternatively, the at least one wiring layer may be a wiring layer connecting an exposed region of a conductive layer related to a specific first semiconductor laminate and an exposed region of a conductive layer related to another specific first semiconductor laminate. It may be a combination for the wiring layer of this structure. By the additional wiring layer, the plurality of first semiconductor laminates may be electrically connected to each other so that the corresponding active layers may emit light at an alternating voltage. If necessary, the semiconductor device may further include a third insulating layer formed in a region where the wiring layer is to be formed among the first surfaces of the first and second semiconductor laminates.

As such, the present invention is not limited by the above-described embodiments and the accompanying drawings, and is intended to be limited by the appended claims, and various forms of substitution may be made without departing from the technical spirit of the present invention described in the claims. It will be apparent to one of ordinary skill in the art that modifications, variations and variations are possible.

As described above, according to the present invention, it is possible to provide a light emitting device having a new wiring connection structure in which a protection element can be integrated by drawing one contact embedded in a substrate structure through a conductive layer, and a method of manufacturing the same. In addition, the present invention can provide a light emitting device having a complicated wiring connection structure and a bonding pad structure which can be usefully provided for high integration, and a manufacturing method thereof. Such a wiring based structure can be very usefully employed in AC voltage driven LED arrays.

Claims (38)

First and second semiconductor laminates each having a first and a second conductivity type semiconductor layer and an active layer positioned therebetween; First and second contacts respectively formed on opposite surfaces of the first and second semiconductor laminates so as to be connected to the first and second conductive semiconductor layers, respectively; A substrate structure having first and second surfaces disposed opposite to each other, and having the first and second semiconductor laminates separated from each other and embedded to expose the first conductive semiconductor layer through the first surface; A first insulating layer formed on a region of the buried surfaces of the first and second semiconductor laminates except for the second contact formation region; First and second conductive layers formed to be connected to second contacts of the first and second semiconductor laminates, respectively, and extending along the first insulating layer to have regions exposed on the first surface of the substrate structure, respectively. ; First and second electrodes formed on a first surface of the substrate structure and connecting exposed regions of conductive layers related to the first and second semiconductor laminates and first contacts of the second and first semiconductor laminates, respectively; Wiring layer; And And a first and second external connection terminals configured to be electrically connected to first and second contacts of the first semiconductor laminate, respectively. The method of claim 1, The substrate structure is made of a conductive material, And a second insulating layer formed between the second semiconductor laminate and the substrate structure such that the second contact of the second semiconductor laminate is electrically insulated from the substrate structure. The method of claim 2, And the first external connection terminal is formed on a first contact of the first semiconductor laminate, and the second external connection terminal is formed on a second surface of the substrate structure. The method of claim 1, The substrate structure is made of a conductive material, And a second insulating layer formed between the first and second semiconductor laminates and the substrate structure such that the second contacts of the first and second semiconductor laminates are electrically insulated from the substrate structure. Light emitting device. The method of claim 4, wherein And the first external connection terminal is formed on a first contact of the first semiconductor laminate, and the second external connection terminal is formed on a first contact of the second semiconductor laminate. The method according to claim 2 or 4, And said substrate structure is a metal layer obtained from a plating process. The method of claim 1, And the substrate structure is made of a material having electrical insulation. The method of claim 1, And the first semiconductor laminate has a larger occupied area on the substrate structure than the second semiconductor laminate. The method of claim 1, The exposed area of the first and second conductive layers is located at the same level as the exposed surface of the first and second semiconductor laminate. The method according to claim 1 or 7, And the exposed area of the conductive layer is located at a level lower than the exposed surfaces of the first and second semiconductor laminates. The method of claim 1, The first semiconductor laminate is a plurality, The plurality of first semiconductor laminates further comprise at least one wiring layer formed to be electrically connected to each other. The method of claim 11, And the at least one wiring layer comprises a wiring layer connecting an exposed region of a specific first conductive layer and a first contact related to another specific first semiconductor laminate. The method of claim 11, And the at least one wiring layer comprises a wiring layer connecting an exposed region of a specific first conductive layer and an exposed region of another first conductive layer. The method of claim 11, And a third insulating layer formed in a region in which the wiring layer is to be formed among the first surfaces of the first and second semiconductor laminates. The method of claim 11, And the plurality of semiconductor laminates are electrically connected to each other by the additional wiring layer so that the corresponding active layers can emit light at an alternating voltage. Forming first and second semiconductor laminates having first and second conductivity-type semiconductor layers and an active layer disposed therebetween on the growth substrate; Forming a second contact on at least a portion of the upper surface of the second conductive semiconductor layer, and forming a first insulating layer on the surfaces of the first and second semiconductor laminates except for the region where the second contact is formed. ; Forming first and second conductive layers formed to be connected to second contacts of the first and second semiconductor laminates, respectively, and extending toward an upper surface of the growth substrate along the first insulating layer; Forming a substrate structure surrounding the first and second semiconductor laminates on the growth substrate; Removing the growth substrate from the first and second semiconductor laminates and the substrate structure such that an extended region of the first and second conductive layers is partially exposed; Forming a first contact on exposed surfaces of the first and second semiconductor laminates so as to be connected to the first conductive semiconductor layer; Forming first and second wiring layers on exposed surfaces of the substrate structure such that the first and second conductive layer exposed regions and the first contacts of the second and first semiconductor laminates are respectively connected; And And forming first and second external connection terminals to be electrically connected to first and second contacts of the first semiconductor laminate, respectively. The method of claim 16, The substrate structure is made of a conductive material, And forming a second insulating layer on the surfaces of the first and second semiconductor laminates between the first and second conductive layer forming steps and the substrate structure forming step. Way. The method of claim 17, Forming the first and second external connection terminals, And forming the first and second external connection terminals on the first contact of the first semiconductor laminate and the second surface of the substrate structure, respectively. The method of claim 16, The substrate structure is made of a conductive material, Further comprising forming a second insulating layer on the surfaces of the first and second semiconductor laminates between the first and second conductive layer forming steps and the substrate structure forming step. Manufacturing method. The method of claim 19, Forming the first and second external connection terminals, And forming the first and second external connection terminals on the first contacts of the first and second semiconductor laminates. The method of claim 17 or 20, The forming of the substrate structure is performed by a plating process. The method of claim 16, And the substrate structure is made of a material having electrical insulation. The method of claim 16, Forming the second contact and the first insulating layer, And forming a first insulating layer in which an area in which the second contact is to be formed is opened, and forming the second contact in the open area. The method of claim 16, And the first semiconductor laminate has a larger occupied area on the substrate structure than the second semiconductor laminate. The method of claim 16, Forming the first and second semiconductor laminates, Sequentially forming the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer on the growth substrate, and mesa etching to separate the grown layers into the first and second semiconductor laminates. Light emitting device manufacturing method comprising the step of performing. The method of claim 25, The first insulating layer extends to an upper surface of a region between the first and second semiconductor laminates, And after removing the first and second semiconductor laminates, removing the first insulating layer portion located between the first and second semiconductor laminates. The method of claim 25, And the mesa etching is performed to expose the growth substrate portion in a region between the first and second semiconductor laminates. The method of claim 27, Forming the first and second conductive layers, And forming a conductive layer connected to the second contact and extending along the side surfaces of the first and second semiconductor laminates to the exposed growth substrate portion. The method of claim 25, And the mesa etching is performed such that at least a part of the first conductivity-type semiconductor layer remains in a region between the first and second semiconductor laminates. The method of claim 29, Forming the first and second conductive layers, And forming a conductive layer connected to the second contact and extending along the side surfaces of the first and second semiconductor laminates to the remaining first conductive semiconductor layer. The method of claim 16, The first semiconductor laminate is a plurality, Forming the first and second semiconductor laminates, Sequentially forming the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer on the growth substrate, wherein the grown layers are formed of the plurality of first semiconductor laminates and the second semiconductor stack. Light-emitting device comprising the step of performing a mesa etching so as to separate the sieve. The method of claim 31, wherein The forming of the first and second wiring layers may further include forming at least one additional wiring layer such that the plurality of first semiconductor laminates are electrically connected to each other. 33. The method of claim 32, Wherein the at least one additional wiring layer comprises a wiring layer connecting the exposed portion of the conductive layer associated with the particular first semiconductor laminate and the first contact associated with another specific first semiconductor layer laminate. Light emitting device manufacturing method. 33. The method of claim 32, The at least one additional wiring layer comprises an additional wiring layer connecting an exposed portion of the conductive layer associated with a particular first semiconductor laminate and an exposed region of the conductive layer relating to another particular first semiconductor laminate. Light emitting device manufacturing method characterized in that. 33. The method of claim 32, And the plurality of first semiconductor laminates are electrically connected to each other by the additional wiring layer so that the corresponding active layers can emit light at an alternating voltage. The method of claim 16, Before forming the first and second wiring layers, further comprising forming a third insulating layer on an area of the exposed surfaces of the first and second semiconductor laminates in which the first and second wiring layers are to be formed. Light emitting device manufacturing method characterized in that. First and second semiconductor laminates each having a first and a second conductivity type semiconductor layer and an active layer positioned therebetween; First and second contacts respectively formed on opposite surfaces of the first semiconductor laminate so as to be connected to the first and second conductivity-type semiconductor layers of the first semiconductor laminate, respectively; A substrate structure having first and second surfaces disposed opposite to each other, and having the first and second semiconductor laminates separated from each other and embedded to expose the first conductive semiconductor layer through the first surface; An insulating layer formed on a region of the buried surface of the first semiconductor laminate except for the second contact forming region and a buried surface of the second semiconductor laminate; A conductive layer formed to be connected to a second contact of the first semiconductor laminate, the conductive layer extending along the insulating layer to have an area exposed on the first surface of the substrate structure; A wiring layer formed on a first surface of the substrate structure and extending from an exposed area of the conductive layer of the first semiconductor laminate onto an exposed surface of the second semiconductor laminate; A first external connection terminal formed to be electrically connected to a first contact of the first semiconductor laminate; And And a second external connection terminal formed in a wiring layer region on an exposed surface of the second semiconductor laminate. Forming first and second semiconductor laminates having first and second conductivity-type semiconductor layers and an active layer disposed therebetween on the growth substrate; Forming a second contact on at least a portion of an upper surface of the second conductive semiconductor layer, and forming an insulating layer on a surface of the first semiconductor laminate except for a region where the second contact is formed; Forming a conductive layer formed to be connected to each of the second contacts of the first semiconductor laminate, and extending along the insulating layer toward the upper surface of the growth substrate; Forming a substrate structure surrounding the first and second semiconductor laminates on the growth substrate; Removing the growth substrate from the first and second semiconductor laminates and the substrate structure such that an extended region of the conductive layer is partially exposed; Forming a first contact on an exposed surface of the first semiconductor laminate to be connected to the first conductive semiconductor layer; Forming a wiring layer on the exposed surface of the substrate structure to extend from the exposed area of the conductive layer to the exposed surface of the second semiconductor laminate; And Forming a first external connection terminal to be electrically connected to a first contact of the first semiconductor laminate, and forming a second external connection terminal in a wiring layer region located on an exposed surface of the second semiconductor laminate. Method of manufacturing a light emitting device.

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