KR100810475B1 - Electro-optical device, and electronic device provided with the same - Google Patents

Abstract

assignment

For example, in an electro-optical device such as a liquid crystal device, for example, the substrate size can be reduced, and the influence of noise in the image signal can be suppressed to enable high quality image display.

Resolution

The electro-optical device includes, on a substrate, a plurality of pixels formed in a pixel region and a peripheral circuit for controlling a plurality of pixels formed in a peripheral region located around the pixel region. Further, different types of signals are supplied from among a plurality of types of signals for controlling peripheral circuits, respectively, and are formed of different conductive films among a plurality of conductive films positioned on different layers via an interlayer insulating film, and at least in the peripheral region. A plurality of signal wires having a portion overlapping with each other and a shield film positioned between portions overlapping each other on a substrate of the plurality of signal wires are provided.

Electro-optical Device, Sealed Membrane

Description

Electro-optical device, and electronic device provided with this {{ELCTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS HAVING THE SAME}

BRIEF DESCRIPTION OF THE DRAWINGS The top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment of this invention.

FIG. 2 is a sectional view taken along line H-H 'of FIG. 1; FIG.

3 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels constituting an image display area.

4 is a plan view showing a partial configuration related to a pixel on a TFT array substrate, which corresponds to a lower layer portion (lower layer portion up to symbol 6a (data line) in FIG. 6) in a laminated structure.

FIG. 5 is a plan view showing a partial configuration related to a pixel on a TFT array substrate, and corresponds to an upper layer portion (an upper layer portion beyond the symbol 6a (data line) in FIG. 6) in the laminated structure. FIG.

FIG. 6 is a cross-sectional view along the line A-A 'in the case of overlapping FIGS. 4 and 5. FIG.

7 is an explanatory diagram showing a circuit configuration related to a data line driving circuit and a sampling circuit, and an electrical connection relationship by signal wiring and the like.

FIG. 8 is a circuit diagram showing a circuit system related to shaping of transmission signals in the configuration shown in FIG. 7; FIG.

FIG. 9 is a cross-sectional view taken along the line BB ′ in FIG. 7. FIG.

FIG. 10 is a sectional view of the same effect as FIG. 9 in a first modification. FIG.

11 is a sectional view of the same effect as FIG. 9 in a second modification.

12 is a layout diagram of image signal lines and branch wirings;

FIG. 13 is a sectional view taken along the line D-D 'in FIG. 12; FIG.

14 is a layout diagram of signal wiring around the external circuit connection terminal;

FIG. 15 is a sectional view taken along the line D-D 'in FIG. 14; FIG.

FIG. 16 is a sectional view taken along the line E-E 'in FIG. 14; FIG.

17 is a cross-sectional view taken along the line FF 'in FIG. 14;

FIG. 18 is a sectional view of the same effect as FIG. 6 in the second embodiment; FIG.

19 is a plan view showing the configuration of a projector which is an example of an electronic apparatus to which an electro-optical device is applied.

20 is a perspective view showing a configuration of a personal computer which is an example of an electronic apparatus to which an electro-optical device is applied.

Fig. 21 is a perspective view showing the structure of a cellular phone which is an example of an electronic apparatus to which an electro-optical device is applied.

* Description of Major Symbols in Drawings *

9a: pixel electrode 6a: data line

7: sampling circuit 7s: sampling switch

10 TFT array substrate 10a image display area

11a: scanning line 20: opposing substrate

21: counter electrode 41, 42, 43: interlayer insulating film

50 liquid crystal layer 75 dielectric film

90: signal wiring 91: image signal line

92: enable signal lines 95, 95d, 95s: power supply wiring

101: data line driving circuit

102, 102c, 102d, 102e: External circuit connection terminal

104: scan line driver circuits VID1 to VID6: image signals

ENB1 to ENB4: Enable Signal

TECHNICAL FIELD This invention relates to the technical field of electronic devices, such as a liquid crystal projector, provided with electro-optical devices, such as a liquid crystal device, and this electro-optical device, for example.

In this type of electro-optical device, a plurality of external circuits are connected along an edge of one side on a display electrode such as a pixel electrode or a circuit portion such as a data line driving circuit or a scanning line driving circuit for driving the same. The terminals are arranged. On the board | substrate, several signal wiring for supplying several types of signals to circuit parts, such as a scanning line drive circuit and a data line drive circuit, is wired from these some external circuit connection terminals.

Regarding such signal wiring, for example, in Patent Literature 1, in addition to the original wiring, additional wiring is formed from the same film as the conductive film in the pixel, that is, the redundant wiring structure does not increase the number of steps. Research has been conducted to reduce wiring resistance.

[Patent Document 1] Japanese Unexamined Patent Publication No. 2002-229061

However, with respect to signal wirings to which signals of different types are supplied, they are arranged so that they do not overlap in plan view on the substrate, so that the intervals of the signal wirings adjacent to each other in the same plane are beyond the limit of patterning miniaturization. Can't narrow in For this reason, in order to reduce the area required for laying out the signal wiring, there is an inherent limitation, and there is a problem that it becomes a disadvantage of miniaturization of the electro-optical device. Further, for example, with the miniaturization of the electro-optical device, there is a problem that the interval between signal wirings is narrowed, thereby increasing the interference between different kinds of signals supplied to adjacent wirings. In particular, there is a problem that noise occurs in an image signal due to a clock signal having a high frequency for operating a data line driving circuit or the like.

This invention is made | formed in view of the above-mentioned problem, for example, For example, board | substrate size can be reduced, and also the influence of the noise in an image signal can be suppressed, and high quality image display is possible. It is an object of the present invention to provide an electro-optical device and an electronic device.

Means to solve the problem

In order to solve the said subject, the electro-optical device of this invention is a peripheral circuit for controlling the some pixel formed in the pixel area on the board | substrate, and the peripheral area located in the periphery of the said pixel area. And a plurality of different types of signals for controlling the peripheral circuits, respectively, and are formed of each of a plurality of conductive films positioned in different layers via an interlayer insulating film, and at least partially in the peripheral region. And a plurality of signal wires having portions overlapping each other, and a shield film positioned between portions of the plurality of signal wires overlapping each other.

According to the electro-optical device of the present invention, at the time of its operation, for example, an image signal, a clock signal, various control signals, a power supply signal, and the like are output from a plurality of signals through an external circuit connection terminal, for example. Supplied to wiring and peripheral circuits. The plurality of signal wires and the peripheral circuits are formed in peripheral regions located around the pixel regions on the substrate. The term "peripheral circuit" according to the present invention refers to, for example, made or mounted on a substrate such as a scan line driver circuit or a data line driver circuit for controlling or driving a scan line or a data line electrically connected to a pixel. It means various circuits. For example, an image signal is supplied to each pixel via the data line by the data line driver circuit. In addition, a scan signal is supplied to each pixel via a scan line by a scan line driver circuit. For example, in a pixel switching thin film transistor (hereinafter, appropriately referred to as a "pixel switching TFT") formed for each pixel, a gate is connected to a scanning line, and selectively supplies an image signal to a pixel electrode in accordance with a scanning signal. do. By these, for example, an active matrix drive is possible by driving an electro-optic material such as a liquid crystal, for example, between the pixel electrode and the counter electrode, in each pixel. As the driving method of the electro-optical device, not only an active matrix driving method but also various driving methods such as a passive matrix driving method and a segment driving method can be considered.

In the present invention, in particular, the plurality of signal wires are formed of a plurality of conductive films positioned in different layers via an interlayer insulating film. Moreover, the some signal wiring has a part which overlaps each other in at least one part planar view on a board | substrate in a peripheral area. Thereby, it becomes possible to wire a board | substrate so that more signal wiring may not short-circuit each other in the fixed area which looked at the normal line direction. That is, it becomes possible to wire more signal wiring, ensuring the wiring width | variety one by one relatively. This makes it possible to reduce the size of the entire substrate and further the electro-optical device by reducing the peripheral area while ensuring a wide pixel area.

Further, in the present invention, in particular, the plurality of signal wires are each formed of a conductive film which is different for each kind of signal, among the plurality of conductive films, for example. Here, the "type of signal" means the property of the signal itself, such as the frequency of the signal or the height of the potential. For example, among the plurality of signal wires, a signal wire for supplying a signal whose frequency is higher than a predetermined frequency is formed of one conductive film as a high frequency signal wire, and for supplying a signal whose frequency is lower than a predetermined frequency. The signal wiring is a low frequency signal wiring and is formed of one conductive film different from the high frequency signal wiring.

Moreover, especially in this invention, the shield film formed so that it may overlap with a some signal line in the layer between the parts which overlap each other on the board | substrate of a some signal wiring is provided. That is, for example, in order to perform electronic shielding between one signal wire of a plurality of signal wires and another signal wire, the planes of the plurality of signal wires are planarly positioned between the wiring portions overlapping each other. A shield film is provided. As a result, electromagnetic noise generated from signals from each other is reduced by the shield film of one signal wire and the other signal wire. Here, the "sealed film" according to the present invention means a film having an electron shield function such as conduction. In addition, the "sealing film" may be another signal wiring located between one signal wiring and another signal wiring among a plurality of signal wirings. That is, the case where one of the shield film and the plurality of conductive films is shared, and the case where the one of the shield film and the plurality of signal wirings are shared are also included. As a result, the electronic noise which extends to the image signal of the clock signal for data line drive circuits which is a signal with a high frequency especially compared with an image signal is reduced, and high quality image display is attained.

As described above, according to the electro-optical device of the present invention, the substrate size can be reduced, the electro-optical device can be downsized, and the electromagnetic interference between different kinds of signals is reduced, and high-quality image display is possible. Is possible.

In one aspect of the electro-optical device of the present invention, a plurality of data lines and a plurality of scanning lines formed on the substrate to intersect with each other in the pixel region are further provided, and the pixel is disposed at the intersection of the data line and the scanning line. And a storage capacitor in which a lower electrode, a dielectric film, and an upper electrode are stacked in this order on the substrate, and the plurality of conductive films and the shield films are respectively the data line, the lower electrode, and the like. It is the same film as any one of the electrically conductive films which respectively comprise the said upper electrode.

According to this aspect, the plurality of conductive films and the shield film are the same films as any one of the plurality of conductive films respectively constituting the data line, the lower electrode and the upper electrode. Here, "the same film" means a film which is formed at the same opportunity in the manufacturing process, and is the same kind of film. In addition, "it is the same film" does not require the thing which continues as a single film | membrane, but it is basically the meaning that the membrane parts divided in each other among the same film | membrane are enough. Therefore, the plurality of signal wires and the shield film can be formed at the same opportunity as the formation of the data line, the lower electrode or the upper electrode, respectively. In other words, a plurality of signal wirings and a shield film can be formed of a plurality of conductive films without causing complexity in the manufacturing process.

In addition, the storage capacitor improves the potential holding characteristic of the pixel electrode constituting the pixel, for example, and enables high contrast of the display.

In another aspect of the electro-optical device of the present invention, the plurality of signal wires are each formed of the different conductive films for respective preset frequencies.

According to this aspect, for example, among a plurality of signal wires, a signal wire for supplying a signal having a high frequency band whose frequency is higher than a predetermined frequency is formed of one conductive film as the high frequency signal wire, and the frequency has a predetermined frequency. The signal wiring for supplying a signal in the low frequency band lower than the frequency is a low frequency signal wiring and is formed of one conductive film different from the high frequency signal wiring. For example, signal wirings for supplying a clock signal, an enable signal, and the like for driving the data line driving circuit are formed as high frequency signal wirings. On the other hand, for example, signal wiring for supplying a clock signal for driving a scan line driving circuit, signal wiring for supplying various control signals for controlling operations of peripheral circuits such as a data line driving circuit or a scanning line driving circuit, Further, signal wirings for supplying image signals, that is, image signal lines, are formed as low frequency signal wirings. In addition, you may treat the signal wiring for supplying the signal of a fixed electric potential or a fixed electric potential as the low frequency signal wiring here. Therefore, according to the present embodiment, the shield film is positioned between the wiring portions in which the high frequency signal wiring and the low frequency signal wiring overlap each other in plan view. Thus, for example, a low frequency signal such as an image signal is subjected to an electronic influence from a high frequency signal such as a clock signal for driving a data line driving circuit, that is, an electron between a low frequency signal and a high frequency signal. Interference is reduced. For this reason, high quality image display is attained.

In the aspect in which the plurality of signal wirings described above are each formed of different conductive films for each preset frequency band, the plurality of signal wirings include: first frequency signal wiring for supplying a signal having the first frequency; And a second frequency signal wire for supplying a signal having the second frequency lower than the first frequency, wherein the first frequency signal wire, the shield film, and the second frequency signal wire are disposed on the substrate. In this order, the layers may be laminated via the interlayer insulating film.

In this case, the first frequency signal wiring, the shield film, and the second frequency signal wiring are laminated on the substrate in this order via an interlayer insulating film. That is, for example, an image signal line for supplying an image signal is formed as the second frequency signal wiring near the surface in the laminated structure. Therefore, the number of contact holes required for electrically connecting the external circuit connection terminal and the second frequency signal wiring formed close to the surface of the laminated structure is at least reduced. Therefore, the resistance of the second frequency signal wiring can be reduced. In particular, since the image signal line can be reduced, for example, as the second frequency signal wiring, high-quality image display becomes possible. On the other hand, for example, signal wirings for supplying a clock signal for driving a peripheral circuit and the like are formed on the side close to the substrate surface in a laminated structure as the first frequency signal wirings. Generally, TFTs and the like constituting the peripheral circuit are formed on the side close to the substrate surface. Thus, a small number of contact holes between the first frequency signal wire and the peripheral circuit are completed. Therefore, the first frequency signal wire and the peripheral circuit can be easily connected.

In the aspect in which the plurality of signal wirings described above are each formed of different conductive films for each preset frequency band, the plurality of signal wirings include: first frequency signal wiring for supplying a signal having the first frequency; And a second frequency signal wire for supplying a signal having a second frequency lower than the first frequency, wherein the second frequency signal wire, the shield film, and the first frequency signal wire are disposed on the substrate. In this order, the layers may be laminated via an interlayer insulating film.

In this case, the second frequency signal wiring, the shield film and the first frequency signal wiring are laminated on the substrate in this order via the interlayer insulating film. That is, the signal wiring for supplying a signal with high frequency, such as a clock signal for driving a peripheral circuit, for example, is formed as the 1st frequency signal wiring near the surface in a laminated structure. Therefore, heat generated from the first frequency signal wiring due to the high frequency can be radiated or removed from the surface. That is, the first frequency signal wire can be cooled.

In the aspect including the above-mentioned first and second frequency signal wirings, the shield film may be a constant potential wiring for supplying a constant potential.

In this case, since the electrostatic potential wiring functions as a shield film, electronic interference between different kinds of signals can be reduced and high quality image display can be performed without causing complexity of the manufacturing process. The shield film may be a predetermined potential wiring for supplying a predetermined potential signal in which the signal potential changes to a predetermined potential every predetermined time, for example, to be inverted at a predetermined period. Also in this case, since the potential of the signal is constant for each fixed time, the same effect of reducing the electronic interference as described above is obtained correspondingly.

In the aspect in which the above-mentioned constant potential wiring functions as a shield film, the wiring width of the above-mentioned constant potential wiring is at least partially the wiring width of at least one of the first and second frequency signal wirings when viewed in plan view on the substrate. It may be wider than.

In this case, since the wiring width of the constant potential wiring is planar on the substrate and at least partially wider than the wiring width of at least one of the first and second frequency signal wiring, the wiring width between the first and second frequency signal wiring Electronic interference can be reduced more reliably. That is, the function as a shield film of the potential potential wiring can be improved. In addition, since the wiring width is wide, the resistance of the potential wiring can be reduced. Therefore, by the potentiometric wiring, it is possible to supply stable potent wiring or the potentiostatic power supply to the peripheral circuit.

In the aspect in which the above-mentioned constant potential wiring functions as a shield film, the wiring width of the above-mentioned constant potential wiring is planar on the substrate, and at least partially than the wiring width of at least one of the first and second frequency signal wirings. It may be narrow.

In this case, the capacitance constituted from the potential potential wiring, the interlayer insulating film, and the first or second frequency signal wiring, that is, the wiring capacitance can be reduced. Therefore, it is possible to prevent the potential of the potential potential signal from being changed or shaken by the influence of the signals of the first and second frequencies. In other words, it is possible to prevent the electromagnetic noise resulting from the signals of the first and second frequencies from affecting the image signal through, for example, a potential signal such as a potential power supply.

In the embodiment where the wiring width of the above-mentioned constant potential wiring is narrower than at least one of the wiring widths of the first and second frequency signal wirings, the constant potential is the first potential and the second potential which is lower than the first potential. Has a power supply potential, wherein the potential potential wiring includes a first potential power wiring for supplying the first potential and a second potential power wiring for supplying the second potential, and a wiring width of the potential potential wiring is At least partially narrower than all the wiring widths of the first and second frequency signal wirings, wherein the first and second potential power wirings are arranged in parallel and at least partially arranged in parallel on the substrate, The wiring may overlap with each of the first and second frequency signal wirings.

In this case, the first and second potential power wirings are arranged so that they are arranged in parallel and at least partially in parallel on the substrate and overlap each of the first and second frequency signal wirings. Therefore, the electromagnetic noise between the first and second frequency signal wires is reduced by the first and second potential power wires.

For example, when the first potential power wiring is wired between one first and the second frequency signal wires, and the second potential power wiring is wired between the other first and second frequency signal wires, The electronic influence between the second frequency signal wires is different. By the way, in this aspect, since the 1st and 2nd potential power supply wiring overlaps with each of the 1st and 2nd frequency signal wiring, a substantially uniform shielding effect can be acquired.

In another aspect of the electro-optical device of the present invention, the shield film is formed of the same film as the shield film, and is formed below the shield film of the upper layer-side signal wiring formed on the upper layer side of the shield film and of the peripheral circuit. A relay layer is further provided to electrically relay the lower peripheral circuit formed on the side.

According to this aspect, the upper layer side signal wiring and the lower layer side peripheral circuit relay the relay layer and are electrically connected. In other words, the upper layer side signal wiring and the intermediate layer, and the intermediate layer and the lower peripheral circuit are electrically connected, for example, via contact holes interposed between the interlayer insulating films therebetween. Therefore, the situation where the interlayer distance between the upper layer side signal wiring and the lower layer side peripheral circuit is long and making it difficult to connect the two in one contact hole can be avoided. In addition, since the intermediate layer is formed of the same film as the shielded film, the layered structure and the manufacturing process are not complicated.

In another aspect of the electro-optical device of the present invention, a plurality of external circuit connection terminals electrically connected to the plurality of signal wires and the shield film, respectively, arranged in the peripheral region are further provided on the substrate. The shield film overlaps each other with the signal wiring electrically connected to the external circuit connection terminal adjacent to the external circuit connection terminal at least partially electrically connected to the shield film in plan view on the substrate.

According to this aspect, the shield film overlaps with the signal wiring electrically connected to an external circuit connection terminal adjacent to an external circuit connection terminal to which the shield film is electrically connected at least partially in plan view. Therefore, the shield film can be present even in a region in which a plurality of signal wires are electrically connected to the external circuit connection terminals. Therefore, it is possible to more reliably reduce the electromagnetic interference between a plurality of signal wires formed of conductive films positioned on different layers via interlayer insulating films.

In order to solve the said subject, the electronic device of this invention is equipped with the electro-optical device of this invention mentioned above.

According to the electronic apparatus of this invention, since it comprises the electro-optical device of this invention mentioned above, the projection type display apparatus which can display high quality, a mobile telephone, an electronic notebook, a word processor, a viewfinder type, or a monitor direct view type Various electronic devices such as a video tape recorder, a workstation, a television telephone, a POS terminal, and a touch panel can be realized. Further, as the electronic device of the present invention, for example, an electrophoretic device such as an electronic newspaper can be realized.

The operation and other benefits of the present invention will become apparent from the best mode for carrying out the following description.

Implement the invention  Best form for

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described, referring drawings. In the following embodiment, the liquid crystal device of the TFT active-matrix drive system with a built-in drive circuit which is an example of the electro-optical device of this invention is taken as an example.

<1st embodiment>

The liquid crystal device according to the first embodiment will be described with reference to FIGS. 1 to 17.

First, with reference to FIG. 1 and FIG. 2, the whole structure of the liquid crystal device which concerns on this embodiment is demonstrated. Here, FIG. 1 is a top view which shows the structure of the liquid crystal device which concerns on this embodiment, and FIG. 2 is sectional drawing in the H-H 'line | wire of FIG.

1 and 2, in the liquid crystal device according to the present embodiment, the TFT array substrate 10 and the counter substrate 20 are disposed to face each other. The liquid crystal layer 50 is enclosed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are examples of the "pixel region" according to the present invention. It is adhere | attached with each other by the sealing material 52 provided in the sealing area located around the image display area 10a.

In FIG. 1, the light-shielding frame light shielding film 53 which is parallel to the inside of the seal area in which the sealing material 52 is arrange | positioned and which defines the frame area of the image display area 10a is provided in the opposing board | substrate 20 side. It is installed. The data line driving circuit 101 and the external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in the peripheral region, which is located outside the sealing region in which the sealing member 52 is disposed. It is. The sampling circuit 7 is provided so as to be covered by the frame light shielding film 53 inside the seal area according to this one side. In addition, the scanning line driver circuit 104 is provided so as to be covered with the frame light shielding film 53 inside the seal area along two sides adjacent to this one side. In addition, on the TFT array substrate 10, a vertical conducting terminal 106 for connecting the two substrates with the vertical conducting material 107 is disposed in a region facing the four corner portions of the opposing substrate 20. . By these, electrical conduction can be made between the TFT array substrate 10 and the counter substrate 20. In addition, the data line driving circuit 101, the sampling circuit 7, and the scanning line driving circuit 104 are examples of the "peripheral circuit" according to the present invention.

On the TFT array substrate 10, the signal wiring 90 for electrically connecting the external circuit connection terminal 102, the data line driving circuit 101, the scanning line driving circuit 104, the upper and lower conductive terminals 106, and the like. Is formed.

In Fig. 2, on the TFT array substrate 10, a laminated structure in which wirings such as TFTs (Thin Film Transistors) for scanning pixels, scanning lines, data lines, etc. which are driving elements are formed is formed. In the image display region 10a, the pixel electrode 9a is provided on the upper layer of wiring such as a pixel switching TFT, a scanning line, a data line, or the like. On the other hand, the light shielding film 23 is formed on the opposing surface with the TFT array substrate 10 in the opposing substrate 20. And on the light shielding film 23, the counter electrode 21 which consists of transparent materials, such as ITO, is formed facing the some pixel electrode 9a.

In addition, on the TFT array substrate 10, in addition to the data line driver circuit 101 and the scan line driver circuit 104, an inspection circuit for inspecting the quality, defects, and the like of the liquid crystal device during manufacture or shipment, an inspection pattern. Etc. may be formed.

Next, with reference to FIGS. 3-6, the structure in the pixel of the liquid crystal device which concerns on this embodiment is demonstrated. 3 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels formed in a matrix constituting an image display region of a liquid crystal device. 4 and 5 are plan views showing the partial structure related to the pixels on the TFT array substrate, and correspond to the lower layer portion (FIG. 4) and the upper layer portion (FIG. 5) in the laminated structure described later, respectively. FIG. 6 is a cross-sectional view along the line A-A 'in the case of overlapping FIG. 4 and FIG. In addition, in FIG. 6, in order to make each layer and each member into the magnitude | size which can be recognized on drawing, the scale is changed for each each layer and each member.

<Principle Composition of Pixel>

In FIG. 3, TFTs 30 for switching control of the pixel electrode 9a and the pixel electrode 9a are respectively formed in a plurality of pixels formed in a matrix constituting the image display area of the liquid crystal device according to the present embodiment. ) Is formed, and the data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals VS1, VS2, ..., VSn recorded in the data line 6a may be supplied in line order in this order, or may be supplied for each of a plurality of adjacent data lines 6a in groups. do.

In addition, the scanning line 11a is electrically connected to the gate of the TFT 30, and the pulse line scanning signals G1, G2, ..., Gm are line-ordered in this order at the predetermined timing with the scanning line 11a. It is configured to apply. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal VS1, supplied from the data line 6a by closing the switch of the TFT 30 as the switching element only for a certain period of time, VS2, ..., VSn) are recorded at predetermined timing.

The image signals VS1, VS2, ..., VSn of a predetermined level recorded in the liquid crystal via the pixel electrode 9a are held for a predetermined period of time between the counter electrodes formed on the counter substrate. The liquid crystal modulates light by allowing the orientation and order of the molecular set to be changed by the voltage level applied, thereby enabling gray scale display. In the normally white mode, the transmittance for incident light is decreased according to the voltage applied in units of each pixel, and in the normally black mode, the transmittance for the incident light is increased in accordance with the voltage applied in units of pixels, thereby providing liquid crystal as a whole. Light having a contrast in accordance with the image signal is emitted from the device.

In order to prevent the image signal held here from leaking, the storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. One electrode of the storage capacitor 70 is connected to the drain of the TFT 30 in parallel with the pixel electrode 9a, and the other electrode is connected to the capacitance wiring 400 of the potential fixation so as to have an electrostatic potential.

<Specific structure of the pixel>

Next, with reference to FIGS. 4-5, the specific structure of the pixel which implements the above-mentioned operation is demonstrated.

4 to 5, each circuit element of the above-described pixel is patterned and formed on the TFT array substrate 10 as a stacked conductive film. The TFT array substrate 10 is made of, for example, a glass substrate, a quartz substrate, an SOI substrate, a semiconductor substrate, or the like, and is disposed to face the counter substrate 20 made of, for example, a glass substrate or a quartz substrate. In addition, each circuit element includes a first layer including the scanning lines 11a in order from the bottom, a second layer including the TFTs 30 and the like, a third layer including the data lines 6a, and the like. 70) and a fifth layer including the pixel electrode 9a and the like. Further, the base insulating film 12 between the first and second layers, the first interlayer insulating film 41 between the second and third layers, the second interlayer insulating film 42 and the fourth between the third and fourth layers. The third interlayer insulating film 43 is formed between the layer and the fifth layer, and the short circuit between the above-described elements is prevented. In addition, among these, 1st-3rd layer is shown by FIG. 4 as a lower layer part, and 4-5th layer is shown by FIG. 5 as an upper layer part.

(Configuration of the first floor-scan line-)

In FIG. 4, the 1st layer is comprised by the scanning line 11a. The scanning line 11a is patterned in the shape which consists of the main line part extended along the X direction of FIG. 4, and the protrusion part extended in the Y direction of FIG. 4 which the data line 6a extends. The scanning line 11a is made of, for example, conductive polysilicon, and in addition, at least among high melting point metals such as titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), and molybdenum (Mo) It may be formed from a single metal body containing one, an alloy, a metal silicide, a poly silicide or a laminate thereof.

As shown to FIG. 4 and FIG. 6, the scanning line 11a is arrange | positioned so that it may include the area | region which opposes the channel area | region 1a 'on the lower layer side of the TFT 30, and consists of a conductive film.

(Configuration of the second layer -TFT etc.-)

As shown in FIG. 6, the 2nd layer is comprised by TFT (30). The TFT 30 has a LDD (Lightly Doped Drain) structure, for example, and includes a gate insulating film that insulates the gate electrode 3a, the semiconductor layer 1a, the gate electrode 3a, and the semiconductor layer 1a. The insulating film 2 is provided. The gate electrode 3a is formed of conductive polysilicon, for example. The semiconductor layer 1a is made of polysilicon, for example, and has a channel region 1a ', a low concentration source region 1b and a low concentration drain region 1c, and a high concentration source region 1d and a high concentration drain region 1e. ) In addition, the TFT 30 preferably has an LDD structure, but may be an offset structure in which impurities are not introduced into the low concentration source region 1b and the low concentration drain region 1c, and the impurities are formed using the gate electrode 3a as a mask. May be introduced at a high concentration to form a high concentration source region and a high concentration drain region.

The gate electrode 3a of the TFT 30 is electrically connected to the scanning line 11a via a contact hole 12cv formed in the base insulating film 12 in a portion 3b of the TFT 30. The base insulating film 12 is made of, for example, a silicon oxide film or the like, and is formed on the entire surface of the TFT array substrate 10 in addition to the interlayer insulating function of the first layer and the second layer, thereby resulting in polishing of the substrate surface. It has a function of preventing the change of the element characteristic of the TFT 30 which causes roughness, contamination, or the like.

In addition, although the TFT 30 which concerns on this embodiment is a top gate type, it may be a bottom gate type.

(Configuration of third layer-data line etc.)

As shown in FIG. 6, the 3rd layer is comprised from the data line 6a and the relay layer 600. As shown in FIG.

The data line 6a is formed as a three-layer film of aluminum, titanium nitride and silicon nitride in order from the bottom. The data line 6a is formed to partially cover the channel region 1a 'of the TFT 30. For this reason, the channel region 1a 'of the TFT 30 can be shielded from the incident light from the upper layer side by the data line 6a which can be arranged in close proximity to the channel region 1a'. In addition, the data line 6a is electrically connected to the high concentration source region 1d of the TFT 30 via a contact hole 81 passing through the first interlayer insulating film 41.

Further, a conductive film having a lower reflectance may be formed on the side opposite to the channel region 1a 'in the data line 6a as compared with a conductive film such as an Al film constituting the main body of the data line 6a. In this way, the influence of light on the channel region 1a 'can be reduced.

The intermediate layer 600 is formed as the same film as the data line 6a. The intermediate layer 600 and the data line 6a are formed so that each may be divided | segmented, as shown in FIG. In addition, the relay layer 600 is electrically connected to the high concentration drain region 1e of the TFT 30 via a contact hole 83 passing through the first interlayer insulating film 41.

The first interlayer insulating film 41 is formed of, for example, NSG (nonsilicate glass). In addition, silica glass, silicon nitride, silicon oxide, etc. can be used for the 1st interlayer insulation film 41, such as PSG (insilicate glass), BSG (boron silicate glass), BPSG (boron silicate glass).

(Configuration of 4th layer-storage capacity, etc.)

As shown in FIG. 6, the 4th layer is comprised by the storage capacitance 70. As shown in FIG. The storage capacitor 70 is a capacitor electrode 300 as an example of the "upper electrode" according to the present invention and a lower electrode 71 as the "lower electrode" according to the present invention as an example of the "interlayer insulating film" according to the present invention. The structure is arranged to face each other via the dielectric film 75.

The extending part of the capacitor electrode 300 is electrically connected to the relay layer 600 via a contact hole 84 passing through the second interlayer insulating film 42.

The capacitive electrode 300 or the lower electrode 71 is a metal body containing at least one of high melting point metals such as Ti, Cr, W, Ta, Mo, alloys, metal silicides, polysilicides, and the like. One, or preferably tungsten silicide.

As shown in FIG. 5, the dielectric film 75 is formed in the non-opening region located in the gap of the opening region for each pixel in plan view on the TFT array substrate 10, that is, is almost formed in the opening region. Not. The dielectric film 75 is formed of a silicon nitride film having a high dielectric constant or the like without considering the transmittance. As the dielectric film, in addition to the silicon nitride film, for example, a single layer film or a multilayer film such as hafnium oxide (HfO 2), alumina (Al 2 O 3), tantalum oxide (Ta 2 O 5), or the like may be used.

The second interlayer insulating film 42 is formed of, for example, NSG. In addition, silicate glass, silicon nitride, silicon oxide, etc., such as PSG, BSG, and BPSG, can be used for the 2nd interlayer insulation film 42. The surface of the second interlayer insulating film 42 is subjected to planarization such as chemical mechanical polishing (CMP), polishing, spin coating, embedding into recesses, and the like. Therefore, the unevenness caused by these elements on the lower layer side is removed, and the surface of the second interlayer insulating layer 42 is flattened. In addition, this planarization process may be performed with respect to the surface of another interlayer insulation film.

(Configuration of the fifth layer-pixel electrode, etc.)

As shown in FIG. 6, the 3rd interlayer insulation film 43 is formed in the whole surface of a 4th layer, and the pixel electrode 9a is formed as a 5th layer. The third interlayer insulating film 43 is formed of, for example, NSG. In addition, silicate glass, silicon nitride, silicon oxide, etc., such as PSG, BSG, and BPSG, can be used for the 3rd interlayer insulation film 43. Similarly to the second interlayer insulating film 42, the surface of the third interlayer insulating film 43 is planarized by CMP or the like.

As shown in FIG. 4 and FIG. 5, the pixel electrode 9a (outline outlined by the broken line 9a 'in FIG. 5) is arrange | positioned in each of the pixel area arrange | positioned vertically and horizontally, and the boundary The data lines 6a and the scanning lines 11a are formed to be arranged in a grid. In addition, the pixel electrode 9a is made of a transparent conductive film such as indium tin oxide (IT0), for example.

As shown in FIG. 6, the pixel electrode 9a is electrically connected to the extending portion of the capacitor electrode 300 via the contact hole 85 passing through the interlayer insulating film 43. Therefore, the potential of the capacitor electrode 300 which is the conductive film immediately below the pixel electrode 9a becomes the pixel potential. Therefore, the pixel potential is not adversely affected by the parasitic capacitance between the pixel electrode 9a and the lower conductive layer during operation of the liquid crystal device.

As described above, the extending portion of the capacitor electrode 300 and the high concentration drain region 1e of the intermediate layer 600 and the TFT 30 are electrically connected via the contact holes 84 and 83, respectively. Connected. That is, the high concentration drain region 1e of the pixel electrode 9a and the TFT 30 is relay-connected by relaying the extension portions of the relay layer 600 and the capacitor electrode 300.

On the upper side of the pixel electrode 9a, an alignment film 16 subjected to a predetermined alignment treatment such as a rubbing treatment is formed.

The above is the configuration of the pixel on the TFT array substrate 10 side.

On the other hand, in the opposing substrate 20, an opposing electrode 21 is formed on the entire surface of the opposing surface, and an alignment film 22 is further formed thereon (below the opposing electrode 21 in FIG. 6). . The counter electrode 21 is made of a transparent conductive film such as an ITO film, for example, similarly to the pixel electrode 9a. In addition, between the opposing substrate 20 and the opposing electrode 21, the light shielding film 23 is covered so as to cover at least the region opposite to the TFT 30 in order to prevent generation of an optical leakage current in the TFT 30. ) Is formed.

The liquid crystal layer 50 is formed between the TFT array substrate 10 and the counter substrate 20 comprised in this way. The liquid crystal layer 50 is formed by sealing a liquid crystal in a space formed by sealing the periphery of the substrates 10 and 20 with a sealing material. The liquid crystal layer 50 is formed by the alignment film 16 and the alignment film 22 subjected to the alignment treatment such as a rubbing treatment in a state in which no electric field is applied between the pixel electrode 9a and the counter electrode 21. It is supposed to take a predetermined alignment state.

The structure of the pixel demonstrated above is common to each pixel, as shown to FIG. 4 and FIG. Such pixels are periodically formed in the image display region 10a (see FIG. 1) described above.

Next, with reference to FIGS. 7 and 8, the circuit configuration related to the data line driving circuit and the sampling circuit, and the electrical connection relationship by the signal wiring and the like will be described. FIG. 7 is an explanatory diagram showing a circuit configuration related to the data line driving circuit and the sampling circuit, and the electrical connection relationship by the signal wiring and the like. FIG. 8 is a circuit diagram showing a circuit system related to shaping of transmission signals in the configuration shown in FIG. 7.

In FIG. 7, the data line driver circuit 101 includes a shift register 51 and a logic circuit 52.

The shift register 51 is each stage based on the X-side clock signal CLX (and its inverted signal CLX ') and the shift register start signal DX of a predetermined cycle input into the data line driving circuit 101. Is configured to output the transmission signal Pi (i = 1, ..., n) in order from the &quot; In the operation of the liquid crystal device, the shift register 51 is connected to the external circuit connection terminal 102 and the power supply wiring VDDX as an example of the "potential wiring" according to the present invention from an external circuit. (And a low potential power supply VSSX as a power supply) are supplied, and a transistor constituting the shift register 51 is driven.

The logic circuit 52 includes pulse width limiting means, and forms the transmission signal Pi output in order from the shift register 51 on the basis of the enable signals ENB1 to ENB4 and finally based on it. It has a function to output the sampling circuit drive signal Si. In FIG. 8, the logic circuit 52 includes a pulse width control means 540, a precharge circuit 521, and an inverting circuit 523.

In FIG. 8, the pulse width control means 540 is provided with the logic circuit which shapes the waveform of the transmission signal Pi output from the shift register 51. As shown in FIG. More specifically, the pulse width control means 540 is comprised by the unit circuit 540A formed corresponding to each step of the shift register 51, and the unit circuit 540A is comprised by the NAND circuit.

In Fig. 8, the gate of the NAND circuit 540A includes the transfer signal Pi output from the corresponding end of the shift register 51 and four phosphorus as an example of the "plural signal wirings" according to the present invention. One of the enable signals ENB1 to ENB4 supplied to the enable signal line 92 is input. The power supply VDDX (and VSSX) is supplied to the NAND circuit 540A via a wiring not shown in FIG. 8 as a power supply of the NAND circuit 540A. The power supply VDDX is a signal input to the drain of a transistor constituting the NAND circuit 540A, and the power supply VSSX is a signal input to a source of a transistor constituting the NAND circuit 540A.

The NAND circuit 540A performs the shaping of the transmission signal Pi by performing a logical operation of the input transmission signal Pi and the enable signals ENB1 to ENB4. As a result, the NAND circuit 540A generates and outputs a shaping signal Qai, which is a signal in which shaping is performed on the transmission signal Pi. In addition, the unit circuit 540A inverts the logic of the transmission signal Pi or enable signals ENB1 to ENB4 and the shaping signal Qai output from the NAND circuit in addition to the NAND circuit. An inverting circuit or the like may be formed.

The waveform of the transmission signal Pi is trimmed by the pulse width control means 540 based on the waveforms of the enable signals ENB1 to ENB4 having a narrower pulse width, and finally, pulses such as pulse width and pulse period. The shape is limited.

The logic circuit 52 includes a precharge circuit 521 formed corresponding to each stage of the shift register 51. The unit circuit 521A includes an inversion circuit 521a for inverting the logic of the precharge selection signal NRG supplied to the precharge signal supply line 93 and a precharge in which the logic is inverted in the inversion circuit 521a. The NAND circuit 521b inputs the gate select signal NRG and the shaping signal Qai to the gate is substantially formed as a NOR circuit. In the NOR circuit 521A, a logical sum of the shaping signal Qai and the precharge selection signal NRG is calculated, and either one of the shaping signal Qai and the precharge selection signal NRG is output signal Qbi. Output as The output signal Qbi output in this way is output as a sampling circuit drive signal Si via two inverting circuits 523.

7 again, the branch wiring 116 from the image signal line 91 as an example of the "plural signal wiring" concerning this invention is the sampling switch 7s which consists of TFT etc. which comprise the sampling circuit 7 again. ), And the sampling circuit driving signal line 117 from the data line driving circuit 101 is connected to the gate of the sampling switch 302. Therefore, at the time of operation of the liquid crystal device, the image signal applied from the external circuit to the external circuit connection terminals 102 for the image signals VID1 to VID6 passes through the branch wiring 116 from the image signal line 91 through the sampling circuit. It is supplied to (7), and is sampled by the timing according to the sampling circuit drive signal Si supplied from the data line drive circuit 101 via the sampling circuit drive signal line 117 here. Then, the sampled image signal is supplied to each data line 6a.

Although the image signal supplied to the sampling circuit 7 via the branch wiring 116 from the image signal line 91 is not a problem even if it is supplied linearly, in this embodiment, the image signal is serial in 6 phases. Corresponding to each of the parallel expanded image signals, it is configured to be supplied for each group for a set of six data lines 6a. The number of image developments of the image signal is not limited to six phases, but the number of image signals developed in a plurality of phases such as 9 phases, 12 phases, and 24 phases, for example, corresponds to the number of expansions. May be configured to be supplied to a pair of data lines 6a having a set of?.

Next, with reference to FIGS. 6, 7, and 9-11, the signal wiring of the liquid crystal device which concerns on this embodiment is demonstrated in detail. Here, FIG. 9 is sectional drawing in the B-B 'line | wire in FIG. FIG. 10 is a sectional view of the same effect as FIG. 9 in the first modification. FIG. FIG. 11 is a sectional view of the same effect as FIG. 9 in a second modification. FIG. In addition, in FIGS. 9-11, in order to make each layer and each member into the magnitude | size which can be recognized on drawing, the scale is changed for each each layer and each member.

In FIG. 7, signal wires 90 such as the image signal line 91, the enable signal line 92, and the power supply wire 95 are respectively connected to the data line driving circuit 101 from the corresponding external circuit connection terminals 102. And the like. As the signal wiring 90, wiring for supplying clock signals, various control signals, power signals, and the like for driving peripheral circuits such as the data line driving circuit 101 and the scanning line driving circuit 104 is also formed.

As shown in FIG. 9, in the present embodiment, in particular, the signal wiring 90 such as the image signal line 91, the enable signal line 92, the power supply wiring 95, and the like are the second interlayer insulating film 42 and the dielectric film. It is formed of the some electrically conductive film located in the different layer through 75. Therefore, the signal wirings 90 such as the image signal lines 91, the enable signal lines 92, and the power supply wirings 95 can be wired so as to overlap each other at least partially in plan view on the TFT array substrate 10. FIG. . Therefore, it becomes possible to wire so that more signal wirings 90 may not short-circuit each other in the constant area which saw the board | substrate from the normal line direction. That is, it becomes possible to wire more signal wirings 90, ensuring the width | variety of each wiring one by one. As a result, the TFT array substrate 10 as a whole is reduced by reducing the peripheral region located around the image display region 10a while the image display region 10a is widely secured, thereby miniaturizing the entire liquid crystal device. You can do it.

In the present embodiment, in particular, the plurality of signal wires 90 are each formed of a conductive film different for each frequency band of the signal. As shown in FIG. 9, that is, the enable signal line 92 for supplying the enable signals ENB1 to ENB4 having a higher frequency than the image signals VID1 to VID6 is an image signal line 91 for supplying an image signal. It is formed with the electrically conductive film different from each other. In addition, the enable signal line 92 is an example of the "first frequency signal wiring" which concerns on this invention, and the image signal line 91 is an example of the "second frequency signal wiring" which concerns on this invention. The power supply wiring 95 is wired between the image signal line 91 and the enable signal line 92 via the dielectric film 75 and the second interlayer insulating film 42, respectively. Therefore, since the potential of the power supply VDDX supplied via the power supply wiring 95 is constant, the power supply wiring 95 functions as a shield film between the image signal line 91 and the enable signal line 92. That is, electronic interference between the image signal and the enable signal can be reduced. In particular, since the enable signals ENB1 to ENB4 are higher than the frequencies of the image signals VID1 to VID6, the electronic noise to the image signals VID1 to VID6, which are generated, can be reduced. Therefore, high quality image display becomes possible. The image signal line 91 is similarly applied to the signal line 90 for supplying a signal having a frequency higher than the frequency band of the image signal, for example, a clock signal CLK for driving the data line driving circuit 101 and the like. ), The electromagnetic noise with respect to the image signals VID1 to VID6 can be reduced by forming the conductive film different from the conductive film to be formed.

6 and 9, in the present embodiment, in particular, the image signal line 91 is formed of the same film as the conductive film constituting the capacitor electrode 300, and the power supply wiring 95 is the lower electrode 71. ) And the enable signal line 92 is formed of the same film as the conductive film constituting the data line 6a. Therefore, the image signal line 91, the power supply wiring 95 and the enable signal line 92 can be formed at the same opportunity as the formation of the capacitor electrode 300, the lower electrode 71 and the data line 6a, respectively. . That is, a plurality of signal wirings and a shield film can be formed of a plurality of conductive films without incurring complicated manufacturing processes. In addition, any of the signal wirings 90 such as the image signal line 91, the power supply wiring 95, and the enable signal line 92 may be any of the capacitor electrode 300, the lower electrode 71, and the data line 6a. You may form with the same film as the conductive film which comprises. Moreover, you may form with the same film as the conductive films other than the capacitor electrode 300, the lower electrode 71, and the data line 6a in a pixel.

In addition, as shown in FIG. 9, in the present embodiment, particularly, the enable signal line 92, the power supply wiring 95, and the image signal line 91 are arranged on the TFT array substrate 10 in the second interlayer in this order. The insulating film 42 and the dielectric film 75 are laminated via each other. That is, the image signal line 91 is formed on the side closer to the surface in the laminated structure. Therefore, the number of contact holes required to electrically connect the external circuit connection terminal 102 and the image signal line 91 formed near the surface of the laminated structure is at least reduced. Therefore, the image signal line 91 can be reduced in resistance. This enables high quality image display. On the other hand, the enable signal line 92 is formed near the surface of the TFT array substrate 10 in the laminated structure. The TFT or the like constituting the logic circuit 52 to which the enable signal line 92 is electrically connected is formed near the substrate surface. Therefore, the number of contact holes between the enable signal line 92 and the TFT constituting the logic circuit 52 is at least reduced. Therefore, the enable signal line 92 and the logic circuit 52 can be easily connected.

Here, as shown as a 1st modification in FIG. 10, the image signal line 91, the power supply wiring 95, and the enable signal line 92 are the 2nd interlayer insulation film in this order on the TFT array substrate 10 here. The 42 and the dielectric film 75 may be laminated respectively. That is, the enable signal line 92 may be formed on the side closer to the surface in a laminated structure. In this case, heat generated from the enable signal line 92 due to the high frequency of the enable signals ENB1 to ENB4 can be radiated or removed from the surface of the laminated structure. In other words, the enable signal line 92 can be cooled.

7 again, especially in this embodiment, the wiring width of the power supply wiring 95 is wider than the wiring width of the image signal line 91 and the enable signal line 92 in plan view on the TFT array substrate 10. . In other words, the power supply wiring 95 is formed so as to partially overlap with the plurality of image signal lines 91 and the plurality of enable signal lines 92 in plan view on the TFT array substrate 10. Therefore, the electromagnetic interference between the image signal line 91 and the enable signal line 92 can be reduced more reliably, that is, the function as a shield film of the power supply wiring 95 can be improved. In addition, since the wiring width of the power supply wiring 95 is wide, the resistance of the power supply signal wiring 95 can be reduced. Therefore, the stable power supply VDDX can be supplied to the data line driving circuit 101 by the power supply wiring 95.

Here, as shown in FIG. 11 as a 2nd modification, a power supply is a power supply which makes one set the power supply VDDX which has a predetermined electric potential, and the power supply VSSX which has a potential lower than the electric potential of the power supply VDDX as one set. The wiring widths of the power supply wiring 95d for supplying the VDDX and the power supply wiring 95s for supplying the power supply VSSX are at least partially selected from any of the image signal lines 91 and the enable signal lines 92. It may be narrower than the width. In addition, the power supply VDDX is an example of the "first potential" which concerns on this invention, and the power supply VSSX is an example of the "second potential" which concerns on this invention. In addition, the power supply wiring 95d is an example of the "first potential power supply wiring" which concerns on this invention, and the power supply wiring 95s is an example of the "second potential power supply wiring" which concerns on this invention. In addition, the power supply wirings 95d and 95s are one set and overlap with each of the image signal line 91 and the enable signal line 92 so as to be arranged on the TFT array substrate 10 in plan view, at least in part, to each other. You may wire as much as possible. In this case, the electromagnetic noise between the image signal line 91 and the enable signal line 92 is reduced by the power supply wirings 95d and 95s. Further, for example, the power supply wiring 95d is wired between one image signal line 91 and the enable signal line 92, and the power supply wiring 95s is connected between the other image signal line 91 and the enable signal line 92. In this case, the electronic influence between the image signal line 91 and the enable signal line 92 is different. By the way, in this embodiment, since the power supply wirings 95d and 95s overlap with each of the image signal line 91 and the enable signal line 92 as one set, a nearly uniform shielding effect can be obtained.

Next, with reference to FIG. 12 and FIG. 13, the specific structure regarding the electrical connection of an image signal line and a sampling circuit is demonstrated. 12 is a layout diagram of image signal lines and branch wirings. FIG. 13 is a cross-sectional view taken along the line D-D 'of FIG. 12.

As shown in FIG. 12, on the TFT array substrate 10, the sampling circuit driving signal line 117 is wired in a direction crossing the image signal line 91 from the data line driving circuit 101, and sampling sampling is performed. It branches in every 7s and is wired in the direction which the data line 6a extends. In addition, the branch wiring 116 extends the data line 6a from one end side electrically connected to the corresponding image signal line 91 via a contact hole 181 that is opened in the dielectric film 75. Is wired in the direction. A part of the branch wiring 116 forms a source electrode of the sampling switch 7s, a part of the data line 6a forms a drain electrode of the sampling switch 7s, and the sampling circuit driving signal line 117 Some form the gate electrode of the sampling switch 7s. 12 and 13, the branch wiring 116 has the semiconductor layer 1a in the sampling switch 7s via the contact hole 183 opened in the first interlayer insulating film 41. It is electrically connected with.

As shown in FIG. 13, especially in this embodiment, this branch wiring 116 is relay wiring as an example of the "layer layer" which concerns on this invention in which one end is electrically connected to the corresponding image signal line 91. FIG. 500. The relay wiring 500 is formed of the same film as the conductive film constituting the power supply wiring 95 functioning as the shield film, that is, the conductive film constituting the lower electrode 71, and the relay wiring 500 and the branch wiring. The distribution line except the relay wiring 500 is electrically connected to the distribution line 116 through the contact hole 182 which was opened in the 2nd interlayer insulation film 42. That is, the sampling circuit as an example of the image signal line 91, the relay wiring 500, and the relay wiring 500 as an example of the "upper side signal wiring" according to the present invention, and the "lower peripheral circuit" according to the present invention. The sampling switch 7s constituting (7) is electrically connected to each other through the contact holes 181 or 182 that are opened in the dielectric film 75 or the second interlayer insulating film 42 therebetween. Therefore, the situation where the interlayer distance between the image signal line 91 and the sampling switch 7s constituting the sampling circuit 7 is long is long, making it difficult to connect between them by one contact hole. In addition, since the relay wiring 500 is formed of the same film as the power supply wiring 95 functioning as a shield film, the relay structure 500 does not cause a complicated structure and a manufacturing process.

Next, with reference to FIGS. 14-17, the layout of the signal wiring in the periphery of an external circuit connection terminal is demonstrated. 14 is a layout diagram of signal wiring around the external circuit connection terminal. FIG. 15 is a cross-sectional view taken along the line D-D 'in FIG. 14. FIG. 16 is a cross-sectional view taken along the line E-E 'in FIG. 14. FIG. 17 is a cross-sectional view taken along the line F-F 'in FIG. 14. In addition, in FIG. 15-17, in order to make each layer and each member into the magnitude | size which can be recognized on drawing, the scale differs for each layer and each member.

In FIG. 14, the image signal line 91, the power supply wiring 95, and the enable signal line 92 are electrically connected to the corresponding external circuit connection terminals 102d, 102e, and 102f, respectively. The external circuit connection terminals 102d, 102e and 102f are adjacent to each other. As shown in FIGS. 15-17, these external circuit connection terminals 102d, 102e, and 102f are the same film as the conductive film which comprises the image signal line 91, ie, the conductive film which comprises the capacitor electrode 300. FIG. It is formed.

As shown to FIG. 14 and FIG. 15, the image signal line 91 is integrally formed with the external circuit connection terminal 102d by the same film | membrane.

As shown in FIG. 14 and FIG. 16, the power supply wiring 95 is connected to an external circuit connection terminal via a contact hole 191 opened in the dielectric film 75 formed around the external circuit connection terminal 102e. 102e) is electrically connected.

As shown in FIG. 14 and FIG. 17, the enable signal line 92 has a contact hole 192 penetrating through the dielectric film 75 and the second interlayer insulating film 42 formed around the external circuit connection terminal 102f. ) Is electrically connected to the external circuit connection terminal 102f.

As shown in FIG. 14, especially in this embodiment, the power supply wiring 95 is viewed on the TFT array substrate 10 in plan view, and is partially connected to the external circuit connection terminals 102d and adjacent to the external circuit connection terminals 102e. The image signal line 91 and the enable signal line 92 electrically connected to 102f overlap each other. That is, the power source wiring lines are also used in the region located around the portion where the image signal lines 91 and the enable signal lines 92 are connected on the TFT array substrate 10 in plan view, respectively, to the external circuit connection terminals 102d and 102f. 95) part of it exists. Therefore, even when the image signal line 91 and the enable signal line 92 are located in the vicinity of the portion electrically connected to the external circuit connection terminals 102d and 102e, respectively, by the power supply wiring 95 to the shield film, Electronic interference between the image signal line 91 and the enable signal line 92 can be reduced more reliably. In addition, the power supply wiring 95 to the shield film may be partially or completely overlapped with the external circuit connection terminal 102c or 102e in plan view on the TFT array substrate 10.

As described above, according to the liquid crystal device of the present embodiment, the size of the TFT array substrate 10 can be reduced, the liquid crystal device can be reduced in size, and electronic interference between different types of signals can be reduced. High quality image display is possible.

<2nd embodiment>

 Next, the liquid crystal device according to the second embodiment will be described with reference to FIG. 18. Here, FIG. 18 is sectional drawing of the same effect as FIG. 6 in 2nd Embodiment. In addition, in FIG. 18, the same code | symbol is attached | subjected to the same component as the component which concerns on 1st embodiment shown in FIG. 6, and their description is abbreviate | omitted suitably.

 In FIG. 18, the pixel in the liquid crystal device of this embodiment contains the 1st layer containing the scanning line 11a, the 2nd layer containing the gate electrode 3a, and the storage capacitor 70 in order from the bottom. And a sixth layer including a third layer, a fourth layer including a data line 6a, and the like, a fifth layer including a capacitor wiring 400, and the like, a pixel electrode 9a, and the like.

The structure of a 1st layer and a 2nd layer is substantially the same as the structure of the pixel in 1st Embodiment mentioned above.

(Configuration of 3rd layer-storage capacity, etc.)

In FIG. 18, the 3rd layer is comprised by the storage capacitance 70. As shown in FIG. Among these, the capacitor electrode 300 is electrically connected to the capacitor wiring 400. The lower electrode 71 is electrically connected to each of the high concentration drain region 1e and the pixel electrode 9a of the TFT 30. In addition, the capacitor wiring 400 is an example of the "upper electrode" which concerns on this invention.

The lower electrode 71 and the high concentration drain region 1e are connected via a contact hole 83 that is opened in the first interlayer insulating film 41. In the lower electrode 71 and the pixel electrode 9a, the contact holes 881, 882, 804, and 89 are formed of the relay electrode 719, the second relay electrode 6a2, and the third relay electrode 402. Electrically connected by the path comprised by relaying each layer.

The capacitive electrode 300 is, for example, a metal body containing an at least one of high melting point metals such as Ti, Cr, W, Ta, Mo, an alloy, a metal silicide, a polysilicide, a laminate of these, or preferred. Preferably made of tungsten silicide. In addition, for example, conductive polysilicon is used for the lower electrode 71.

(Configuration-data line of the fourth floor-)

 In FIG. 18, the 4th layer is comprised by the data line 6a. The data line 6a is formed of a three-layer film of aluminum, titanium nitride and silicon nitride in order from the bottom. In the fourth layer, a second relay electrode 6a2 is formed as the same film as the data line 6a.

Among these, the data line 6a is electrically connected to the high concentration source region 1d of the TFT 30 via the contact hole 81 passing through the first interlayer insulating film 41 and the second interlayer insulating film 42. Is connected. As described above, the second relay electrode 6a2 is electrically connected to the relay electrode 719 via the contact hole 882 penetrating through the first interlayer insulating film 41 and the second interlayer insulating film 42. Is connected.

(Configuration-capacity wiring, etc. of the fifth layer)

In FIG. 13, the 5th layer is comprised from the capacitor wiring 400 and the 3rd relay electrode 402. As shown in FIG. The capacitor wiring 400 has a two-layer structure in which aluminum and titanium nitride are stacked, for example. The capacitor wiring 400 and the capacitor electrode 300 have a structure for connecting through the contact hole 801. In addition, a third relay electrode 402 is formed as the same film as the capacitor wiring 400. As described above, the third relay electrode 402 is relayed between the second relay electrode 6a2 and the pixel electrode 9a via the contact hole 804 and the contact hole 89.

(Configuration of the sixth layer-pixel electrode, etc.)

 In FIG. 13, a contact hole 89 is provided in the fourth interlayer insulating film 44 to electrically connect the pixel electrodes 9a to the third relay electrode 402.

The above is the pixel structure of this embodiment.

As mentioned above, in the pixel of this embodiment, the film | membrane which forms the capacitor wiring 400, the data line 6a, the capacitor electrode 300, and the lower electrode 71, respectively is a conductive film. Thereby, the signal wiring 90 or the shield film, such as the image signal line 91, the power supply wiring 95, and the enable signal line 92, may be formed in the same film as any one of these four conductive films. Similarly, like the liquid crystal device of the first embodiment, the manufacturing process is not complicated, and the signal wiring 90 such as the image signal line 91, the power supply wiring 95, the enable signal line 92, and the like is not caused. Alternatively, the shield films may be formed of different conductive films. Therefore, the area on the TFT array substrate 10 necessary for wiring the signal wiring 90 such as the image signal line 91, the power supply wiring 95, the enable signal line 92, and the like can be made small. Depending on the shield film, electronic interference between different kinds of signals can be reduced.

(Electronics)

Next, the case where the liquid crystal device which exists as the electro-optical device mentioned above is applied to various electronic devices is demonstrated.

First, the projector using this liquid crystal device for a light valve is demonstrated. 19 is a plan view illustrating a configuration example of a projector. As shown in FIG. 19, inside the projector 1100, the lamp unit 1102 which consists of white light sources, such as a halogen lamp, is formed. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 disposed in the light guide 1104, corresponding to each primary color. Incident on the liquid crystal panels 1110R, 1110B, and 1110G as light valves.

The structures of the liquid crystal panels 1110R, 1110B, and 1110G are equivalent to those of the liquid crystal device described above, and are driven by primary color signals of R, G, and B supplied from an image signal processing circuit, respectively. The light modulated by these liquid crystal panels is incident on the dichroic prism 1112 from three directions. In this dichroic prism 1112, light of R and B is refracted by 90 degrees, while light of G goes straight. Therefore, as a result of synthesizing the images of each color, the color image is projected onto the screen or the like through the projection lens 1114.

Here, when the display image by each liquid crystal panel 1110R, 1110B, and 1110G is paid attention, the display image by the liquid crystal panel 1110G needs to invert left and right with respect to the display image by the liquid crystal panel 1110R, 1110B. Become.

In addition, since the light corresponding to each primary color of R, G, and B enters into the liquid crystal panels 1110R, 1110B, and 1110G, it is not necessary to form a color filter.

Next, an example in which the liquid crystal device is applied to a mobile PC will be described. 20 is a perspective view showing the configuration of this PC. In FIG. 20, the computer 1200 is composed of a main body portion 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206. This liquid crystal display unit 1206 is configured by adding a backlight to the back of the liquid crystal device 1005 described above.

In addition, an example in which the liquid crystal device is applied to a cellular phone will be described. Fig. 21 is a perspective view showing the structure of this cellular phone. In FIG. 21, the cellular phone 1300 includes a reflective liquid crystal device 1005 together with a plurality of operation buttons 1302. In this reflective liquid crystal device 1005, front lights are formed on the entire surface of the reflective liquid crystal device 100 as necessary.

 In addition to the electronic apparatus described with reference to FIGS. 19 to 21, a liquid crystal television, a viewfinder type, a monitor direct view type videotape recorder, a car navigation device, a pager, an electronic notebook, an electronic calculator, a word processor, a workstation, and a television A telephone, a POS terminal, the apparatus provided with a touch panel, etc. are mentioned. Needless to say, those applicable to these various electronic devices.

In addition to the liquid crystal device described in the above-described embodiments, the present invention also includes a reflective liquid crystal device (LCOS), a plasma display (PDP), a field emission display (FED, SED), and an organic EL that form elements on a silicon substrate. It is also applicable to a display.

This invention is not limited to embodiment mentioned above, It can change suitably in the range which is not contrary to the summary or idea of the invention which can be found from the Claim and the whole specification, and the electro-optic accompanying with such a change. Apparatus, and an electronic device comprising the electro-optical device are also included in the technical scope of the present invention.

According to the liquid crystal device of the present embodiment, the size of the TFT array substrate 10 can be reduced, the liquid crystal device can be downsized, electronic interference between different types of signals can be reduced, and high quality image display. Is possible.

Claims (12)

On the substrate, A plurality of pixels formed in the pixel region, A peripheral circuit formed in a peripheral region positioned around the pixel region, for controlling the plurality of pixels; A plurality of different types of signals for controlling the peripheral circuits are supplied, respectively, and are formed of a plurality of first conductive films positioned on different layers via an interlayer insulating film, and at least partially in the peripheral region. A plurality of signal wires having portions overlapping each other; And a second conductive film formed so as to overlap with the plurality of signal wires in the layer between the overlapping portions of the plurality of signal wires. The method of claim 1, Further comprising a plurality of data lines and a plurality of scan lines formed on the substrate to cross each other in the pixel area, The pixel is formed in accordance with the intersection of the data line and the scan line, and has a storage capacitor in which a lower electrode, a dielectric film, and an upper electrode are stacked in this order; The plurality of first conductive films and the second conductive films are the same film as any one of the conductive films constituting the data line, the lower electrode, and the upper electrode, respectively. The method according to claim 1 or 2, And the plurality of signal wires are each formed of the first conductive film which is different for each preset frequency. The method of claim 3, wherein The plurality of signal wires, A first frequency signal wire for supplying a signal whose frequency is a first frequency, and A second frequency signal wire for supplying a signal having a second frequency wherein said frequency is lower than said first frequency, The first frequency signal wiring, the second conductive film, and the second frequency signal wiring are laminated on the substrate in this order with an interlayer insulating film interposed therebetween. The method of claim 3, wherein The plurality of signal wires, A first frequency signal wire for supplying a signal whose frequency is a first frequency, and A second frequency signal wire for supplying a signal having a second frequency wherein said frequency is lower than said first frequency, The second frequency signal wire, the second conductive film, and the first frequency signal wire are laminated on the substrate in this order with an interlayer insulating film interposed therebetween. The method of claim 4, wherein And the second conductive film is an electrostatic potential wiring for supplying a constant electric potential. The method of claim 6, The wiring width of a part or all of the said potential potential wiring is larger than the wiring width of at least one of the said 2nd frequency signal wiring and the said 1st frequency signal wiring in plan view on the said board | substrate. The method of claim 6, The wiring width of a part or the whole of the said potential potential wiring is narrower than the wiring width of at least one of the said 1st and 2nd frequency signal wiring in plan view on the said board | substrate. The method of claim 8, The constant potential is a power source potential having a first potential and a second potential that is lower than the first potential, The potential potential wiring is made up of a first potential power wiring for supplying the first potential and a second potential power wiring for supplying the second potential, The wiring width of part or all of the potential potential wiring is narrower than any wiring width of the first and second frequency signal wirings, Some or all of the first and second potential power wirings are arranged in parallel on the substrate, and are wired so as to overlap with each of the first and second frequency signal wirings. Device. The method according to claim 1 or 2, An upper layer side signal line formed on the same layer as the second conductive film and formed above the second conductive film among the plurality of signal wires, and a lower layer side formed below the second conductive film in the peripheral circuit. An electro-optical device, further comprising a relay layer for electrically relaying peripheral circuits. The method according to claim 1 or 2, On the substrate, A plurality of external circuit connection terminals electrically connected to the plurality of signal wires and the second conductive film, respectively, arranged in the peripheral region; A part or all of the second conductive film overlaps with the signal wiring electrically connected to the external circuit connection terminal adjacent to the external circuit connection terminal to which the second conductive film is electrically connected in plan view. Electro-optical device, characterized in that. An electronic apparatus comprising the electro-optical device according to claim 1.

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