JP2007017478A - Electro-optical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the discontinuous change of picture quality near the boundary of a dummy pixel with a display pixel, and to suppress the increase of an area occupied by the dummy pixels in an electro-optical device such as a liquid crystal device. <P>SOLUTION: The electro-optical device is equipped with: a plurality of pixel sections arranged on a pixel region; and a plurality of dummy pixel sections respectively arranged on a plurality of dummy pixel regions. Alignment pitches of the dummy pixel regions are less than those in the pixel region, and further gradually decrease with distance from an edge of the pixel region. A ratio of magnitude of the alignment pitch of the first dummy pixel region out of the dummy pixel regions adjacent to the pixel region to that of the pixel region is larger than a ratio of magnitude of the alignment pitch of the second dummy pixel region, adjacent to the first dummy pixel region from the side opposite to the pixel region, to that of the first dummy pixel region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  In this type of electro-optical device, for example, a plurality of pixel portions each having a pixel electrode or the like are arranged in a matrix in a pixel region such as an image display region. In each pixel portion, in order to enable active matrix driving, a pixel switching thin film transistor (Thin Film Transistor: hereinafter referred to as “TFT” as appropriate) for switching driving a pixel electrode, for example, a pixel electrode and a counter electrode In general, a storage capacitor is provided so as to provide a predetermined capacity in parallel with the liquid crystal capacitor constructed between the two.

  In the case of this type of electro-optical device, a structure in which a large number of pixel portions exist near the center of the pixel region near the edge of the pixel region, but no pixel portion exists on the opposite side. Due to this imbalance, electro-optical material malfunctions such as liquid crystal alignment defects are likely to occur. Therefore, conventionally, a dummy pixel portion or a dummy pixel that simulates a pixel portion is generally arranged in a peripheral region surrounding the periphery of the pixel region or a region close to the pixel region in the frame region. Traditionally, such dummy pixels have the same size and the same structure as the pixels (ie, display pixels). Furthermore, in order to use the substrate effectively, a structure in which dummy pixels having a width smaller than that of the display pixels are arranged has been proposed (see Patent Document 1).

Japanese Patent No. 3027703

  However, as in Patent Document 1, when a dummy pixel having a small width dimension is provided adjacent to a display pixel, the smaller the width dimension is, for example, in an etching process for forming a wiring or a storage capacitor. As a result, the electrical or optical properties of the dummy pixel and the display pixel change discontinuously. Therefore, there is a technical problem that the image quality is likely to change discontinuously near the dummy pixels. In particular, when data lines are simultaneously driven for each data line group including a plurality of data lines using an image signal subjected to serial-parallel conversion or phase expansion, data lines adjacent to the dummy pixel region are used. A striped or striped shape between a display pixel block driven by a group and a display pixel block adjacent thereto, depending on a discontinuous change in electrical or optical properties between the dummy pixel and the display pixel. In practice, the display defect is likely to occur very seriously.

  On the other hand, if the dummy pixel is constructed in the same size as the display pixel according to the traditional method, the presence of the dummy pixel causes a relative increase in the surrounding area. In particular, when driving each data line group using a plurality of serial-parallel converted image signals, it is desirable to arrange dummy pixels on the data lines and arrange them in the number of parallel image signal lines. Accordingly, the number of dummy pixels is inevitably increased. For example, if the number of conversions or phase expansions related to serial-parallel conversion is 12, 24, 48, 96,..., The area occupied by the dummy pixels is enlarged to a degree that cannot be ignored.

  The present invention has been made in view of the above problems. For example, the electro-optical device can prevent discontinuous change in image quality near the boundary between a dummy pixel and a display pixel and can suppress an increase in the area occupied by the dummy pixel. It is an object of the present invention to provide an apparatus and an electronic apparatus including such an electro-optical device.

  In order to solve the above problems, a first electro-optical device according to an aspect of the invention includes a plurality of pixel portions arranged in a pixel region on a substrate and a periphery of the pixel region as viewed in plan on the substrate. A plurality of dummy pixel portions, each of which is arranged in a plurality of dummy pixel regions constituting a surrounding peripheral region, and each simulates at least a part of the structure of the pixel portion, and at least the pixels in the peripheral region In the region adjacent to one side of the region, the arrangement pitch of the dummy pixel region in at least one of the direction along the one side and the direction intersecting the one side is smaller than the arrangement pitch of the pixel region, The arrangement pitch of the dummy pixel regions gradually decreases as the distance from the one side increases, and the arrangement pitch of the first dummy pixel region adjacent to the pixel region in the dummy pixel region is increased. The ratio of the size of the pixel region to the arrangement pitch of the first dummy pixel region is equal to the arrangement pitch of the second dummy pixel region adjacent to the first dummy pixel region on the opposite side of the pixel region. It is larger than the ratio of size to pitch.

  According to the first electro-optical device of the present invention, during the operation, an image signal, a scanning signal, and the like are supplied to the pixel portion via, for example, a wiring such as a data line and a scanning line. These image signals and the like are selectively supplied to a display electrode such as a pixel electrode from a switching element such as a thin film transistor for pixel switching (hereinafter referred to as “TFT”) in the pixel portion. Matrix driving is performed. That is, image display is performed in a pixel region in which a plurality of pixel portions are arranged in a matrix. At this time, in the dummy pixel region, as in the pixel region, an active matrix drive is performed in the dummy pixel region by supplying an image signal or the like to the dummy pixel portion that simulates the structure of the pixel portion. Accordingly, incompletely driven pixel portions such as a portion where the liquid crystal is driven incompletely, which occurs near the edge of the pixel region in the active matrix driving, are excluded from the actually displayed pixel region. Therefore, it is possible to display a good image to every corner of the pixel area. Here, “simulating the structure of the pixel portion” means that the dummy pixel portion is viewed in plan on the substrate so that the electrical or optical properties of the dummy pixel portion are somewhat closer to the pixel portion. It means that the structure is similar to the structure of the pixel portion. That is, in a narrow sense, it means that the structure of the dummy pixel portion is the same as the structure of the pixel portion, but in a broad sense, the structure of the dummy pixel portion so that the dummy pixel portion is close to the pixel portion. Is closer to the structure of the pixel portion. For example, it means that the laminated structure of the dummy pixel portion includes the same part as the part of the laminated structure of the pixel portion, or that the dummy pixel portion has the same kind of electronic element as the electronic element included in the pixel portion. Therefore, the pixel portion can be easily simulated by the dummy pixel portion.

  Here, particularly in the first electro-optical device of the present invention, the arrangement pitch of the dummy pixel regions is smaller than the arrangement pitch of the pixel regions, and the arrangement pitch of the dummy pixel regions is gradually decreased as the distance from one side of the pixel region is increased. Become. Therefore, it is possible to reduce the area of the peripheral region necessary for arranging the plurality of dummy pixel regions, and to prevent the electrical or optical properties of the dummy pixel portion and the pixel portion from changing discontinuously. . Specifically, when etching is performed to form wirings and storage capacitors in the pixel portion and the dummy pixel portion, it is caused by a difference in density of the wiring and storage capacitors due to a difference in size between the pixel region and the dummy pixel region. Etching spots that may occur can be reduced or eliminated. That is, it is possible to prevent the image quality from changing discontinuously near the boundary between the dummy pixel portion and the pixel portion, and to suppress an increase in the surrounding area occupied by the dummy pixel portion.

  In particular, when a serial-parallel converted or phase-expanded image signal is handled, a dummy pixel unit is interposed between a pixel unit block driven by a data line group adjacent to the dummy pixel region and a pixel unit block adjacent thereto. In accordance with the discontinuous change in electrical or optical properties between the pixel portion and the pixel portion, it is possible to prevent a stripe-like or stripe-like display defect from occurring.

  Here, “gradually smaller” means smaller continuously or intermittently or stepwise. In other words, the width Wi (i = 1,..., N (where n is a natural number of 3 or more)) in the direction intersecting the one side of the dummy pixel region becomes W1 ≧ W2 ≧ ... ≧ Wn as the distance from the one side increases. It means that the relationship changes so as to satisfy the relationship (W1> Wn) Therefore, typically, three or more dummy pixel regions according to the present invention are arranged in a direction intersecting the one side. In other words, the dummy pixel region is arranged in three rows or three columns or more along the one side.

  Further, in the first electro-optical device of the present invention, in particular, the ratio of the size of the arrangement pitch of the first dummy pixel area adjacent to the pixel area in the dummy pixel area to the arrangement pitch of the pixel area is the first dummy pixel area. On the other hand, the ratio of the arrangement pitch of the second dummy pixel areas adjacent to the opposite side of the pixel area to the arrangement pitch of the first dummy pixel areas is larger. That is, for example, the arrangement pitch of the first dummy pixel region is, for example, 80% of the arrangement pitch of the pixel region, and the arrangement pitch of the second dummy pixel region is, for example, 50%, that is, half of the arrangement pitch of the first dummy pixel region. It is. In other words, the degree or degree to which the arrangement pitch of the first dummy pixel area changes from the arrangement pitch of the pixel area is the degree or degree to which the arrangement pitch of the second dummy pixel area changes from the arrangement pitch of the first dummy pixel area. Small compared to That is, in the immediate vicinity of the pixel area, the arrangement pitch does not change much.

  For this reason, the arrangement pitch of the first dummy pixel region is smaller than the arrangement pitch of the pixel region, and etching for forming, for example, a wiring or a storage capacitor is uniformly performed near the boundary between the dummy pixel portion and the pixel portion. Thus, it is possible to reliably prevent the image quality from changing discontinuously. Furthermore, by increasing the arrangement pitch of the second dummy pixel areas to, for example, half of the arrangement pitch of the first dummy pixel areas, an increase in the surrounding area occupied by the dummy pixel areas can be efficiently suppressed.

  As described above, according to the first electro-optical device of the present invention, it is possible to prevent a discontinuous change in image quality near the boundary between the dummy pixel portion and the pixel portion, and the dummy pixel region occupies. It is possible to efficiently suppress the increase in the surrounding area and to effectively use the area on the substrate.

  In order to solve the above problems, a second electro-optical device of the present invention has a plurality of pixel portions arranged in a pixel region on a substrate and a periphery of the pixel region when viewed in plan on the substrate. A plurality of dummy pixel portions, each of which is arranged in a plurality of dummy pixel regions constituting a surrounding peripheral region, and each simulates at least a part of the structure of the pixel portion, and at least the pixels in the peripheral region In a region adjacent to one side of the region, the arrangement pitch of the dummy pixel regions in at least one of the direction along the one side and the direction intersecting the one side gradually decreases as the distance from the one side increases. The first of the arrangement pitches of the second dummy pixel regions adjacent to the opposite side of the pixel region with respect to the first dummy pixel region adjacent to the pixel region in the dummy pixel region. The ratio of the size of the me pixel area to the arrangement pitch is the second dummy pixel area of the arrangement pitch of the third dummy pixel area adjacent to the second dummy pixel area opposite to the first dummy pixel area. Larger than the ratio of the size to the arrangement pitch.

  According to the second electro-optical device of the present invention, during the operation, image display in the image region is performed in substantially the same manner as in the case of the first electro-optical device according to the present invention described above.

  Here, particularly in the second electro-optical device of the present invention, the arrangement pitch of the dummy pixel regions gradually decreases as the distance from one side of the pixel region increases. Therefore, the area of the surrounding area required for arranging the plurality of dummy pixel areas is reduced, and for example, the arrangement pitch of the first dummy pixel areas adjacent to the pixel area in the dummy pixel areas is defined as the arrangement pitch of the pixel areas. It is possible to prevent the electrical or optical properties of the dummy pixel portion and the pixel portion from changing discontinuously by almost or preferably matching completely. Specifically, when etching is performed to form wirings and storage capacitors in the pixel portion and the dummy pixel portion, it is caused by a difference in density of the wiring and storage capacitors due to a difference in size between the pixel region and the dummy pixel region. Etching spots that may occur can be reduced or eliminated. That is, it is possible to prevent the image quality from changing discontinuously near the boundary between the dummy pixel portion and the pixel portion, and to suppress an increase in the surrounding area occupied by the dummy pixel portion.

  In particular, when a serial-parallel converted or phase-expanded image signal is handled, a dummy pixel unit is interposed between a pixel unit block driven by a data line group adjacent to the dummy pixel region and a pixel unit block adjacent thereto. In accordance with the discontinuous change in electrical or optical properties between the pixel portion and the pixel portion, it is possible to prevent a stripe-like or stripe-like display defect from occurring.

  Here, “gradually smaller” means smaller continuously or intermittently or stepwise. In other words, the width Wi (i = 1,..., N (where n is a natural number of 3 or more)) in the direction intersecting the one side of the dummy pixel region becomes W1 ≧ W2 ≧ ... ≧ Wn as the distance from the one side increases. It means that the relationship changes so as to satisfy the relationship (W1> Wn) Therefore, typically, three or more dummy pixel regions according to the present invention are arranged in a direction intersecting the one side. In other words, the dummy pixel region is arranged in three rows or three columns or more along the one side.

  Further, in the second electro-optical device according to the present invention, in particular, the arrangement pitch of the second dummy pixel regions adjacent to the opposite side of the pixel region with respect to the first dummy pixel region adjacent to the pixel region in the dummy pixel region. The ratio of the size of the first dummy pixel area to the arrangement pitch of the second dummy pixel area is equal to the arrangement pitch of the third dummy pixel area adjacent to the second dummy pixel area opposite to the first dummy pixel area. It is larger than the ratio of the size to the arrangement pitch. That is, for example, the arrangement pitch of the second dummy pixel region is, for example, 80% of the arrangement pitch of the first dummy pixel region, and the arrangement pitch of the third dummy pixel region is, for example, 50 of the arrangement pitch of the second dummy pixel region. % Or half. In other words, the degree or degree to which the arrangement pitch of the first dummy pixel area changes from the arrangement pitch of the pixel area is the degree or degree to which the arrangement pitch of the second dummy pixel area changes from the arrangement pitch of the first dummy pixel area. Small compared to That is, in the immediate vicinity of the pixel region, the arrangement pitch does not change so much or does not change at all. In addition, the degree or degree to which the arrangement pitch of the second dummy pixel area changes from the arrangement pitch of the first dummy pixel area is the degree to which the arrangement pitch of the third dummy pixel area changes from the arrangement pitch of the second dummy pixel area. Or smaller than the degree. That is, the farther from the pixel region, the arrangement pitch changes relatively abruptly.

  For this reason, in order to form, for example, a wiring or a storage capacitor near the boundary between the second dummy pixel portion and the first dummy pixel portion, the arrangement pitch of the second dummy pixel region is smaller than the arrangement pitch of the first dummy pixel region. Etching can be performed uniformly. Furthermore, by increasing the arrangement pitch of the third dummy pixel area to, for example, half the arrangement pitch of the second dummy pixel area, it is possible to efficiently suppress an increase in the surrounding area occupied by the dummy pixel area.

  As described above, according to the second electro-optical device of the present invention, it is possible to prevent a discontinuous change in image quality near the boundary between the dummy pixel portion and the pixel portion, and the dummy pixel region occupies. It is possible to efficiently suppress the increase in the surrounding area and to effectively use the area on the substrate.

  In one aspect of the first or second electro-optical device of the present invention, when the arrangement pitch of the first dummy pixel regions is D1 and the arrangement pitch of the pixel regions is D0, the first dummy pixel region is The value of the ratio D1 / D0 of the size of the arrangement pitch of the first dummy pixel area to the arrangement pitch of the pixel area is given by a predetermined function F (D0) that monotonously decreases with respect to the arrangement pitch D0. It is arranged.

  According to this aspect, the larger the arrangement pitch D0 of the pixel area, the larger the arrangement pitch D0 of the first dummy pixel area given by the predetermined function F (D0) monotonically decreasing with respect to the arrangement pitch D0. The size ratio D1 / D0 is small. Here, “monotonically decreasing” means monotonically decreasing in a broad sense in terms of algebra, and for any D01 and D02 (where D01 <D02), F (D01) ≧ F (D02), and For some D01 and D02 (however, D01 <D02), this means that F (D01)> F (D02). That is, for example, when the pixel area arrangement pitch D0 is 20 μm, the ratio D1 / D0 of the size of the arrangement pitch of the first dummy pixel area to the arrangement pitch of the pixel area is ½ (ie, 50%). When the pixel area arrangement pitch D0 is 40 μm, the ratio D1 / D0 of the size of the arrangement pitch of the first dummy pixel area to the arrangement pitch of the pixel area is ¼ (that is, 25%). In other words, the arrangement pitch of the first dummy pixel areas is, for example, 10 um, regardless of whether the arrangement pitch of the pixel areas is, for example, 20 um or 40 um. Therefore, the arrangement pitch of the first dummy pixel area for preventing the discontinuous change in image quality near the boundary between the dummy pixel part and the pixel part is secured, and the increase of the surrounding area occupied by the dummy pixel area is increased. It becomes possible to suppress more efficiently according to the arrangement pitch and to effectively use the area on the substrate.

  In another aspect of the first or second electro-optical device of the present invention, when the arrangement pitch of the first dummy pixel regions is D1 and the arrangement pitch of the pixel regions is D0, the first dummy pixel region is The value of the ratio D1 / D0 of the size of the arrangement pitch of the first dummy pixel regions to the arrangement pitch of the pixel regions is the film thickness T of any one of the plurality of interlayer insulating films constituting the pixel portion. On the other hand, they are arranged so as to be given by a predetermined function G (T) that monotonously decreases.

  According to this aspect, for example, the first dummy pixel region is given by the predetermined function G (T) that monotonously decreases with respect to the film thickness T as the film thickness T of the interlayer insulating film constituting the dummy pixel portion decreases. The ratio of the size D1 / D0 of the pixel area to the array pitch of the pixel pitch is large. Here, “monotonically decreasing” means monotonically decreasing in a broad sense in terms of algebra. That is, for example, as the film thickness T of the interlayer insulating film is thinner, the arrangement pitch of the first dummy pixel regions approaches or completely matches the arrangement pitch of the pixel regions. Therefore, the image quality changes discontinuously in the vicinity of the boundary between the dummy pixel portion and the pixel portion, which is caused by etching spots at the time of etching to form wirings, storage capacitors, etc. in the pixel portion and the dummy pixel portion. This can be prevented. On the other hand, for example, the greater the thickness T of the interlayer insulating film, the smaller the arrangement pitch of the first dummy pixel regions than the arrangement pitch of the pixel regions. Therefore, the increase in the peripheral region occupied by the dummy pixel region is increased in the thickness T of the interlayer insulating film by the amount that the discontinuous change in image quality due to the etching spots is less likely to occur due to the thicker film thickness T of the interlayer insulating film. Accordingly, it is possible to more efficiently suppress and effectively use the region on the substrate.

  In another aspect of the first or second electro-optical device of the present invention, the arrangement pitch of the first dummy pixel regions is 80% or more of the arrangement pitch of the pixel regions.

  According to this aspect, the arrangement pitch of the first dummy pixel regions depends on the difference in size between the pixel region and the dummy pixel region during the etching for forming the wiring, the storage capacitor, and the like in the pixel unit and the dummy pixel unit. It is sufficiently large against etching spots that may be caused by the difference in density of wiring, storage capacitance, etc., so that it is possible to prevent the image quality from changing discontinuously near the boundary between the dummy pixel portion and the pixel portion. it can.

  In another aspect of the first or second electro-optical device of the present invention, the arrangement pitch of the second dummy pixel regions is 50% or less of the arrangement pitch of the first dummy pixel regions.

  According to this aspect, it is possible to more efficiently suppress an increase in the surrounding area occupied by the dummy pixel area and to effectively use the area on the substrate.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  Since the electronic apparatus of the present invention includes the above-described electro-optical device of the present invention, a projection display device, a television, a mobile phone, an electronic notebook, a word processor, a view capable of performing high-quality image display. Various electronic devices such as a finder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and a Conduction Electron-Emitter Display), an electrophoretic device, and a device using the electron emission device, DLP (Digital Light Processing) and the like can also be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.

(First embodiment)
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line H-H ′ in FIG. 1.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region positioned around the image display region 10a. Are bonded to each other. Here, the image display area 10a is an example of the “pixel area” according to the present invention.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. Further, the scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, a lead wiring 90 is formed for electrically connecting the external circuit connection terminal 102 to the data line driving circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like. .

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which wirings such as TFT (Thin Film Transistor) of pixel switching elements, scanning lines, and data lines are formed is formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a data line. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. A counter electrode 21 made of a transparent material such as ITO is formed on the light shielding film 23 so as to face the plurality of pixel electrodes 9a.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, etc. of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

  Next, the electrical configuration of the present embodiment will be described with reference to FIG. FIG. 3 is a circuit diagram showing equivalent circuits such as various elements and wirings in the pixel portion and the dummy pixel portion together with their peripheral drive circuits.

  In FIG. 3, each of a plurality of pixel portions 93 formed in a matrix that constitutes an image display area of the electro-optical device according to the present embodiment includes a pixel electrode 9a and a TFT 30 for controlling the switching of the pixel electrode 9a. The data line 6 a formed and supplied with an image signal is electrically connected to the source of the TFT 30. A scanning line 113 a to which a scanning signal is supplied is electrically connected to the gate of the TFT 30. The pixel electrode 9 a and the storage capacitor 70 are electrically connected to the drain of the TFT 30.

  The electro-optical device includes a data line driving circuit 101, a scanning line driving circuit 104, and a sampling circuit 7 in a peripheral area located around the image display area 10a. The data line driving circuit 101 is configured to sequentially supply sampling circuit driving signals to the sampling circuit 7 via the sampling circuit driving signal line 114. The sampling circuit 7 includes a plurality of single-channel TFTs 302 for sampling, that is, as sampling switches. Each single-channel TFT 302 has its source connected to the lead-out line 116 from the image signal line 115, its drain connected to the data line 6 a, and its gate connected to the sampling circuit drive signal line 114. Then, the image signals VID1 to VID6 on the image signal line 115 are simultaneously sampled at the timing of the sampling circuit driving signal supplied from the data line driving circuit 101, and are simultaneously supplied to the six data lines. As a result, the image signals S1, S2,..., Sn are sequentially written in groups of six data lines 6a. On the other hand, the scanning line driving circuit 104 is configured to supply the scanning signals G1, G2,..., Gm in a pulsed manner to the scanning lines 113a in a line-sequential order in this order at a predetermined timing.

  In the image display region 10a, scanning signals G1, G2,..., Gm are applied to the gate of the TFT 30 from the scanning line driving circuit 104 via the scanning line 113a in a line sequential manner. Image signals S1, S2,..., Sn supplied from the data line 6a are written to the pixel electrode 9a at a predetermined timing by closing the switch of the TFT 30 as a pixel switching element for a certain period. Image signals S1, S2,..., Sn written to the liquid crystal layer 50 (see FIG. 2) via the pixel electrode 9a are held for a certain period with the counter electrode 21 (see FIG. 2). The liquid crystal layer 50 modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signal is emitted from the electro-optical device as a whole. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 a and the counter electrode 21. As will be described in detail later, the storage capacitor 70 includes a pixel potential side capacitor electrode connected to the pixel electrode 9a and a fixed potential side capacitor electrode disposed opposite to the capacitor electrode with a dielectric film interposed therebetween. A part of the fixed potential capacitor line 300 arranged side by side with the scanning line 113a serves as such a fixed potential side capacitor electrode.

  The capacitor line 300 is electrically connected to the capacitor line potential supply terminal 303 outside the image display area 10a in which the pixel electrodes 9a are arranged. Accordingly, all the capacitor lines 300 are set to a stable fixed potential supplied from the capacitor line potential supply terminal 303 or a predetermined potential to be inverted, and good potential holding characteristics can be obtained in the storage capacitor 70. As such a potential source, a constant potential source of a positive power source or a negative power source supplied to a scanning line driving circuit or a data line driving circuit for supplying a scanning signal for driving the TFT 30 to the scanning line 113a may be used. A constant potential supplied to the counter electrode 21 of the counter substrate 20 may be used.

  Further, in FIG. 3, pixel electrodes 9a each shown by a white square are arranged in the image display area 10a, and dummy pixels shown by black squares are respectively shown in the dummy pixel areas spreading in the frame shape around the pixel electrodes 9a. Pixel electrodes 9d are arranged. The pixel electrode 9a and the dummy pixel electrode 9d have substantially the same configuration. Further, the pixel portion 93 including the pixel electrode 9a, the pixel switching TFT 30 and the storage capacitor 70 is substantially the same as the dummy pixel portion 93d including the dummy pixel electrode 9d, the pixel switching TFT 30 and the dummy storage capacitor 70d. It has a configuration. In other words, the dummy pixel unit 93 may be configured to simulate at least a part of the pixel unit 93. The configuration of the dummy pixel portion 93d will be described in detail later. In FIG. 3, more specifically, the peripheral two columns and the peripheral two rows of the image display area 10a are the dummy pixel portions 93d, and active matrix driving is performed in the dummy pixel area as in the image display area 10a. As a result, the portion in which the liquid crystal is driven incompletely generated near the edge of the image display area 10a in the active matrix driving is excluded from the actually displayed image display area 10a. As a result, it is possible to display a good image to every corner of the image display area 10a.

  Next, specific configurations of the pixel portion and the dummy pixel portion will be described with reference to FIGS. FIG. 4 is a plan view of adjacent pixel portions and dummy pixel portions. FIG. 5 is a cross-sectional view taken along the line A-A ′ of FIG. 4.

  In FIG. 4, on the TFT array substrate of the electro-optical device, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ′) are provided in a matrix, and the vertical and horizontal directions of the pixel electrodes 9a are provided. Data lines 6a and scanning lines 113a are provided along the boundaries.

  Similar to the pixel electrode 9a in the image display area 10a, a plurality of transparent dummy pixel electrodes 9d are provided in the dummy pixel area, and the data line 6a and the scanning line are respectively provided along the vertical and horizontal boundaries of the dummy pixel electrode 9d. 113a is provided. However, the dummy electrode 9d may not be transparent.

  4 and 5, the scanning line 113a is arranged so as to face the channel region 1a 'in the semiconductor layer 1a, and the scanning line 113a functions as a gate electrode. At the intersections of the scanning lines 113a and the data lines 6a, pixel switching TFTs 30 are provided in which the scanning lines 113a are arranged to face each other as channel electrodes in the channel region 1a '.

  In FIG. 5, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and includes a scanning line 113a, a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 113a, and scanning. Insulating film 2 including a gate insulating film that insulates line 113a from semiconductor layer 1a, low concentration source region 1b and low concentration drain region 1c of semiconductor layer 1a, high concentration source region 1d and high concentration drain region 1e of semiconductor layer 1a It has.

  As shown in FIGS. 4 and 5, the capacitor line 300 is formed on the scanning line 113a. The capacitor line 300 protrudes up and down in FIG. 4 along the data line 6a from the main line portion extending in a stripe shape along the scanning line 113a in plan view and from the main line portion at the intersection of the scanning line 113a and the data line 6a. And a protruding portion.

  The capacitor line 300 is made of a conductive light shielding film containing, for example, a metal or an alloy, constitutes an example of the upper light shielding film, and also functions as a fixed potential side capacitive electrode. The capacitor line 300 includes, for example, a simple metal, an alloy, a metal including at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). It consists of silicide, polysilicide, or a laminate of these. The capacitor line 300 may include other metals such as Al (aluminum), Ag (silver), Au (gold), and Cu (copper). Alternatively, the capacitor line 300 may have a multilayer structure in which a first film made of, for example, a conductive polysilicon film and a second film made of a metal silicide film containing a refractory metal are stacked.

  On the other hand, the relay layer 71 disposed opposite to the capacitor line 300 via the dielectric film 75 has a function as a pixel potential side capacitor electrode of the storage capacitor 70, and further, the high concentration of the pixel electrode 9 a and the TFT 30. It functions as an intermediate conductive layer that relay-connects the drain region 1e.

  As described above, the storage capacitor 70 includes the relay layer 71 as the pixel potential side capacitor electrode connected to the high concentration drain region 1e and the pixel electrode 9a of the TFT 30, and a part of the capacitor line 300 as the fixed potential side capacitor electrode. However, it is constructed by being opposed to each other through the dielectric film 75.

  Then, the data lines 6a extending in the vertical direction in FIG. 4 and the capacitor lines 300 extending in the horizontal direction in FIG. 4 are formed so as to cross each other, so that the data line 6a extends in the plane above the TFT 30 on the TFT array substrate 10. A lattice-shaped upper light-shielding film is formed as viewed, and defines an opening area of each pixel.

  As shown in FIGS. 4 and 5, the pixel electrode 9a is electrically connected to the high-concentration drain region 1e in the semiconductor layer 1a through the contact holes 83 and 85 by relaying the relay layer 71. .

  On the other hand, the data line 6a is electrically connected to the high-concentration source region 1d in the semiconductor layer 1a made of, for example, a polysilicon film through the contact hole 81. Note that the data line 6a and the high-concentration source region 1a can be relay-connected by a relay layer.

  In FIG. 5, the TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.

  As shown in FIG. 5, the TFT array substrate 10 is provided with a pixel electrode 9a, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is made of an organic film such as a polyimide film.

  On the scanning line 113a, a first interlayer insulating film 41 in which a contact hole 81 leading to the high concentration source region 1d and a contact hole 83 leading to the high concentration drain region 1e are respectively formed is formed.

  A relay layer 71 and a capacitor line 300 are formed on the first interlayer insulating film 41, and a second interlayer insulating film 42 in which a contact hole 81 and a contact hole 85 are formed is formed thereon. ing.

  A data line 6 a is formed on the second interlayer insulating film 42, and a third interlayer insulating film 43 in which a contact hole 85 leading to the relay layer 71 is formed is formed thereon. The pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 43 thus configured.

  On the other hand, the counter substrate 20 is provided with a counter electrode 21 on the entire surface of the counter substrate 20, and an alignment film 22 is further provided thereon (under the counter electrode 21 in FIG. 5). As with the pixel electrode 9a, the counter electrode 21 is made of a transparent conductive film such as an ITO film. A light-shielding film 23 is provided between the counter substrate 20 and the counter electrode 21 so as to cover at least a region facing the TFT 30 in order to prevent generation of light leakage current in the TFT 30.

  A liquid crystal layer 50 is provided between the TFT array substrate 10 thus configured and the counter substrate 20. The liquid crystal layer 50 is formed by sealing liquid crystal in a space formed by sealing the peripheral portions of the substrates 10 and 20 with a sealing material. The liquid crystal layer 50 takes a predetermined alignment state by the alignment film 16 and the alignment film 22 that have been subjected to an alignment process such as a rubbing process in a state where an electric field is not applied between the pixel electrode 9 a and the counter electrode 21. It is like that.

  Next, the arrangement of dummy pixel regions will be described with reference to FIGS. FIG. 6 is a schematic diagram showing the relationship between the arrangement pitches of the pixel area and the dummy pixel area according to this embodiment.

  4 and 6, particularly in the present embodiment, the arrangement pitch Dd of the dummy pixel region 94d is smaller than the arrangement pitch D0 of the pixel region 94a, and the arrangement pitch Dd of the dummy pixel region 94d is equal to that of the image display region 10a. It gets smaller gradually as you move away from one side. That is, as shown in FIG. 6, the arrangement pitches D0, D1, D2, and D3 of the pixel region 94a, the first dummy pixel region 94d1, the second dummy pixel region 94d2, and the third dummy pixel region d3 are D0> D1. The relationship of ≧ D2 ≧ D3 (more precisely, the relationship of D0> D1> D2 = D3 in FIG. 6) is satisfied. Therefore, the area of the surrounding area required for arranging the plurality of dummy pixel areas 94d is reduced. Therefore, it is possible to effectively use the area on the substrate. Alternatively, the substrate can be miniaturized.

  Further, in FIG. 6, the arrangement pitch D1 of the first dummy pixel region 94d1 is 80% of the arrangement pitch D0 of the pixel region 94a, and the data line 6a, the storage capacitor 70, etc. are formed. When the etching is performed, the difference between the ratio of the pixel area 94a and the first dummy pixel area 94d1 to the pixel area 94a or the first dummy pixel area 94d1 due to the difference in size between the pixel area 94a and the first dummy pixel area 94d1 is caused. It is large enough for etching spots that may occur. Therefore, it is possible to prevent the image quality from changing discontinuously near the boundary between the first dummy pixel region 94d1 and the pixel region 94, in other words, near the boundary between the surrounding region and the image display region 10a. Note that the image quality changes discontinuously near the boundary between the surrounding area and the image display area 10a as the arrangement pitch D1 of the first dummy pixel area 94d1 is larger than 80% of the arrangement pitch D0 of the pixel area 94a. This can be prevented more reliably. In particular, the block of the pixel unit 93 driven by the data line 6a group adjacent to the dummy pixel region 94d and the block of the pixel unit 93 adjacent to the dummy pixel region 94d due to serial-parallel conversion or phase expansion of the image signal. In the meantime, in accordance with the discontinuous change in the electrical or optical properties between the dummy pixel portion 93d and the pixel portion 93, it is possible to prevent a stripe-like or stripe-like display defect from occurring.

In addition, in FIG. 6, in the present embodiment, the arrangement pitch D2 of the second dummy pixel region 94d2 and the arrangement pitch D3 of the third dummy pixel region 94d3 are 50% of the arrangement pitch D1 of the first dummy pixel region 94d1. It has become. Therefore, the area occupied by the second dummy area 94d2 and the third dummy area 94d3 is small. Therefore, effective use of the area on the substrate can be achieved.
Note that the arrangement pitch D2 of the second dummy pixel region 94d2 and the arrangement pitch D3 of the third dummy pixel region 94d3 may be smaller than 50% of the arrangement pitch D1 of the first dummy pixel region 94d1. In that case, the area on the substrate can be used more effectively.

  Next, the arrangement of the first dummy pixel regions will be described with reference to FIGS. FIG. 7 is a graph showing the predetermined function F (D0).

  As shown in FIGS. 6 and 7, in the present embodiment, in particular, the first dummy pixel region 94d1 has a size ratio D1 / D0 of the arrangement pitch D1 of the first dummy pixel region 94d1 to the arrangement pitch D0 of the pixel region 94a. Are given by a predetermined function F (D0) monotonically decreasing with respect to D0. In FIG. 7, in this embodiment, the arrangement pitch D0 of the pixel region 94a is 12 μm, and as described above, the arrangement pitch D1 of the first dummy pixel region 94d1 is 80% of the arrangement pitch D0 of the pixel region 94a. is there. That is, the first dummy pixel region 94d1 is arranged such that the size ratio D1 / D0 is the value of F (D0) (that is, 0.8).

  In FIG. 7, when the arrangement pitch D0 of the pixel region 94a is 20 μm, the size ratio D1 / D0 is ½ (that is, 50%), and when the arrangement pitch D0 of the pixel region 94a is 40 μm. The size ratio D1 / D0 is 1/4 (ie 25%). In other words, the arrangement pitch D1 of the first dummy pixel region 94d1 is 10 μm regardless of whether the arrangement pitch of the pixel region 94a is 20 μm or 40 μm. Here, etching spots that may occur during the etching for forming the data line 6a, the storage capacitor 70, and the like are the data line 6a, the storage capacitor 70, and the like due to the difference in size between the pixel region 94 and the first dummy pixel region 94d1. This is due to the difference in density. However, if the first dummy pixel region 94d1 is arranged at an arrangement pitch or more given by F (D0), the image quality changes discontinuously near the boundary between the dummy pixel part 93d and the pixel part 93 due to etching spots. Can be prevented. Furthermore, the increase in the area occupied by the first dummy pixel area 94d can be more efficiently suppressed according to the arrangement pitch D0 of the pixel areas 94a, and the area on the substrate can be effectively used.

  In addition, the predetermined function F (D0) may be defined as a curve that changes as shown in FIG. 7 only for the arrangement pitch D0 within a specific range. In this case, for the arrangement pitch D0 outside the specific range, the value of the ratio D1 / D0 may be constant, and the arrangement pitch D1 may be constant regardless of the arrangement pitch D0. For example, if the arrangement pitch D0 is large to some extent, the inconvenience in the above-described etching or the like is difficult to be manifested. Therefore, the arrangement pitch D1 may be constant regardless of the arrangement pitch D0, and conversely, the arrangement pitch D0 may be small to some extent. For example, the arrangement pitch D1 may be constant as much as the arrangement pitch D0 because of the relationship with the limit of microfabrication at the time of manufacture.

  Next, with reference to FIG. 8, the arrangement of the first dummy pixel regions according to a modification of the present embodiment will be described. FIG. 8 is a graph showing the predetermined function G (T).

  As shown in FIG. 8, in the first dummy pixel region 94d1, the value of the ratio D1 / D0 of the size of the arrangement pitch D1 to the arrangement pitch D0 of the pixel region 94a is the interlayer insulating film 41 constituting the pixel portion 93, They may be arranged so as to be given by a predetermined function G (T) that monotonously decreases with respect to any one film thickness T among 42 and 43. In this case, as the film thickness T of the interlayer insulating films 41, 42 and 43 constituting the dummy pixel portion 93 is smaller, the pixel area 94 having the arrangement pitch D1 of the first dummy pixel area 94d1 is given by the predetermined function G (T). The ratio of the size ratio D1 / D0 to the arrangement pitch d0 is large. That is, as the film thickness T of the interlayer insulating films 41, 42, and 43 is thinner, the arrangement pitch D1 of the first dummy pixel region 94d1 approaches or completely coincides with the arrangement pitch D0 of the pixel region 94a. Therefore, in the vicinity of the boundary between the dummy pixel portion 93d and the pixel portion 93, which is caused by etching spots at the time of etching to form the data line 6a, the storage capacitor 70, etc. in the pixel portion 93 and the dummy pixel portion 93d, It is possible to prevent the image quality from changing discontinuously. On the other hand, the thicker the film thickness T of the interlayer insulating films 41, 42 and 43, the smaller the arrangement pitch D1 of the first dummy pixel regions 94d1 is smaller than the arrangement pitch D0 of the pixel regions 94a. Therefore, the increase in the peripheral region occupied by the dummy pixel region 94d is increased by the increase in the film thickness T of the interlayer insulating films 41, 42, and 43, so that the discontinuous change in image quality due to the etching spots is less likely to occur. According to the film thickness T of the films 41, 42 and 43, it is possible to more efficiently suppress the area on the substrate and effectively use it.

  Note that the predetermined function G (T) shown in FIG. 8 is given by G (T) = k × T + C (where k and C are constants), and the constants k and C are the types of interlayer insulating films or It depends on the etching rate. However, the predetermined function G (T) is not limited to a linear function of T.

  In addition, the predetermined function G (T) may be defined as a straight line that changes as shown in FIG. 8 only for the film thickness T within a specific range. In this case, for the film thickness T outside the specific range, the value of the ratio D1 / D0 may be constant, and the arrangement pitch D1 may be constant regardless of the film thickness T. For example, if the film thickness T is large to some extent, the above-described inconvenience in etching or the like is difficult to be manifested. Therefore, the arrangement pitch D1 may be constant regardless of the film thickness T or the arrangement pitch D0. If T is somewhat small, the arrangement pitch D1 may be constant together with the arrangement pitch D0 from the relationship with the limit of microfabrication during manufacturing.

(Second Embodiment)
A liquid crystal device according to a second embodiment will be described with reference to FIG. FIG. 9 is a schematic diagram having the same concept as FIG. 6 in the second embodiment. In FIG. 9, the same components as those in the first embodiment shown in FIGS. 1 to 7 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In FIG. 9, in the present embodiment, in particular, the first dummy pixel region 94d1 is arranged such that the arrangement pitch D1 almost or preferably completely coincides with the arrangement pitch D0 of the pixel region 94a. Therefore, when etching is performed to form the data line 6a and the storage capacitor 70 in the pixel portion 93 and the dummy pixel portion 93d, the data line 6a and the storage capacitor due to the difference in size between the pixel region 94a and the dummy pixel region 94d. Etching spots that may be caused by a difference in density such as 70 can be reduced or eliminated. Therefore, it is possible to prevent the electrical or optical properties of the dummy pixel portion 93d and the pixel portion 93 from changing discontinuously. Accordingly, it is possible to prevent the image quality from changing discontinuously near the boundary between the dummy pixel portion 93d and the pixel portion 93, and to suppress an increase in the surrounding region including the dummy pixel region 94d.

  Further, in FIG. 9, the arrangement pitches D0, D1, D2, and D3 of the pixel region 94a, the first dummy pixel region 94d1, the second dummy pixel region 94d2, and the third dummy pixel region d3 are D0 ≧ D1 ≧ D2 ≧ The relationship D3 (more precisely, the relationship D0 = D1> D2> D3 in FIG. 9) is satisfied. The arrangement pitch D2 of the second dummy pixel region 94d2 is 80% of the arrangement pitch D1 of the first dummy pixel region 94d1, and the arrangement pitch D3 of the third dummy pixel region 94d3 is the arrangement pitch D2 of the second dummy pixel region 94d2. Of 50%. That is, the ratio D2 / D1 (= 0.8) of the size of the arrangement pitch D2 of the second dummy pixel region 94d2 to the arrangement pitch D1 of the first dummy pixel region 94d1 is equal to the arrangement pitch D3 of the third dummy pixel region 94d3. It is larger than the ratio D3 / D2 (0.5) of the size of the second dummy pixel region 94d2 with respect to the arrangement pitch D2. Therefore, the data line 6a is arranged near the boundary between the second dummy pixel region 94d2 and the first dummy pixel region 94d1 and the arrangement pitch D2 of the second dummy pixel region 94d2 is smaller than the arrangement pitch D1 of the first dummy pixel region 94d1. In addition, etching for forming the storage capacitor 70 and the like can be performed uniformly. Further, since the arrangement pitch D3 of the third dummy pixel region 94d3 is 50%, that is, half of the arrangement pitch D2 of the second dummy pixel region 94d2, the increase in the surrounding region occupied by the dummy pixel region 94d is efficiently suppressed. Can do.

  As described above, according to the liquid crystal device according to the second embodiment, it is possible to prevent a discontinuous change in image quality in the vicinity of the boundary between the dummy pixel portion 93d and the pixel portion 93, and the dummy pixel region 94d. It is possible to efficiently suppress an increase in the surrounding area occupied by the substrate and to effectively use the area on the substrate.

(Electronics)
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 10 is a plan view showing a configuration example of the projector. As shown in FIG. 10, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  Next, an example in which the liquid crystal device is applied to a mobile personal computer will be described. FIG. 11 is a perspective view showing the configuration of the personal computer. In FIG. 11, the computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal device 1005 described above.

  Further, an example in which the liquid crystal device is applied to a mobile phone will be described. FIG. 12 is a perspective view showing the configuration of this mobile phone. In FIG. 12, a mobile phone 1300 includes a reflective liquid crystal device 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal device 1005, a front light is provided on the front surface thereof as necessary.

  In addition to the electronic devices described with reference to FIGS. 10 to 12, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Examples include a station, a videophone, a POS terminal, a device equipped with a touch panel, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), It can also be applied to an organic EL display or the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. An electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is sectional drawing of HH 'of FIG. FIG. 3 is a circuit diagram showing equivalent circuits such as various elements and wirings in a pixel portion and a dummy pixel portion together with peripheral drive circuits thereof. It is a top view of the pixel part and dummy pixel part which mutually adjoin. It is sectional drawing of A-A 'of FIG. It is a schematic diagram which shows the relationship between the magnitude | size of the arrangement | sequence pitch of the pixel area | region and dummy pixel area | region which concerns on 1st Embodiment. It is a graph which shows the predetermined function F (D0). It is a graph which shows the predetermined function G (T). It is a schematic diagram with the same meaning as FIG. 6 in 2nd Embodiment. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied. 1 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which an electro-optical device is applied. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 9a ... Pixel electrode, 113a ... Scan line, 6a ... Data line, 7 ... Sampling circuit, 10 ... TFT array substrate, 10a ... Image display area, 20 ... Counter substrate, 21 ... Counter electrode, 23 ... Light shielding film, 50 ... Liquid crystal Layer 93... Pixel portion 93 d dummy pixel portion 94 a pixel region 94 d 94 d 1 94 d 2 94 d 3 dummy pixel region 101 data line drive circuit 104 scan line drive circuit D 0, D 1, D 2 D3: Arrangement pitch

Claims (7)

On the board
A plurality of pixel portions arranged in the pixel region;
A plurality of dummy pixels which are respectively arranged in a plurality of dummy pixel regions constituting a surrounding region surrounding the pixel region when viewed in plan on the substrate and respectively simulate at least a part of the structure of the pixel portion. Department and
The arrangement pitch of the dummy pixel regions in at least one of the direction along the one side and the direction intersecting the one side in the region adjacent to at least one side of the pixel region in the surrounding region is the pixel. Smaller than the arrangement pitch of the areas,
The arrangement pitch of the dummy pixel regions gradually decreases with distance from the one side,
The ratio of the size of the arrangement pitch of the first dummy pixel region adjacent to the pixel region in the dummy pixel region to the arrangement pitch of the pixel region is opposite to the pixel region with respect to the first dummy pixel region. An electro-optical device, wherein an arrangement pitch of a second dummy pixel region adjacent to the first dummy pixel region is larger than a ratio of a size thereof to the arrangement pitch of the first dummy pixel region. On the board
A plurality of pixel portions arranged in the pixel region;
A plurality of dummy pixels which are respectively arranged in a plurality of dummy pixel regions constituting a surrounding region surrounding the pixel region when viewed in plan on the substrate and respectively simulate at least a part of the structure of the pixel portion. Department and
In the region adjacent to at least one side of the pixel region in the surrounding region, the arrangement pitch of the dummy pixel regions in at least one of the direction along the one side and the direction intersecting the one side is the one side Gradually gets smaller as you move away from
Of the dummy pixel regions, the arrangement pitch of the second dummy pixel region adjacent to the opposite side of the pixel region with respect to the first dummy pixel region adjacent to the pixel region is larger than the arrangement pitch of the first dummy pixel region. The ratio of the size is the ratio of the arrangement pitch of the third dummy pixel area adjacent to the second dummy pixel area on the opposite side of the first dummy pixel area to the arrangement pitch of the second dummy pixel area. An electro-optical device characterized by being larger than the above. When the arrangement pitch of the first dummy pixel areas is D1, and the arrangement pitch of the pixel areas is D0,
The first dummy pixel region has a predetermined function F () in which the value of the ratio D1 / D0 of the size of the arrangement pitch of the first dummy pixel region to the arrangement pitch of the pixel region monotonously decreases with respect to the arrangement pitch D0. The electro-optical device according to claim 1, wherein the electro-optical device is arranged as given by D 0). When the arrangement pitch of the first dummy pixel areas is D1, and the arrangement pitch of the pixel areas is D0,
In the first dummy pixel region, a value of a ratio D1 / D0 of the size of the arrangement pitch of the first dummy pixel region to the arrangement pitch of the pixel region is any of the plurality of interlayer insulating films constituting the pixel portion. The electro-optical device according to any one of claims 1 to 3, wherein the electro-optical device is arranged so as to be given by a predetermined function G (T) that monotonously decreases with respect to the single film thickness T.   5. The electro-optical device according to claim 1, wherein an arrangement pitch of the first dummy pixel regions is 80% or more of an arrangement pitch of the pixel regions.   The electro-optical device according to claim 1, wherein an arrangement pitch of the second dummy pixel regions is 50% or less of an arrangement pitch of the first dummy pixel regions. An electronic apparatus comprising the electro-optical device according to claim 1.

Images