JP2009042436A - Electro-optical device and electronic apparatus - Google Patents

Abstract

In an electro-optical device such as a liquid crystal device, for example, characteristics of a transistor constituting a peripheral circuit are improved.
An electro-optical device is provided on a substrate 10 in a peripheral region located around a pixel region in which a plurality of pixel electrodes 9a and a plurality of pixel electrodes are arranged, and (i) a first on the substrate. A plurality of channel regions 74C each having a channel length along the direction (X direction) and parallel to the second direction (Y direction) intersecting with the first direction at a predetermined interval; A semiconductor layer 74 having a source region 74S and a drain region 74D electrically connected to each other in common, and (ii) a gate electrode 71G extending in the second direction so as to overlap with a plurality of channel regions And a transistor 71 including:
[Selection] Figure 4

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  In this type of electro-optical device, a large number of scanning lines and data lines arranged vertically and horizontally in a display area composed of a plurality of pixels, and a large number of pixel electrodes corresponding to the respective intersections thereof are provided on the TFT substrate. It is done. Such an electro-optical device employs, for example, an active matrix driving method by TFT (Thin Film Transistor) driving, and a pixel switching TFT is provided for each pixel. The image signal supplied to the data line is supplied to the pixel electrode in accordance with the switching operation of the pixel switching TFT formed in each pixel, and an image is displayed in the display area. In addition, various peripheral circuits for controlling a plurality of pixels are formed in the peripheral region located around the display region on the TFT array substrate on which the TFT is formed. Such a peripheral circuit includes a transistor such as a TFT.

  For example, Patent Document 1 discloses a technique for preventing deterioration of TFT characteristics due to light by forming a channel of a TFT so that the channel length at the channel edge is longer than the channel length at the center of the channel. Yes.

Japanese Patent Laying-Open No. 2005-072135

  A pixel switching TFT provided in each pixel that mainly performs a relatively low-speed switching operation may have a relatively low transistor characteristic, while a relatively high-speed switching operation in a peripheral circuit and a current amplification operation. Alternatively, a transistor that performs a current control operation, a rectifying operation, a voltage holding operation, or the like is required to have relatively high transistor characteristics. Therefore, in order to improve the characteristics of the transistors constituting the peripheral circuit, it is common to form the transistors so that the channel width is relatively large and the channel length is relatively short. However, when the transistor is formed in this way, there is a technical problem that off-leakage current may increase or a space on the TFT substrate for forming the transistor may increase.

  The present invention has been made in view of, for example, the above-described problems. For example, an electro-optical device capable of improving the characteristics of transistors constituting a peripheral circuit and an electronic apparatus including such an electro-optical device. It is an issue to provide.

  In order to solve the above problems, an electro-optical device of the present invention is provided on a substrate in a peripheral region positioned around a pixel region in which the plurality of pixel electrodes and the plurality of pixel electrodes are arranged, (i) A plurality of channel regions each having a channel length along a first direction on the substrate and formed in parallel with a predetermined interval in a second direction intersecting the first direction; and A semiconductor layer having a source region and a drain region electrically connected to each other in common; and (ii) a gate electrode extending along the second direction so as to overlap the plurality of channel regions. A transistor.

  According to the electro-optical device of the present invention, the plurality of pixel electrodes are arranged in the pixel region or the pixel array region (or “image display region”) on the substrate, for example, at the intersection of the plurality of data lines and the plurality of scanning lines. For example, they are arranged in a matrix corresponding to the pixel switching TFTs arranged in the section. On the other hand, transistors that constitute part of the peripheral circuit are provided in a peripheral region located around the pixel region. For example, as in an image signal supply circuit that supplies an image signal to a data line, the potential of the pixel electrode is set. It is provided in the peripheral area for control.

  A semiconductor layer included in the transistor includes a plurality of channel regions and a source region and a drain region that are electrically connected to the plurality of channel regions in common. Each of the plurality of channel regions has a channel length along a first direction on the substrate (for example, a direction in which a plurality of data lines are arranged, that is, a direction in which each of the plurality of scanning lines extends or an X direction). Each of the plurality of channel regions is formed to extend along the first direction with a channel width of, for example, 1 μm. Further, the plurality of channel regions are along a second direction intersecting the first direction (for example, a direction in which each of the plurality of data lines extends, that is, a direction in which the plurality of scanning lines are arranged or a Y direction), For example, it is formed so as to be parallel with a predetermined interval of 1 um or the like. In other words, the plurality of channel regions are arranged at predetermined intervals along the channel width direction of each of the plurality of channel regions.

  The source region is formed, for example, so as to extend along the second direction adjacent to the plurality of channel regions, and is electrically connected to the plurality of channel regions in common.

  For example, the drain region is formed to extend along the second direction adjacent to the plurality of channel regions on the side opposite to the source region with respect to the plurality of channel regions. Commonly connected electrically.

  A gate electrode included in the transistor extends in the second direction so as to overlap with the plurality of channel regions, and functions as a common gate electrode for the plurality of channel regions.

  Therefore, the transistor has a configuration in which a plurality of transistor portions each including one channel region among the plurality of channel regions are arranged in parallel and electrically connected in parallel. Here, experimentally or experimentally, in a general transistor, as the channel width is narrower or narrower, the characteristics of the transistor per unit channel width can be improved. For example, the on-current per unit channel width can be increased, and the change in the source-drain current with respect to the gate voltage can be made steep. In other words, experimentally or empirically, in a typical transistor, an edge portion or an edge portion in the channel width direction of the channel region may have higher characteristics than a central portion in the channel width direction of the channel region. .

  Therefore, according to the present invention, a plurality of channel regions are formed at a predetermined interval between the source region and the drain region. Therefore, as in the conventional transistor, one channel region is provided between the source region and the drain region. As compared with the case where the transistor is formed, a larger number of edges in the channel width direction of the channel region of the transistor can be formed. Therefore, the characteristics of the transistor can be improved. That is, for example, by making the channel width of each of the plurality of channel regions relatively short and the predetermined interval relatively narrow, the characteristics of the transistor per occupied area can be improved. Therefore, the performance of the peripheral circuit can be improved, and finally, high-quality image display can be performed. In addition, since the characteristics of the transistor per occupied area can be improved, the transistor can be downsized and the electro-optical device can be downsized.

  In one aspect of the electro-optical device according to the aspect of the invention, the semiconductor layer may be elongated along the first direction with a predetermined width corresponding to the predetermined interval between adjacent channel regions of the plurality of channel regions. It has a plurality of formed openings.

  According to this aspect, the plurality of channel regions are separated from each other by the openings formed in the semiconductor layer in a longitudinal or slit shape along the channel length direction. In other words, the plurality of channel regions can be reliably separated from each other by the plurality of openings. That is, a plurality of channel regions in the transistor can be easily formed.

  In another aspect of the electro-optical device of the present invention, the channel width of each of the plurality of channel regions is 5 μm or less.

  According to this aspect, it becomes easy to form a large number of channel regions in a region where a transistor is to be formed, and the characteristics of the transistor can be reliably improved.

  In other words, if the channel width of each of the plurality of channel regions is longer than 5 μm, a sufficient number of channel regions for improving the characteristics of the transistor to the extent permitted by the product specifications are provided. There is a risk that it may be difficult to form the region in the region to be formed. However, according to this aspect, since the channel width of each of the plurality of channel regions is 5 μm or less, a sufficient number of channel regions for improving the characteristics of the transistor to the extent permitted by the product specifications are provided. Can be easily formed in the region to be formed.

  In another aspect of the electro-optical device of the present invention, the predetermined interval is 0.5 μm or more and shorter than the channel width.

  According to this aspect, the number of channel regions can be increased while securing a manufacturing margin, and the characteristics of the transistor can be reliably improved. That is, if the predetermined interval is smaller than 0.5 μm, adjacent channel regions may be formed continuously due to manufacturing errors in the manufacturing process, and the number of channel regions may be reduced. . For this reason, it becomes difficult to sufficiently improve the characteristics of the transistor. However, according to this aspect, since the predetermined interval is 0.5 μm or more, the channel regions adjacent to each other can be hardly or completely eliminated, and the characteristics of the transistor can be reliably improved. Can do.

  In another aspect of the electro-optical device of the present invention, the semiconductor layer includes a plurality of first LDD regions formed between each of the plurality of channel regions and the source region, and the plurality of channel regions. And a plurality of second LDD regions respectively formed between each of the first and second drain regions.

  According to this aspect, LDD (Lightly Doped Drain) regions are provided on both sides of each of the plurality of channel regions, that is, the transistor has an LDD structure (in other words, each transistor has a plurality of LDD structures). Of the transistor portion are electrically connected in parallel). Accordingly, a decrease in on-state current in the transistor can be suppressed, and off-state current can be reduced.

  In another aspect of the electro-optical device according to the aspect of the invention, a plurality of scanning lines and a plurality of data lines wired in the pixel region and the peripheral region are provided, and the plurality of pixel electrodes are imaged via the data line. An image signal supply circuit for supplying a signal, and the transistor constitutes a part of the image signal supply circuit.

  According to this aspect, the performance of the image signal supply circuit that requires a relatively high-speed switching operation can be improved.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since the electro-optical device of the present invention described above is provided, a projection display device, a television, a mobile phone, an electronic notebook, and a word processor capable of performing high-quality image display. Various electronic devices such as a viewfinder type or a monitor direct view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), and a display device using these electrophoretic device and electron emission device are realized. Is also possible.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.
<First Embodiment>
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the overall configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are surrounded by an image display region 10a as an example of the “pixel region” according to the present invention. They are bonded to each other by a sealing material 52 provided in a sealing region located in the area.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. In the present embodiment, the peripheral region is defined as a region farther than the frame region defined by the frame light shielding film 53 when viewed from the center of the TFT array substrate 10, and is a region including the frame region. That is, the peripheral area is an area on the TFT array substrate 10 excluding the image display area 10a, and is set as an area that does not emit light.

  A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. The scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, a lead wiring 90 is formed for electrically connecting the external circuit connection terminal 102 to the data line driving circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like. .

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which wirings such as pixel switching TFTs, scanning lines, and data lines are formed. In the image display area 10a, pixel electrodes 9a made of a transparent material such as ITO (Indium Tin Oxide) are provided in a matrix on the upper layer of wiring such as pixel switching TFTs, scanning lines, and data lines. An alignment film is formed on the pixel electrode 9a. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. The light shielding film 23 is formed of, for example, a light shielding metal film or the like, and is patterned, for example, in a lattice shape in the image display region 10a on the counter substrate 20. On the light shielding film 23, the counter electrode 21 made of a transparent material such as ITO is formed in a solid shape so as to face the plurality of pixel electrodes 9a. An alignment film is formed on the counter electrode 21. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  In the present embodiment, it is assumed that incident light incident on the liquid crystal layer 50 in the image display region 10a from the counter substrate 20 side is emitted as display light from the TFT array substrate 10 side.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

  Next, the electrical configuration of the liquid crystal device according to the present embodiment will be described with reference to FIG. FIG. 3 is a block diagram showing the electrical configuration of the liquid crystal device according to this embodiment.

  As shown in FIG. 3, the liquid crystal device according to this embodiment includes a peripheral circuit including a scanning line driving circuit 104, a data line driving circuit 101, and a sampling circuit 7 in the peripheral region on the TFT array substrate 10, and an image signal. Line 6 is provided. The data line driving circuit 101 and the sampling circuit 7 constitute an example of the “image signal supply circuit” according to the present invention.

  The scanning line driving circuit 104 is supplied with a Y clock signal CLY, an inverted Y clock signal CLYinv, and a Y start pulse DY. When the Y start pulse DY is input, the scanning line driving circuit 104 sequentially receives the scanning signal Gi (where i = 1,..., M) at a timing based on the Y clock signal CLY and the inverted Y clock signal CLYinv. Generate and output.

  The data line driving circuit 101 is supplied with an X clock signal CLX, an inverted X clock signal CLXinv, and an X start pulse DX. The data line driving circuit 101 includes a shift register. When the X start pulse DX is input, the data line driving circuit 101 has a timing based on the X clock signal CLX and the inverted X clock signal XCLXinv, and the sampling signal Si (where i = 1, 2,..., N) are sequentially generated and output.

  The sampling circuit 7 includes a plurality of sampling TFTs 71 provided for each data line 6a. The sampling TFT 71 is an example of the “transistor” according to the present invention, and includes a TFT including a semiconductor layer having a plurality of channel regions, as will be described in detail later.

  The source wiring 71S of the sampling TFT 71 is electrically connected to the image signal line 6, the gate wiring 71G of the sampling TFT 71 is electrically connected to the sampling signal line 97, and the drain wiring of the sampling TFT 71. 71D is electrically connected to the data line 6a. Each sampling TFT 71 receives an image signal VID via the image signal line 6 and also receives a sampling signal Si from the data line driving circuit 101 via the sampling signal line 97 (where i = 1, 2,... When n) is input, the image signal VID is sampled and applied to each data line 6a as a data signal Di (where i = 1, 2,..., n).

  As shown in FIG. 3, each of a plurality of pixels formed in a matrix that forms the image display region 10a of the TFT array substrate 10 includes a pixel electrode 9a and pixel switching for switching control of the pixel electrode 9a. The TFT 30 is formed, and the data line 6 a to which the data signal Di is supplied is electrically connected to the source of the pixel switching TFT 30. The data signal Di written to the data line 6a may be supplied line-sequentially in this order, or may be supplied for each group of a plurality of adjacent data lines 6a. Further, the scanning line 11 a is electrically connected to the gate of the pixel switching TFT 30. The scanning signals G1, G2,..., Gm are applied to the scanning line 11a in this order from the scanning line driving circuit 104 at a predetermined timing. In the present embodiment, for the sake of simplicity of explanation, the scanning signals G1, G2,..., Gm are configured to be applied to the scanning lines 11a in this order, but the scanning signals Gi (however, , I = 1, 2,..., M) may be applied to the scanning line 11a in any order. The pixel electrode 9a is electrically connected to the drain of the pixel switching TFT 30, and the pixel switching TFT 30 serving as a switching element is closed for a certain period so that the data signal Di supplied from the data line 6a is received. Write at a predetermined timing.

  A predetermined level of data signal Di (where i = 1, 2,..., N) written to the liquid crystal via the pixel electrode 9a is applied to the counter electrode 21 (see FIG. 2). (See FIG. 2). The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device as a whole.

  In order to prevent the image signal held here from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 a and the counter electrode 21. One electrode of the storage capacitor 70 is electrically connected to the drain of the pixel switching TFT 30 in parallel with the pixel electrode 9a, and the other electrode is electrically connected to the fixed potential capacitor line 400 so as to have a constant potential. It is connected to the.

  Next, a specific configuration of the sampling TFT according to this embodiment will be described with reference to FIGS. FIG. 4 is a plan view showing the configuration of the sampling TFT. FIG. 5 is a cross-sectional view taken along the line V-V ′ of FIG. 4. FIG. 6 is a plan view showing a configuration of a semiconductor layer constituting the sampling TFT. 7 is a cross-sectional view taken along the line VII-VII 'of FIG. In FIGS. 5 and 7, the scales of the respective layers and members are different from each other in order to make each layer and each member recognizable on the drawings.

  4 and 5, each sampling TFT 71 is formed on a base insulating film 12 provided on the TFT array substrate 10. The sampling TFT 71 includes a semiconductor layer 74, a gate wiring 71G, a gate insulating film 75, a source wiring 71S, and a drain wiring 71D.

  As shown in FIG. 6, the semiconductor layer 74 has a plurality of channel regions 74C, a plurality of LDD regions 74L1, a plurality of LDD regions 74L2, a source region 74S, and a drain region 74D. The plurality of LDD regions 74L1 are examples of the “plurality of first LDD regions” according to the present invention, and the plurality of LDD regions 74L2 are examples of the “plurality of second LDD regions” according to the present invention. is there. In addition, although the example in which the plurality of LDD regions 74L1 and LDD regions 74L2 are formed separately from each other corresponding to each channel region 74C is shown, one channel region 74C side of each of the source region 74S and the drain region 74D is shown. It may be formed as an LDD region and shared.

  Each of the plurality of channel regions 74C has a channel length along the X direction, and each channel region 74C is formed to extend along the X direction with a channel width Wc of about 1 μm. The plurality of channel regions 74C are arranged at a predetermined interval of about 1 μm along the channel width direction (that is, the Y direction).

  As shown in FIGS. 4, 6, and 7, the plurality of channel regions 74 </ b> C extend in the semiconductor layer 74 along the channel length direction (that is, the X direction) with a predetermined width Ws of about 1 μm and They are separated from each other by a plurality of slits 410 opened so as to be arranged along the channel width direction (that is, the Y direction). The plurality of slits 410 is an example of “a plurality of openings” according to the present invention. By the plurality of slits 410, the plurality of channel regions 74C can be reliably separated from each other.

  A source region 74S and a drain region 74D are formed on both sides of the plurality of channel regions 74C. An LDD region 74L1 is formed between the source region 74S and each of the plurality of channel regions 74C, and an LDD region 74L2 is formed between the drain region 74D and each of the plurality of channel regions 74C.

  The source region 74S, the drain region 74D, and the LDD regions 74L1 and 74L2 are impurity regions formed by implanting impurity ions into the semiconductor layer 74 by impurity implantation (ie, doping) such as ion implantation (ie, ion implantation). The LDD regions 74L1 and 74L2 are formed to have a lower impurity concentration than the source region 74S and the drain region 74D. According to such an impurity region, when the sampling TFT 71 is not operating, it is possible to reduce the off-current that flows to the source region and the drain region, and to suppress the decrease of the on-current that flows when the sampling TFT 71 is operating.

  The source region 74S is formed so as to extend along the Y direction, and is electrically connected in common to the plurality of channel regions 74C.

  The drain region 74D is formed to extend along the Y direction on the opposite side to the source region 74S with respect to the plurality of channel regions 74C, and is electrically connected to the plurality of channel regions 74C in common. It is connected.

  Note that the source region 74S and the drain region 74D may be formed in an island shape so as to be separated from each other for each channel region 74C, and electrically connected to the source wiring 71S and the drain wiring 71D via contact holes, respectively. . In the actual manufacturing process, the dimensions of the LDD regions 74L1 and 74L2 vary depending on the roundness of the corners of the plurality of slits 410. In this case, the LDD regions 74L1 and 74L2 are not rounded. Therefore, the problem of variation in LDD dimensions can be solved. Similarly, the opening regions of the plurality of slits 410 may be extended to the inside of the source region 74S and the drain region 74D. 4 and 5 again, the gate wiring 71G is formed of, for example, a conductive polysilicon film or the like on the upper layer side of the semiconductor layer 74 via the gate insulating film 75. The gate wiring 71G is formed so as to extend along the Y direction so as to overlap the plurality of channel regions 74C, and functions as a common gate electrode for the plurality of channel regions 74C. That is, the gate wiring 71G includes a gate electrode that overlaps each channel region 74C via the gate insulating film 75, and a channel is formed in each channel region 74C by an electric field from the gate wiring 71G. The gate wiring 71G is electrically connected to the sampling signal line 97 through a contact hole and a relay wiring (not shown) (see FIG. 3).

  4 and 5 (or FIG. 7), the source wiring 71S is formed of a metal film such as aluminum on the upper side of the semiconductor layer 74 via the interlayer insulating films 41 and 42. The source wiring 71S is electrically connected to the source region 74S through a contact hole 8S opened through the interlayer insulating films 41 and 42. The source wiring 71S is formed so as to extend along the direction in which the source region 74S extends (that is, the Y direction). The source wiring 71S is electrically connected to the image signal line 6 through a contact hole and a relay wiring (not shown) (see FIG. 3).

  The drain wiring 71D is formed of the same film as the source wiring 71S. That is, the drain wiring 71D is formed of a metal film such as aluminum on the upper side of the semiconductor layer 74 via the interlayer insulating films 41 and 42. The drain wiring 71D is electrically connected to the drain region 74D through a contact hole 8D opened through the interlayer insulating films 41 and 42. The drain wiring 71D is formed so as to extend along the direction in which the source region 74S extends (that is, the Y direction). The drain wiring 71D is electrically connected to the data line 6a through a contact hole and a relay wiring (not shown) (see FIG. 3).

  Therefore, the sampling TFT 71 has a configuration in which a plurality of transistor portions 71p each including the channel region 74C are arranged in parallel along the Y direction and are electrically connected in parallel.

  Interlayer insulating films 43 and 44 are sequentially stacked on the upper layer side of the source wiring 71S and the drain wiring 71D.

  A light shielding film 510 is formed on the lower layer side of the sampling TFT 71 through the base insulating film 12. The light shielding film 510 is provided for each sampling TFT 71, and is formed so as to overlap the sampling TFT 71 when viewed in plan on the TFT array substrate 10. The light shielding film 510 is, for example, a simple metal, an alloy, or a metal silicide containing at least one of refractory metals such as titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), and molybdenum (Mo). , Polysilicide or a light-shielding conductive material such as a laminate thereof. The light-shielding film 510 causes back-surface reflection on the TFT array substrate 10 or return light such as light emitted from another liquid crystal device by a multi-plate projector or the like and penetrating the composite optical system (from the lower side to the upper side in FIG. 5). Light) can be reduced from entering the sampling TFT 71, and the light leakage current in the sampling TFT 71 can be reduced. Further, the light shielding film 510 can reduce the return light from being reflected by the sampling TFT 71 and can reduce light leakage in the peripheral region.

  Here, if the sampling TFT 71 is formed as a conventional transistor (that is, a plurality of slits 410 are not formed in the semiconductor layer 74, and a plurality of channel regions 74C are channel regions having one continuous channel width W1). In the case of being formed), there is a possibility that the characteristics of the sampling TFT 71 cannot be improved to the extent permitted by the product specifications in a limited region where the sampling TFT 71 is to be formed. On the other hand, experimentally or experimentally, in a general transistor, the characteristics of the transistor per unit channel width can be improved as the channel width is narrower or narrower. For example, the on-current per unit channel width can be increased, and the change in the source-drain current with respect to the gate voltage can be made steep. In other words, experimentally or empirically, in a typical transistor, an edge portion or an edge portion in the channel width direction of the channel region may have higher characteristics than a central portion in the channel width direction of the channel region. . Therefore, particularly in the present embodiment, the sampling TFT 71 includes the semiconductor layer 74 having the plurality of channel regions 74C as described above, and each channel region 74C has a channel width Wc of about 1 μm in the X direction. It is formed so as to extend along. Further, the plurality of channel regions 74C are arranged at a predetermined interval of about 1 μm along the channel width direction (that is, the Y direction).

  Accordingly, in the sampling TFT 71, a plurality of channel regions 74C are formed at a predetermined interval of about 1 μm along the channel width direction between the source region 74S and the drain region 74D. Compared with the case where one channel region is formed between the source region 74S and the drain region 74D, more edge portions in the channel width direction (that is, the Y direction) of the channel region 74C in the sampling TFT 71 may be formed. it can. Therefore, the characteristics of the sampling TFT 71 can be improved. That is, since the plurality of channel regions 74C each having a relatively short channel width of about 1 μm are arranged at a relatively narrow predetermined interval of about 1 μm, the characteristics per unit area of the sampling TFT 71 can be improved. Is possible. Therefore, the performance of the sampling circuit 7 can be improved, and finally high-quality image display can be performed.

  4 and 6, in the present embodiment, the channel width Wc of each of the plurality of channel regions 74C is about 1 μm. Therefore, it becomes easy to form many channel regions 74C in the region where the sampling TFT 71 is to be formed, and the characteristics of the sampling TFT 71 can be improved with certainty.

  Note that the narrower the channel width Wc of each of the plurality of channel regions 74C, the more the characteristics of the sampling TFT 71 can be improved. The channel width Wc of each of the plurality of channel regions 74C is preferably 5 μm or less. In this case, it is possible to easily form a sufficient number of channel regions 74C in the region where the sampling TFTs 71 are to be formed to improve the characteristics of the sampling TFTs 71 to the extent permitted by the product specifications. it can.

  4 and 6, in the present embodiment, the predetermined width Ws of each of the plurality of slits 410 is about 1 um. Therefore, the number of channel regions 74C can be increased while securing a manufacturing margin, and the characteristics of the sampling TFT 71 can be reliably improved. The predetermined width Ws of each of the plurality of slits 410 is preferably 0.5 μm or more. If the predetermined width Ws is smaller than 0.5 μm, adjacent channel regions 74C may be continuously formed due to manufacturing errors in the manufacturing process, and the number of channel regions 74C may be reduced. is there. For this reason, it becomes difficult to sufficiently improve the characteristics of the sampling TFT 71. However, by forming the slit 410 with the predetermined width Ws of 0.5 μm or more, the channel regions 74C adjacent to each other can be hardly or completely formed, and the characteristics of the sampling TFT 71 can be ensured. Can be improved.

  As described above, according to the liquid crystal device according to the present embodiment, the characteristics of the sampling TFT 71 constituting the sampling circuit 7 can be improved, and finally a high-quality image can be displayed. .

In addition to or instead of the sampling TFT 71, a transistor included in the data line driving circuit 101 (for example, a transistor constituting a shift register included in the data line driving circuit 101) is configured in the same manner as the sampling TFT 71 described above. May be. That is, the transistor included in the data line driver circuit 101 may include a semiconductor layer having a plurality of channel regions arranged in the channel width direction at a predetermined interval. In this case, the characteristics of the transistors included in the data line driving circuit 101 can be improved.
<Electronic equipment>
Next, the case where the above-described liquid crystal device, which is an electro-optical device, is applied to various electronic devices will be described with reference to FIGS. Hereinafter, a projector using the liquid crystal device as a light valve will be described. FIG. 8 is a plan view showing a configuration example of the projector.

  As shown in FIG. 8, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R and 1110B.

  In addition, since light corresponding to each primary color of R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 8, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook , Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change. In addition, an electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is the II-II 'sectional view taken on the line of FIG. 1 is a block diagram illustrating an electrical configuration of a liquid crystal device according to a first embodiment. It is a top view which shows the structure of TFT for sampling. FIG. 5 is a cross-sectional view taken along line V-V ′ in FIG. 4. It is a top view which shows the structure of the semiconductor layer which comprises sampling TFT. It is the VII-VII 'sectional view taken on the line of FIG. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  6a ... data line, 7 ... sampling circuit, 9a ... pixel electrode, 10 ... TFT array substrate, 10a ... image display area, 11a ... scanning line, 20 ... counter substrate, 21 ... counter electrode, 50 ... liquid crystal layer, 71 ... sampling TFT, 71D ... drain wiring, 71S ... source wiring, 71G ... gate wiring, 74C ... channel region, 74D ... drain region, 74S ... source region, 101 ... data line driving circuit, 102 ... external circuit connection terminal, 104 ... scanning Line drive circuit, 410 ... slit, 510 ... light shielding film

Claims (7)

On the board
A plurality of pixel electrodes;
(I) a second direction that has a channel length along the first direction on the substrate and intersects the first direction, and is provided in a peripheral region located around the pixel region in which the plurality of pixel electrodes are arranged. A semiconductor layer having a plurality of channel regions formed in parallel with each other at a predetermined interval, and a source region and a drain region electrically connected in common to the plurality of channel regions, respectively (ii) And a transistor having a gate electrode extending along the second direction so as to overlap the plurality of channel regions.   The semiconductor layer has a plurality of openings formed in a longitudinal direction along the first direction with a predetermined width corresponding to the predetermined interval between adjacent channel regions of the plurality of channel regions. The electro-optical device according to claim 1.   The electro-optical device according to claim 1, wherein a channel width of each of the plurality of channel regions is 5 μm or less.   The electro-optical device according to claim 3, wherein the predetermined interval is 0.5 μm or more and shorter than the channel width. The semiconductor layer is
A plurality of first LDD regions each formed between each of the plurality of channel regions and the source region;
5. The electro-optical device according to claim 1, further comprising: a plurality of second LDD regions formed between each of the plurality of channel regions and the drain region. 6. . A plurality of scanning lines and a plurality of data lines wired in the pixel region;
An image signal supply circuit that is provided in the peripheral region and supplies an image signal to the plurality of pixel electrodes via the data line;
The electro-optical device according to claim 1, wherein the transistor constitutes a part of the image signal supply circuit.   An electronic apparatus comprising the electro-optical device according to claim 1.