KR100746362B1 - 패키지 온 패키지 기판 및 그 제조방법 - Google Patents
패키지 온 패키지 기판 및 그 제조방법 Download PDFInfo
- Publication number
- KR100746362B1 KR100746362B1 KR1020050122291A KR20050122291A KR100746362B1 KR 100746362 B1 KR100746362 B1 KR 100746362B1 KR 1020050122291 A KR1020050122291 A KR 1020050122291A KR 20050122291 A KR20050122291 A KR 20050122291A KR 100746362 B1 KR100746362 B1 KR 100746362B1
- Authority
- KR
- South Korea
- Prior art keywords
- package substrate
- package
- solder
- substrate
- metal bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 163
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910000679 solder Inorganic materials 0.000 claims abstract description 111
- 239000002184 metal Substances 0.000 claims abstract description 91
- 238000000034 method Methods 0.000 claims description 29
- 230000004907 flux Effects 0.000 claims description 11
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000000465 moulding Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 229940070259 deflux Drugs 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 238000007499 fusion processing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
Claims (17)
- 상면에 전자소자가 실장되는 바텀(bottom) 패키지 기판과;상기 바텀 패키지 기판의 상면에 결합되는 메탈 범프와;상기 바텀 패키지 기판의 상부에 적층되며, 하면에 솔더볼이 결합되는 탑(top) 패키지 기판을 포함하되,상기 메탈 범프는 상기 솔더볼의 위치에 대응하여 형성되며, 상기 메탈 범프의 높이는 상기 전자소자의 높이와 상기 솔더볼의 높이의 차이보다 크거나 같은 패키지 온 패키지 기판.
- 삭제
- 제1항에 있어서,상기 메탈 범프는 상기 솔더볼보다 융점이 높거나 같은 재질로 형성되는 패키지 온 패키지 기판.
- 제1항에 있어서,상기 메탈 범프는 볼 형태의 솔더(solder)를 리플로우(reflow)한 후 코이닝(coinning)하여 형성되는 패키지 온 패키지 기판.
- 제1항에 있어서,상기 메탈 범프는 상기 바텀 패키지 기판의 상면에 인쇄되는 솔더 페이스트를 리플로우(reflow)한 후 코이닝(coinning)하여 형성되는 패키지 온 패키지 기판.
- 제1항에 있어서,상기 탑 패키지 기판은 상기 솔더볼을 상기 메탈 범프에 접합시킴으로써 상기 바텀 패키지 기판에 결합되는 패키지 온 패키지 기판.
- 제6항에 있어서,상기 솔더볼은 상기 메탈 범프에 융착되어 접합되는 패키지 온 패키지 기판.
- (a) 바텀 패키지 기판 상의 소정의 위치에 메탈 범프를 형성하는 단계;(b) 상기 바텀 패키지 기판 상의 상기 메탈 범프가 형성되지 않는 위치에 전자소자를 실장하는 단계; 및(c) 상기 바텀 패키지 기판의 상부에, 하면에 솔더볼이 결합되는 탑(top) 패키지 기판을 적층하는 단계를 포함하되,상기 메탈 범프는 상기 솔더볼의 위치에 대응하여 형성되며, 상기 메탈 범프의 높이는 상기 전자소자의 높이와 상기 솔더볼의 높이의 차이보다 크거나 같은 것을 특징으로 하는 패키지 온 패키지 기판의 제조방법.
- 제8항에 있어서,상기 단계 (a) 이전에 상기 바텀(bottom) 패키지 기판의 상면에 플럭스(flux)를 도포하는 단계를 더 포함하는 패키지 온 패키지 기판의 제조방법.
- 제9항에 있어서,상기 단계 (a)는,(d) 상기 바텀(bottom) 패키지 기판의 상면에 솔더(solder)를 결합하는 단계;(e) 상기 솔더를 리플로우(reflow)하는 단계; 및(f) 상기 솔더를 코이닝(coinning)하는 단계를 포함하는 패키지 온 패키지 기판의 제조방법.
- 제10항에 있어서,상기 단계 (d)는 볼 형상의 솔더를 마운팅하는 단계를 포함하는 패키지 온 패키지 기판의 제조방법.
- 제10항에 있어서,상기 단계 (d)는 마스크를 이용하여 솔더 페이스트를 인쇄한 후, 상기 마스크를 제거하는 단계를 포함하는 패키지 온 패키지 기판의 제조방법.
- 제10항에 있어서,상기 단계 (e)는 상기 플럭스를 제거하는 단계를 더 포함하는 패키지 온 패키지 기판의 제조방법.
- 제10항에 있어서,상기 단계 (f)는 상기 메탈 범프의 높이가 균일하게 되도록 상기 솔더를 코이닝(coinning)하는 단계를 포함하는 패키지 온 패키지 기판의 제조방법.
- 삭제
- 제8항에 있어서,상기 단계 (c)는 상기 솔더볼을 상기 메탈 범프에 접합시킴으로써 상기 탑 패키지 기판을 상기 바텀 패키지 기판에 결합하는 단계를 포함하는 패키지 온 패키지 기판의 제조방법.
- 제8항에 있어서,상기 단계 (c) 이후에 상기 솔더볼 또는 상기 메탈 범프를 가열하여 상기 솔더볼과 상기 메탈 범프를 융착시키는 단계를 더 포함하는 패키지 온 패키지 기판의 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050122291A KR100746362B1 (ko) | 2005-12-13 | 2005-12-13 | 패키지 온 패키지 기판 및 그 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050122291A KR100746362B1 (ko) | 2005-12-13 | 2005-12-13 | 패키지 온 패키지 기판 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20070062645A KR20070062645A (ko) | 2007-06-18 |
KR100746362B1 true KR100746362B1 (ko) | 2007-08-06 |
Family
ID=38362897
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020050122291A Expired - Fee Related KR100746362B1 (ko) | 2005-12-13 | 2005-12-13 | 패키지 온 패키지 기판 및 그 제조방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100746362B1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101013545B1 (ko) * | 2007-07-26 | 2011-02-14 | 주식회사 하이닉스반도체 | 스택 패키지 및 그의 제조방법 |
US7960822B2 (en) | 2008-11-17 | 2011-06-14 | Samsung Electro-Mechanics Co., Ltd. | Package on package substrate |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20050009846A (ko) * | 2003-07-18 | 2005-01-26 | 삼성전자주식회사 | 스택 반도체 칩 비지에이 패키지 및 그 제조방법 |
-
2005
- 2005-12-13 KR KR1020050122291A patent/KR100746362B1/ko not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20050009846A (ko) * | 2003-07-18 | 2005-01-26 | 삼성전자주식회사 | 스택 반도체 칩 비지에이 패키지 및 그 제조방법 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101013545B1 (ko) * | 2007-07-26 | 2011-02-14 | 주식회사 하이닉스반도체 | 스택 패키지 및 그의 제조방법 |
US7960822B2 (en) | 2008-11-17 | 2011-06-14 | Samsung Electro-Mechanics Co., Ltd. | Package on package substrate |
KR101198411B1 (ko) * | 2008-11-17 | 2012-11-07 | 삼성전기주식회사 | 패키지 온 패키지 기판 |
Also Published As
Publication number | Publication date |
---|---|
KR20070062645A (ko) | 2007-06-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9263426B2 (en) | PoP structure with electrically insulating material between packages | |
US5477419A (en) | Method and apparatus for electrically connecting an electronic part to a circuit board | |
US6624004B2 (en) | Flip chip interconnected structure and a fabrication method thereof | |
US7091064B2 (en) | Method and apparatus for attaching microelectronic substrates and support members | |
JP4864810B2 (ja) | チップ内蔵基板の製造方法 | |
JP2018056234A (ja) | プリント回路板、電子機器及びプリント回路板の製造方法 | |
JP4729963B2 (ja) | 電子部品接続用突起電極とそれを用いた電子部品実装体およびそれらの製造方法 | |
US6657313B1 (en) | Dielectric interposer for chip to substrate soldering | |
JP2011171427A (ja) | 積層型半導体装置 | |
JPH06267964A (ja) | バンプの形成法 | |
JP5036397B2 (ja) | チップ内蔵基板の製造方法 | |
JP2008227310A (ja) | 2種類の配線板を有するハイブリッド基板、それを有する電子装置、及び、ハイブリッド基板の製造方法 | |
JPH0817972A (ja) | 部品の接続構造及びその製造方法 | |
KR100746362B1 (ko) | 패키지 온 패키지 기판 및 그 제조방법 | |
JP2005340230A (ja) | プリント配線板および部品実装体の製造方法 | |
JP2001230537A (ja) | ハンダバンプの形成方法 | |
JP2001257229A (ja) | バンプを有する電子部品及びその実装方法 | |
JP2008091650A (ja) | フリップチップ実装方法、および半導体パッケージ | |
KR100746365B1 (ko) | 플립칩 실장용 기판의 제조방법 | |
KR20070119790A (ko) | 폴리머 범프를 갖는 적층 패키지, 그의 제조 방법 및 모기판 실장 구조 | |
JP2006066811A (ja) | はんだ印刷用マスク、部品実装方法 | |
KR101133126B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
JP2007035870A (ja) | 半導体装置 | |
JP2751897B2 (ja) | ボールグリッドアレイ実装構造及び実装方法 | |
JP2008091553A (ja) | 回路基板及びその製造方法、並びに半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20051213 |
|
PA0201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20070131 Patent event code: PE09021S01D |
|
PG1501 | Laying open of application | ||
E701 | Decision to grant or registration of patent right | ||
PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20070727 |
|
GRNT | Written decision to grant | ||
PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20070730 Patent event code: PR07011E01D |
|
PR1002 | Payment of registration fee |
Payment date: 20070731 End annual number: 3 Start annual number: 1 |
|
PG1601 | Publication of registration | ||
G170 | Re-publication after modification of scope of protection [patent] | ||
PG1701 | Publication of correction | ||
LAPS | Lapse due to unpaid annual fee | ||
PC1903 | Unpaid annual fee |