KR100729558B1 - Test tray for semiconductor device inspection with latch plate - Google Patents

Abstract

The present invention relates to a test tray for semiconductor inspection having a latch plate which is applied to a test process performed to check whether a semiconductor device is operating normally before a packaging step, which is a final step of semiconductor device production, to fix the semiconductor device. A test tray for testing a semiconductor device, the test tray comprising: a base plate fastened such that a plurality of inserts having hollow seating holes formed on a support base formed at one side of a bottom surface of the semiconductor device are integrated with a maximum number; And a latch plate having a plurality of latch members inserted into the mounting hole of the insert of the base plate and protruding in one direction to support the semiconductor device seated on the support jaw of the mounting hole so as not to be separated from the outside.And a gong.

Therefore, the maximum number of inserts can be integrated on the base plate, so that the space occupied by the handler can test a large amount of semiconductor devices without making a difference.

Description

TEST TRAY FOR PROBING SEMICONDUCTOR DEVICE WITH INDEPENDENT LATCH PLATE}

1 is a perspective view showing an example of a test tray used in a semiconductor device test process according to the prior art

FIG. 2 is an enlarged perspective view of an insert of the test tray of FIG. 1.

3 is a perspective view illustrating a state in which the latch plate and the base plate of the test tray according to an embodiment of the present invention are separated;

4 is a perspective view showing an inner side surface of the latch plate in FIG.

5 is a perspective view showing the base plate in FIG.

Figure 6 is a side cross-sectional view showing a state in which the latch plate and the base plate in Figure 3 coupled

Figure 7 is a side cross-sectional view showing a state in which the match plate is coupled to the test tray according to an embodiment of the present invention

Explanation of symbols on the main parts of the drawings

100. Semiconductor device 200. Test tray

300. Base plate 310. Border

311.Guide member 312. Coupling hole

316. Hooks 320. Partition Walls

330. Insert fastening jaw 331. Insert insertion hole

360. Insert 361. Mounting hole

366. Fasteners 400. Latch Plates

410.Edge 411.Plate Guide Pin

416. Fastening holes 460. Latch members

461. Supporting Pieces

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test tray for inspecting semiconductor devices having an independent latch plate for preventing the flow of semiconductor devices seated on inserts using latch plates. The present invention relates to a test tray for inspecting a semiconductor device having an independent latch plate, which is applied to a test process performed to check whether the semiconductor device operates normally before the packaging step, which is a step, to prevent the flow of the device.

 1 is a perspective view showing an example of a test tray used in a semiconductor device test process according to the prior art.

As shown in FIG. 1, in a test handler (collectively referred to as semiconductor device test equipment) (not shown), the semiconductor device 1 is inserted into an insert 11 which is a pocket-type semiconductor device seating part of the test tray 10. To the test chamber (not shown) behind the handler. When the test tray 10 is located in the test chamber, the match plate 20 pushes the test tray 10 toward the high-fix board 30, which is a test device of the semiconductor device, and at this time, the match plate 20. The pusher block 11 pushes the upper surface of the semiconductor element 1 inserted into the insert 10 so that the semiconductor element 1 contacts the socket 32 on the high-fix board 30 and the semiconductor element 1 ) Will be tested.

FIG. 2 is an enlarged perspective view illustrating an insert of the test tray of FIG. 1.

As shown in FIG. 2, when the test tray 10 to which the insert 11 is fastened is moved for testing, the semiconductor device 1 may be inserted into the insert 11 due to the shock inside the test handler or the rotation of the test tray 10. The latch 13 serves to hold the semiconductor device 1 so as not to fall out of the hollow seating portion 12.

As described above, the insert 11 because the latch 13 and the toggle 14, which are mechanisms for preventing the element 1 from being disengaged from the insert 11 during transportation inside the handler, must exist essentially. There was a problem of limiting the utilization of the space on).

Therefore, more inserts 11 are fastened to a limited space of the test tray 10 by inserts 11, which require space for the latch 13 and toggle 14, so that more semiconductor elements 1 can be obtained. There is a problem that is structurally difficult to test.

In addition, in order to insert the semiconductor device 1 into the insert 10, the toggle 14 is essentially pressed, and the latch 13 is moved so that the semiconductor device 1 is seated. There is a problem that occurs when the semiconductor device 1 is not seated correctly due to the difference in the opening time, there is a problem that a separate mechanism for pressing the toggle 14 is required.

In addition, there is a need to test as many semiconductor devices 1 as possible in one handler as the amount of semiconductor usage increases gradually, and the above-described prior art does not meet these requirements.

The present invention has been proposed to solve the problems in the prior art as described above, and the space occupied by the handler can be tested with a latch from the insert so that it is possible to test a large amount of semiconductor devices without making a difference. As the toggle is separated, a larger number of devices can be loaded on the base plate of the test tray that has been used previously, and a test tray that can fundamentally prevent the semiconductor device from being released from the insert due to the malfunction of the latch or the toggle To provide.

 This object of the present invention is a test tray for the test of the semiconductor device in the test handler, the plurality of inserts formed with a hollow seating hole that is seated on the supporting jaw formed on one side of the center bottom of the semiconductor device Base plate fastened so that the number is integrated, and a plurality of latch members protruding in one direction are inserted into the mounting hole of the insert of the base plate to support the semiconductor device seated on the support jaw of the mounting hole so as not to be separated to the outside. It is achieved by a test tray for inspecting a semiconductor device having a latch plate according to the present invention comprising a latch plate engaged.

An example of a test tray for inspecting a semiconductor device having a latch plate according to the present invention for achieving the above object of the present invention will be described in detail in the following configurations and effects.

According to a preferred embodiment of the present invention for achieving the above object, in a test tray for the test of the semiconductor device in the test handler, the semiconductor device is a hollow seated on the supporting jaw formed on one side of the center bottom The base plate is fastened so that the maximum number of inserts formed with a mounting hole of the plurality of inserts, and the semiconductor element is inserted into the seating hole of the insert of the base plate to support the semiconductor device seated on the support jaw of the seating hole is not separated A test tray is provided, comprising a latch plate having a plurality of latch members protruding in one direction and fastened therein.

Preferably, the latch plate has a hollow 'c' shaped support having a length spaced apart from the upper surface of the semiconductor element seated on the support jaw of the seating hole of the insert of the base plate by a minute gap. A side protrusion is formed so that the latch plate supports the semi-elementary element seated in the insert when combined with the base plate.

Hereinafter, a test tray according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

 3 is a perspective view illustrating a state in which a latch plate and a base plate of the test tray are separated according to an embodiment of the present invention, FIG. 4 is a perspective view illustrating an inner side surface of the latch plate in FIG. 3, and FIG. 6 is a perspective view illustrating a base plate, and FIG. 6 is a side cross-sectional view illustrating a state in which a latch plate and a base plate are coupled to each other in FIG. 3.

3 to 6, the test tray 200 according to an embodiment of the present invention has a hollow seating hole in which the semiconductor device 100 is seated on a support jaw 362 formed at one side of the bottom surface of the center. 361 is formed and each of the base plates 300 are independently adjacently fastened so that a plurality of inserts 360 having no latches and toggles to prevent the flow of the semiconductor device 100 are integrated. The plurality of latch members 460 protruding in one direction are inserted into the mounting holes 361 of the insert 360 to support the semiconductor device 100 seated on the supporting jaw 362 of the mounting holes so as not to be separated out. It is configured to include a latch plate 400 having a latch function that is fastened inside to support the semiconductor device 100.

By the structure of the insert and the latch plate 400 as described above, a larger number of inserts 360 can be adjacently fastened to the limited area of the base plate 300, so that a large amount of semiconductor devices can be obtained even within the limited area of the base plate 300. It becomes possible to test 100.

On the other hand, the latch plate 400 of the test tray 200 according to an embodiment of the present invention basically has the same dimensions as the base plate 300 of the test tray 200 when moving in the test handler (not shown) It is coupled to the base plate 300 is subjected to the semiconductor device 100 test process.

In addition, the base plate 300 is formed with several partition walls 320 for partitioning the inside of the edge 310 at a predetermined interval, and the inner side of the edge 310 and both side surfaces of the partition wall 320 are Each insert 360 is inserted into the insert fastening jaw 330 extending at a predetermined interval so as to be adjacently fastened in one direction.

At this time, the upper surface of the insert 360 which is fastened to the insert fastening jaw 330 of the base plate 300 is inserted downward so as to be lower than the upper surface of the edge 310 and the partition wall 320.

An insert insertion hole 331 is formed in the insert fastening jaw 330 of the base plate 300 so that the hollow fastening protrusion 366 extending to one side of the insert 360 is inserted into the insert insertion hole of the fastening jaw ( 331 is fixed after being inserted.

Preferably, one side of the latch member 460 of the latch plate 400 has a fine gap with an upper surface of the semiconductor device 100 seated in the mounting hole 361 of the insert 360 of the base plate 300. Hollow '-' shaped support piece 461 having a length spaced apart is projected.

That is, the latch member 460 of the latch plate 400 is latch plate so that when the latch plate 400 is coupled to the base plate 300, the latch member 460 is in contact with the insert 360 of the base plate 300. A support piece 461 is fastened to a corresponding position on the inner side of the surface 400 and is spaced apart from the semiconductor device 100 by a predetermined distance to support the semiconductor device 360 not to flow in the insert 360.

Reference numerals 313, 317, 368 and 468 are fasteners or pins which are inserted into and fixed in the fixing holes on one side of the guide member 311, the hook 316, the insert 367 and the latch member 460, respectively. .

At least one guide member 311 having a coupling hole 312 formed at one side of the base plate rim 310 is fastened to a hook 316 protruding upward at the other side, and an edge 410 of the latch plate 400. ), The plate guide pin 411 and the fastening hole 416 are respectively formed at positions corresponding to the coupling hole 312 and the hook 316 of the guide member of the base plate rim 310.

Through this, the latch plate 400 is vertically lifted up and down from the upper portion of the base plate 300 and coupled to the upper surface of the base plate 300 to be interviewed.

 That is, when the latch plate 400 is coupled to the base plate 300 of the test tray 200 according to an embodiment of the present invention, the latch members 460 fastened to the inner side of the latch plate 400 are End portions of the plate-shaped support pieces 461 (the shapes of the support pieces are not limited thereto) protruding in the vertical direction are inserted into the insert 360 while the semiconductor device 100 mounted in the insert 360. ) Spaced slightly away from the top surface.

Therefore, when the latch plate 400 is coupled to the base plate 300 of the test tray 200 as described above, the end of the support member 461 of the latch member 460 does not directly contact the upper surface of the semiconductor device 100. Since only the edge 310 of the base plate 300 and the upper surface of the partition wall 320 are interviewed with the inner surface of the latch plate 400, the shock generated by the coupling is seated in the insert 360 and the insert. Since it is not delivered to the semiconductor device 100, there is no need to additionally provide an elastic member for buffering.

 7 is a side cross-sectional view showing a state in which a match plate is coupled to a test tray according to an embodiment of the present invention.

As shown in FIG. 7, a latch member supporting the semiconductor device 100 without directly contacting the upper surface of the semiconductor device 100 in a state where the latch plate 400 is first coupled to the base plate 300 is supported. The semiconductor device 100 in a state of being seated in the seating hole 361 of the insert 360 by the piece 461 is not detached to the outside by impact or rotation during movement in the handler.

Thereafter, the match plate 600 is coupled to the latch plate 400 so that the semiconductor element pusher block 610 of the match plate 600 passes through the central hole of the latch member 460 to seat the insert 360. The end of the semiconductor device pusher block 610 is pushed while being inserted into the hole 361 and contacts the upper surface of the semiconductor device 100.

Therefore, the semiconductor device 100 is tested by the semiconductor device 100 while contacting the socket (not shown) on the high-fix board (not shown) by the semiconductor device pusher block 610 of the match plate 600. You lose. That is, when the match plate 600 is coupled to the test tray 200 according to the present invention, the semiconductor device 100 is controlled to move in the vertical direction in the insert 360.

Reference numeral 620 denotes that the match plate 600 is simultaneously inserted together with the semiconductor element pusher block 610 to fix the insert 360 so that the match plate 600 is inserted into the correct position upon coupling to the test tray 200 according to the present invention. Insert guide pin to guide the accuracy of semiconductor device test.

 Reference numerals 367 and 467 are guide holes formed at one side of the insert 360 and the latch member 460 through which the insert guide pin 620 passes and is inserted.

The present invention has been described above with reference to the accompanying drawings and embodiments, but the present invention is not limited to the specific embodiments, and modifications of the present invention can be easily carried out by those skilled in the art to which the present invention pertains. It is obvious that it belongs to the technical idea of this invention.

The test tray according to the present invention can be further loaded with a semiconductor device in the space on the base plate occupied by the latch of the insert in the prior art by having a separate independent latch plate by separating the latch fixed to the insert fastened on the base plate In other words, since a large amount of inserts can be accumulated on the base plate, the space occupied by the handler can test a large amount of semiconductor devices without any difference from the existing handler.

In addition, the test tray according to the present invention has a structure in which an insert is not provided with a latch or a toggle, and an independent latch plate is coupled to the base plate, so that the end of the latch member support piece of the latch plate does not directly contact the semiconductor device. Since it is formed to be spaced apart from the upper surface by a predetermined distance, i.e., a minute gap, it is possible to prevent the shock from being transmitted to the semiconductor element by the end of the support piece at the moment when the latch plate is coupled to the base plate, the latch plate to the base plate Since the shock is not transmitted to the semiconductor device when combined, there is no effect that the additional installation of the elastic member for the shock mitigation.

In addition, since the insert is not provided with the latch or the toggle, there is an effect that it is possible to fundamentally prevent the semiconductor device from being released from the insert due to the malfunction of the latch or the toggle.

Claims (4)

delete delete delete In the test tray for testing the semiconductor device in the test handler, The inner side of the edge 310 is integrated such that a plurality of inserts 360 having a hollow seating hole 361 formed on the support base 362 formed at one side of the bottom surface of the semiconductor device 100 are integrated in a maximum number. A plurality of partition walls 320 partitioning at predetermined intervals are formed, and insert fastening jaws 330 protruding at predetermined intervals so that the respective inserts are inserted and adjacently fastened in one direction to the inner side of the edge and both sides of the partition wall. The base plate 300 is formed, A hollow support piece 461 having a length that is inserted into the seating hole of the insert and is spaced apart from the top surface of the semiconductor device by a microgap so that the semiconductor device seated on the support jaw of the seating hole is not separated to the outside is supported in one direction. A plurality of latch members 460 protruding into the configuration is configured to include a latch plate 400 fastened to the inside, At least one guide member 311 having a coupling hole 312 formed at one side of the base plate rim 310 is fastened to a hook 316 protruding upward at the other side, and at the rim 410 of the latch plate. A plate guide pin 411 and a fastening hole 416 are respectively formed at positions corresponding to the coupling hole and the hook of the guide member of the base plate rim, whereby the latch plate 400 is the base plate 300 A test tray for testing a semiconductor device having a latch plate, which is lifted up and down at an upper portion of the base plate and is coupled to an upper surface of the base plate.

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