KR100723517B1 - A counter that maintains a counting value and outputs it, and a phase locked loop having the counter - Google Patents

Abstract

A counter for holding and outputting a counting value and a phase locked loop having the counter are disclosed. The counter according to the invention has a selector and a counting part. The selector selects and outputs a clock signal or a hold signal in response to a predetermined selection signal. The counting unit counts the clock signal, maintains the number of clocks counting the clock signal in response to the hold signal, and then outputs the number of clocks. The counter outputting after maintaining the counting value according to the present invention has an advantage of stably outputting the counting value regardless of the propagation delay time.

Description

Counter keeping counting value and Phase Locked Loop having the counter

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a view showing a counter for outputting after maintaining a counting value according to the present invention.

2 is a timing diagram illustrating an operation of the counter of FIG. 1.

3 is a block diagram illustrating a phase locked loop having a counter of FIG. 1.

4 is a diagram illustrating a relationship between an oscillation control voltage and an oscillation frequency of the phase locked loop of FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter and a phase locked loop (PLL), and more particularly to a counter for outputting after maintaining a counting value and a phase locked loop having the counter.

A general asynchronous counter has a plurality of flip flops. A general asynchronous counter counts the clock signal while sequentially delivering a clock signal through the flip-flops.

However, in the general asynchronous counter, the propagation delay time occurs because the clock signals are sequentially transmitted. Thus, the timing at which each flip-flop receives a clock signal is different. That is, during a certain time period, some flip-flops receive and count clock signals, while other flip-flops do not yet receive clock signals.

Therefore, if flip-flops output counting values in the specific time interval, there is a problem in that the clock number of the clock signal cannot be counted correctly. That is, if all the flip-flops output counting values before receiving the clock signal, the flip-flop that has not received the clock signal may not output the correct counting value.

In particular, when a general asynchronous counter counts a high frequency clock signal, the propagation delay time at which the clock signal is transmitted through flip-flops is relatively long compared to the period in which the clock signal is input. Therefore, the phenomenon of not being able to output an accurate counting value is more problematic.

The phase locked loop is a circuit that outputs an oscillating clock signal having a desired locking frequency. The phase locked loop compares the frequency of the oscillation clock signal and the locking frequency currently being output, and varies the frequency of the oscillation clock signal according to the comparison result, thereby outputting an oscillation clock signal having a desired locking frequency. In order to determine whether the oscillation frequency of the oscillation clock signal coincides with the locking frequency, the phase locked loop needs to know exactly the frequency of the oscillation clock signal that is currently output. However, as described above, a general asynchronous counter cannot accurately count a high frequency clock signal. Therefore, the phase locked loop does not find the exact frequency of the oscillating clock signal. Accordingly, a phase locked loop having a general asynchronous counter has a problem in that it cannot output an oscillating clock signal having a desired locking frequency.

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An object of the present invention is to provide a counter that outputs after maintaining a counting value.

Another object of the present invention is to provide a phase locked loop having a counter that maintains a counting value and outputs it.

A counter according to the present invention for achieving the above technical problem is provided with a selection unit and a counting unit. The selector selects and outputs a clock signal or a hold signal in response to a predetermined selection signal. The counting unit counts the clock signal, maintains the number of clocks counting the clock signal in response to the hold signal, and then outputs the number of clocks.

The counting portion has a plurality of latch means. The plurality of latch means are connected to each other in series, and output the clock number by one bit, respectively, and maintain the clock number by one bit in response to the hold signal, and then output the held clock number.

The selector outputs the hold signal after outputting the clock signal.

The clock signal and the hold signal are sequentially transmitted through the plurality of latch means.

The counting unit may output the number of clocks maintained after the propagation delay time for transmitting the clock signal input before the hold signal is input to all of the plurality of latch means.

Each latch means may be a first to N th flip flop.

The hold signal may be a ground voltage.

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In accordance with another aspect of the present invention, a phase locked loop includes a voltage controlled oscillator, a counter, and a frequency state controller. The voltage controlled oscillator selects a band in response to a band selection signal and outputs an oscillation clock signal corresponding to the oscillation control voltage. The counter outputs an oscillation frequency by counting the oscillation clock signal, and outputs after maintaining the oscillation frequency for a predetermined time in response to a hold signal. The frequency state controller outputs the band selection signal by comparing the oscillation frequency with a reference frequency.

According to another aspect of the present invention, there is provided a method of counting a clock signal, in response to a predetermined selection signal, selecting and outputting a clock signal or a hold signal, receiving the clock signal, and counting the clock signal. And maintaining the number of clocks counting the clock signal in response to the hold signal and outputting the number of clocks.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a view showing a counter for outputting after maintaining a counting value according to the present invention.

Referring to FIG. 1, the counter 100 according to the present invention includes a selector 110 and a counting unit 120.

The selector 110 selectively outputs the clock signal CLK or the hold signal HOLD in response to the predetermined selection signal SEL. The selector 110 may be a multiplexer.
The counting unit 120 counts the clock signal CLK and maintains the number of clocks counting the clock signal CLK in response to the hold signal HOLD. The counting unit 120 may include first to N th latch means FF1 to FFn connected to each other in series. The latch means FF1 to FFn output the clock numbers C1 to Cn of the clock signal CLK by 1 bit, respectively. In response to the hold signal HOLD, the clock numbers C1 to Cn are each maintained by one bit and then output.

In more detail, the selector 110 outputs the clock signal CLK to the counting unit 120 and then outputs the hold signal HOLD to the counting unit 120. The clock signal CLK and the hold signal HOLD are sequentially transmitted through the plurality of latch means FF1 to FFn of the counting unit 120. The plurality of latch means FF1 to FFn is held after the propagation delay time for transmitting the clock signal CLK, which is input before the hold signal HOLD, to all the plurality of latch means FF1 to FFn. Outputs one clock number (C1 to Cn).

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Referring back to FIG. 1, each of the first to Nth latch means FF1 to FFn may be a first to Nth flip flop FF1 to FFn.

In addition, each of the first to Nth flip-flops FF1 to FFn may be first to N-th D-flip flops FF1 to FFn. The first to Nth D-flip flops FF1 to FFn are connected to a D input terminal and a Qb input terminal, respectively.

The first D-flip flop FF1 receives the hold signal HOLD output from the selector 110 through the C input terminal, and the hold signal HOLD through the Qb output terminal to the second D-flip flop FF2. Outputs K-th (k is a natural number of 2 or more and N-1 or less) D-flip flops (FF2 to FFn-1) are C input terminals for the hold signal HOLD output from k-1 D-flip flop (FFk-1). And a hold signal HOLD is output through the Qb output terminal to the k + 1 D-flip-flop FFk + 1. The N-th D-flip flop FFn receives the hold signal HOLD from the N-th D-flip flop FFn-1 through the C input terminal.

In addition, each of the first to Nth flip-flops FF1 to FFn may be the first to Nth T-flip flops FF1 to FFn. The first T-flip flop FF1 receives the hold signal HOLD output from the selector 110 through the T input terminal and the hold signal HOLD through the Qb output terminal to the second T-flip flop FF2. )

K-th (k is a natural number of 2 or more and N-1 or less) T-flip flops (FF2 to FFn-1) denote T-hold signals HOLD output from k-1 T-flip flop (FFk-1). Received through the input terminal, and outputs the hold signal (HOLD) through the Qb output terminal to the k + 1 T- flip-flop (FFk + 1). The N-th T-flip flop FFn receives the hold signal HOLD from the N-th T-flip flop FFn-1 through the T input terminal.

2 is a timing diagram illustrating an operation of the counter of FIG. 1.

1 and 2, the operation of the counter 100 according to the present invention is described in detail. For convenience of explanation, it is assumed below that the counter of FIG. 1 includes three flip-flops. That is, n = 3, and the clock numbers C1 to C3 of the clock signal are 3 bits.
The selector 110 outputs the clock signal CLK (counting mode) and then outputs the hold signal HOLD (output mode). The first to third flip-flops FF1 to FF3 of the counting unit 120 sequentially count the clock signal CLK. In more detail, the first flip-flop FF1 inverts the logic state of the clock number C1 stored in synchronization with the rising edge or the falling edge of the clock signal CLK. The second and third flip-flops FF2 and FF3 are stored in synchronization with the rising edge or falling edge of the clock numbers C1 and C2 stored in the previous stage flip-flops FF1 and FF2. Reverse the logic states of (C2, C3).

When the counting mode ends and the output mode starts, the selector 110 stops outputting the clock signal CLK and outputs a hold signal HOLD having a constant logic level. The hold signal HOLD may be a ground voltage. The first to third flip-flops FF1 to FF3 sequentially perform a counting operation on the clock signal CLK, and then sequentially stop the counting operation in response to the hold signal HOLD. Accordingly, the first to third flip-flops FF1 to FF3 maintain the logic state of the stored clock numbers C1 to C3.

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2 shows an example in which the hold signal HOLD is input after the first to fourth clocks of the clock signal CLK are input.

The first to third flip-flops FF1 to FF3 perform a normal counting operation until the fourth clock is input. That is, after the falling edge of the third clock is input, the stored value of the first flip-flop FF1 is 1, the stored value of the second flip-flop FF2 is 1, and the third flip-flop FF3. ) Is 0.

When the fourth clock is input, the first to third flip-flops FF1 to FF3 sequentially count the fourth clock in response to the falling edge of the fourth clock. That is, the stored value of the first flip-flop FF1 is changed from 1 to 0. Accordingly, the stored value of the second flip-flop FF2 is changed from 1 to 0, and the stored value of the third flip-flop FF3 is changed from 0 to 1.

Next, when the hold signal HOLD, which is the ground voltage, is input, the first to third flip-flops FF1 to FF3 maintain the stored values. That is, the stored value of the first flip-flop FF1 is kept at 0, the stored value of the second flip-flop FF2 is kept at 0, and the stored value of the third flip-flop FF3 is kept at 1.

In more detail, as indicated by a dotted line in FIG. 2, the clock signal CLK is not input while the hold signal HOLD is input to the first to third flip-flops FF1 to FF3. Therefore, the first to third flip-flops FF1 to FF3 sequentially stop the counting operation in response to the hold signal HOLD which is sequentially transmitted, and maintain the existing stored value. The first to third flip-flops FF1 to FF3 maintain the stored values until the clock signal CLK is input again.

In the general asynchronous counter, the clock of the clock signal CLK is transferred to the flip-flops FF1 to FF3 during the A-B time period of FIG. 2. Therefore, when the general counter outputs the clock numbers C1 to C3 of the clock signal CLK in the A-B time interval, the counter cannot output an accurate counting value. In addition, as shown by a dotted line in FIG. 2, after the A-B time interval, the next clock of the clock signal CLK is input to the flip-flops FF1 to FF3. Therefore, the flip-flops FF1 to FF3 start counting the next clock. Therefore, the general counter may not output the correct counting value even after the A-B time period.

However, as described above, in the counter 100 according to the present invention, the plurality of latch means FF1 to FF3 hold the hold signal HOLD during counting the clock numbers C1 to C3 of the clock signal CLK. ), The counting stops and the number of clocks C1 to C3 is maintained. The plurality of latch means FF1 to FF3 outputs the held clock number C1 to C3 after the propagation delay time (A-B time interval) has elapsed since the hold signal HOLD is received. The propagation delay time (A-B time period) means a time taken for the clock signal CLK inputted to the latch means FF1 of the first stage to be transferred to the latch means FF3 of the last stage. Therefore, the counter 100 according to the present invention can stably output a value counting the clock number of the clock signal.

3 is a block diagram illustrating a phase locked loop 300 having the counter of FIG. 1.

Referring to FIG. 3, the phase locked loop 300 according to the present invention includes a phase detector 310, a charge pump 320, a control voltage output unit 330, a loop filter 340, a voltage controlled oscillator 350, A divider 360, a counter 100, and a frequency state controller 370 are provided.

The phase detector 310 compares the phase of the divided oscillation frequency fVCOCLK of the divided oscillation clock signal VCOCLK 'with the reference frequency fREF of the reference clock REFCLK. The phase detector 310 outputs the comparison result as an up signal UP or a down signal DOWN. For example, the phase detector 310 may output an up signal UP when the divided oscillation frequency fVCOCLK is lower than the reference frequency fREF, and may output the up signal UP when the divided oscillation frequency fVCOCLK is higher than the reference frequency fREF. The down signal DOWN may be output.

The charge pump 320 converts a predetermined pulse signal into a voltage VCP in response to an up signal UP or a down signal DOWN output from the phase detector 310 and outputs the converted pulse signal.

The control voltage output unit 330 selects one of the output voltage VCP or the locking voltage VLOCK of the charge pump 320 and outputs the voltage as the oscillation control voltage VCTRL.

In more detail, while the frequency state controller 370 and the voltage controlled oscillator 350 perform the band selection operation (band selection mode), the control voltage output unit 330 outputs the locking voltage VLCOK. Here, the locking voltage VLOCK means a voltage corresponding to the target frequency of the oscillation clock signal VCOCLK. That is, the locking voltage VLOCK means a voltage to which the phase locked loop 300 is to be locked. In general, the locking voltage VLOCK is typically 1 / 2VDD. Therefore, in the band selection mode, the control voltage output unit 330 outputs the fixed locking voltage VLOCK as the oscillation control voltage VCTRL.

On the other hand, while the frequency state control unit 370 and the voltage controlled oscillator 350 do not perform the band selection operation (normal mode), the control voltage output unit 330 outputs the output voltage VCP of the charge pump 320. Outputs

The loop filter 340 generally has a structure in the form of a low pass filter (LPF), and accumulates and discharges charges from the charge pump 320 and removes noise frequencies including unwanted output components. do.

The voltage controlled oscillator 350 selects a band in response to the band selection signal BS and outputs an oscillation clock signal VOCLK corresponding to the oscillation control voltage VCTRL.

The counter 100 counts the oscillation clock signal VCOCLK to output the digital value DV_VCOCLK of the oscillation frequency fVCOCLK, and predetermined the digital value DV_VCOCLK of the oscillation frequency fVCOCLK in response to the hold signal HOLD. Print after maintaining for time. Here, the predetermined time refers to the time (propagation delay time of the oscillation clock signal) in which the oscillation clock signal VCOCLK inputted before the hold signal HOLD is input to the counter 100 is transmitted.

That is, when the counter 100 receives the hold signal HOLD while counting the oscillation clock signal VCOCLK, the counter 100 stops counting operation and maintains the clock number DV_VCOCLK of the oscillation clock signal VCOCLK up to that point. . Then, the counter 100 outputs the clock number DV_VCOCLK of the held oscillation clock signal VCOCLK after the propagation delay time elapses from the reception of the hold signal HOLD. The clock number DV_VCOCLK of the oscillation clock signal VCOCLK refers to the digital value of the oscillation frequency fVCOCLK of the oscillation clock signal VCOCLK.

The frequency state controller 370 compares the digital value DV_VCOCLK of the oscillation frequency fVCOCLK with the digital value DV_LOCK of the locking frequency fLOCK and outputs a band selection signal BS. In more detail, the frequency state controller 370 receives the digital value DV_VCOCLK of the oscillation frequency fVCOCLK of the oscillation clock signal VCOCLK from the counter 100. The frequency state controller 370 compares the digital value DV_VCOCLK of the oscillation frequency fVCOCLK with the digital value DV_LOCK of the locking frequency fLOCK. As a result of the comparison, the band having the closest digital value DV_VCOCLK of the oscillation frequency fVCOCLK to the digital value DV_LOCK of the locking frequency fLOCK is selected, and the band selection signal BS corresponding thereto is converted into a voltage controlled oscillator. Output to 350. The selection of the band by the voltage controlled oscillator 350 in response to the band selection signal BS is as described above.

4 is a diagram illustrating a relationship between an oscillation control voltage and an oscillation frequency of the phase locked loop of FIG. 3.
Referring to FIG. 4, a process of determining the oscillation frequency fVCOCLK of the oscillation clock signal VCOCLK by the phase locked loop 300 according to the present invention in a band selection mode in which a band selection operation is performed is described.

As described above, in the band selection mode, the oscillation control voltage VCTRL is fixed to the locking voltage VLOCK and output. When the digital value DV_VCOCLK of the oscillation frequency fVCOCLK of the selected band is larger than the digital value DV_LOCK of the locking frequency fLOCK (for example, f3 of BAND3), the frequency state control unit 370 may determine a lower band (eg, For example, the band selection signal BS corresponding to BAND2 is output. On the contrary, when the digital value DV_VCOCLK of the oscillation frequency fVCOCLK of the selected band is smaller than the digital value DV_LOCK of the locking frequency fLOCK (for example, f0 of BAND0), the frequency state control unit 370 is a higher band. For example, the band selection signal BS corresponding to BAND1 is output. The frequency state controller 370 repeats the above process to select a band having the digital value DV_VCOCLK of the oscillation frequency fVCOCLK closest to the digital value DV_LOCK of the locking frequency fLOCK.

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For example, in FIG. 4, in a state in which the locking voltage VLOCK is fixed (band selection mode), BAND2 having an oscillation frequency fVCOCLK closest to the locking frequency fLOCK is selected. In this case, the oscillation frequency fVCOCLK is f2.

A method of counting a clock signal according to the present invention includes selecting and outputting a clock signal or a hold signal in response to a predetermined selection signal, receiving the clock signal and counting the clock signal, and in response to the hold signal And maintaining the number of clocks counting the clock signal and outputting the number of clocks.

The method of counting a clock signal according to the present invention has the same technical concept as a counter that maintains the counting value described above and outputs it, and corresponds to an operation of the counter that maintains the counting value and outputs the counted value. Therefore, those skilled in the art will understand the method for counting the clock signal according to the present invention from the foregoing description, so a description thereof will be omitted.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the counter outputting after maintaining the counting value according to the present invention has an advantage of stably outputting the counting value regardless of the propagation delay time.

Claims (18)

A selector for selectively outputting a clock signal or a hold signal in response to a predetermined selection signal; And A counting unit configured to count the clock signal, maintain a clock count counting the clock signal in response to the hold signal for a propagation delay time, and then output a counted clock count; And the propagation delay time is a time from the counting unit receiving the clock signal to the completion of counting of the clock signal. The method of claim 1, wherein the counting unit, A plurality of latch means connected to each other in series, each outputting the clock number by one bit, and maintaining the clock number by one bit in response to the hold signal, respectively, and then outputting each of the retained clock numbers. Counter characterized in that. The method of claim 2, wherein the selection unit, And outputs the hold signal after outputting the clock signal. The method of claim 2, wherein the clock signal and the hold signal, The counter is sequentially transmitted through the plurality of latch means. The method of claim 2, wherein the counting unit, And outputting the number of clocks maintained after the propagation delay time at which the clock signal inputted before the hold signal is input is passed to all of the plurality of latch means. The method of claim 2, wherein each latch means, A counter, characterized in that the first to N-th flip-flop. The method of claim 6, Each of the first to Nth flip-flops is a first to N-th D-flop flop, The first to N-th D-flop flops are connected to a D input terminal and a Qb input terminal, respectively, The first D flip-flop receives a hold signal output by the selector through a C input terminal, and outputs the hold signal through a Qb output terminal to a second D flip-flop, The k-th (k is a natural number of 2 or more and N-1 or less) D-flip flop receives the hold signal output by the k-th D-flip flop through a C input terminal, and receives the k + 1D Output the hold signal via a Qb output stage to a flip-flop, And the N-th D-flip flop receives the hold signal from the N-th D-flip flop through a C input terminal. The method of claim 6, Each of the first to N th flip flops is a first to N th flip flop, The first T-flip flop receives a hold signal output by the selector through a T input terminal, and outputs the hold signal through a Qb output terminal to a second T-flip flop. The k-th (k is a natural number equal to or greater than 2 and N-1 or less) T-flip flop receives the hold signal output by the k-th T-flip flop through a T input terminal, and receives the k + 1T Output the hold signal via a Qb output stage to a flip-flop, And the N-th T flip-flop receives the hold signal from the N-1 T-flip flop through a T input terminal. The method according to any one of claims 1 to 8, And said hold signal is a ground voltage. In a phase locked loop (PLL), A voltage controlled oscillator (VCO) for selecting a band in response to the band selection signal and outputting an oscillation clock signal corresponding to the oscillation control voltage; A counter for counting the oscillation clock signal to output an oscillation frequency, and maintaining the oscillation frequency for a predetermined time in response to a hold signal; And And a frequency state controller for comparing the oscillation frequency with a reference frequency and outputting the band selection signal. And the predetermined time is a time from the counter receiving the oscillating clock signal to completing counting on the oscillating clock signal. The method of claim 10, wherein the counter, A selector configured to select and output the oscillation clock signal or the hold signal in response to a predetermined selection signal; And And a counting unit counting the oscillation clock signal to output an oscillation frequency, and outputting the oscillation frequency after maintaining the oscillation frequency for a predetermined time in response to the hold signal. The method of claim 11, wherein the counting unit, And a plurality of latch means connected to each other in series and outputting the number of clocks one bit at a time, and respectively outputting the number of clocks one bit at a time for a predetermined time in response to the hold signal. Phase locked loop. The method of claim 12, wherein the selection unit, Outputting the hold signal after a predetermined time elapses from outputting the clock signal. The method of claim 13, wherein the clock signal and the hold signal, And the phase locked loop is sequentially transmitted through the plurality of latch means. The method of claim 12, wherein the counting unit, And outputting the number of clocks maintained after the propagation delay time at which the clock signal inputted before the hold signal is input is passed to all of the plurality of latch means. The method according to any one of claims 10 to 15, And said hold signal is a ground voltage. Selecting and outputting a clock signal or a hold signal in response to a predetermined selection signal; Receiving the clock signal and counting the clock signal; In response to the hold signal, maintaining a number of clocks counting the clock signal for a predetermined time; And Outputting the held clock number; And the predetermined time is a time from receiving the clock signal to completing counting of the clock signal in the counting of the clock signal. The method of claim 17, wherein selecting and outputting the clock signal or the hold signal comprises: And outputting the hold signal after outputting the clock signal.

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