JPH06164372A - Asynchronous up / down counter - Google Patents

Abstract

(57) [Abstract] [Purpose] Even if the clock pulse width changes, a hazard due to the mutual relationship of the operation delay time of each logic element is not generated,
Further, an asynchronous up / down counter is obtained in which malfunction of the counter due to the timing of the counter clock and the timing of the up / down switching signal is prevented. [Structure] A clock signal and an up / down switching signal are input to an up / down detection means, a switching detection signal having a function of locking the counter means by detecting switching of the counting direction, and a fixed up / down switching for switching the counting direction. A signal is output and the direction is switched while the counter means is locked by the confirmed up / down switching signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to prevention of erroneous counting due to a hazard of an asynchronous reversible counter (hereinafter referred to as an asynchronous up / down counter) used in digital signal processing, modulation / demodulation processing, and the like.

[0002]

2. Description of the Related Art FIG. 8 is described in "Basics of IC logic circuit design", published on August 30, 1983, first edition, third edition, by Satoshi Nishino, Nikkan Kogyo Shimbun, page 72, FIG. It is a block diagram which shows the principle of the conventional asynchronous up / down counter. In the figure, 1 is a clock signal, 101α,
Reference numerals 111α, 121α, 131α are flip-flops forming a counter, and SW1, SW2, SW3 are switches for switching up / down of the counter. When all the switches SW1, SW2, SW3 are connected to the upper side, the flip-flops 101α, 111α, 12
Since 1α and 131α alternately output the input clock signal to Q and bar Q, respectively, the flip-flops 101α, 111α, 121α and 131α operate so as to divide the frequency by ½ each time the clock signal is input. To do.
Therefore, the circuit as a whole operates as an asynchronous up counter, and conversely, when all are connected to the lower side, the bar Q output of each flip-flop 101α, 111α, 121α, 131α is the polarity inversion of Q, that is, the complement of 2 is output. However, since the circuit for outputting the complement is the subtraction circuit and the subtraction circuit is connected in series as the whole circuit, it operates as an asynchronous down counter.

FIG. 9 shows the switches SW1, SW2, S of FIG.
It is a logic diagram which constituted W3 with a logic circuit. In the figure,
2α is a control input that controls the selection of whether to connect the output T to the input Q or the input bar Q. 100α is an inverter for inverting the polarity of the control input 2α and outputting the bar 2α, 102α is for inverting the polarity of the input bar Q and the OR of the control input 2α, and outputting it. The OR circuit 103α is for inverting the polarity of the input Q and the OR of the bar 2α and outputting it. OR circuit, 104α
Is an AND circuit for outputting the AND of 102α and 103α, and SW is a switch. In this circuit, control input 2α
When 1 is input to 1, OR circuits 102α and 103α are input with 1 and 0, respectively, and input Q and input bar Q are input with 1 and 0, respectively.
When 0 is entered, the outputs of the OR circuits 102α and 103α are 0,
It becomes 0. Therefore, the AND circuit output becomes 1 and SW
Is in the form of being thrown into the Q side as shown in FIG. Next, when reverse 0 is input to the control input 2α, the OR circuit 102α,
Input 0 and input bar Q with 0 and 1 respectively entered in 103α
When 1 and 0 are input to the OR circuits 102a and 103, respectively.
The outputs 102αa and 103αa of α are 1,0. Therefore, the AND circuit output 104αa becomes 0, and from the result, when attention is paid to the input Q, the input bar Q and the output of the AND circuit 104α, SW is in the form of being thrown to the bar Q side contrary to FIG.

FIG. 10 shows the 72nd page of FIG.
9 is a logic diagram of a conventional asynchronous up / down counter configured by replacing SW1 to SW4 of FIG. 8 described in No. 2 with a logic circuit. In this figure, S is a set signal and R is
Is a reset signal, 1 is a clock signal, 2 is an up / down switching signal, 100 is an inverter for inverting the polarity of the up / down switching signal, 102, 112 and 122 are inputs Q of an asynchronous up / down counter and the bar 2 OR circuit for inverting the polarity of the OR signal of the output, and the gate connected to the Q output 3a of the JK flip-flop, 101, 1
Reference numerals 11, 121 and 131 constitute a counter, and JK which outputs each digit count value output signal 3a, 3b, 3c, 3d and its inverted signal bar 3a, bar 3b, bar 3c, bar 3d.
Type flip-flop. Up in the circuit of Figure 10
Since the inverter for down switching can be shared, only one inverter, labeled 100, is used. The flip-flops 101α, 111α, 121α, 131α which are all the same in FIG.
Of the flip-flops 101, 111, 121, 131. Similarly, SWs that are all the same in FIG.
1-3 are 100α, 102α, 103α, 104 in FIG.
corresponding to α, and 102, 103, 104, and
It corresponds to each logic element which comprises each switch of 112,113,114,122,123,124. Then, each logic element 102, 103, 104, 112, 113, 11
Outputs corresponding to 4,122,123,124 are 102
a, 103a, 3a ', 112b, 113b, 3b',
122c, 123c, 3c '.

However, the circuit of FIG. 10 has the following problems, and its operation will be described with reference to a time chart. FIG. 11 is a timing chart for explaining the operation of the asynchronous up / down counter. Figure 11
The reference numeral corresponds to FIG. If the time is strictly divided in a transient state such as reset, 10
Which of the JK flip-flops 1, 111, 121, 131 operates is uncertain (not particularly determined).

This problem will be described with reference to the timing chart of FIG. First, the asynchronous up / down counter is set (S becomes 1 and the circuit can count by the input of the set signal (a)), and the reset signal R
It is assumed that the circuit is reset (normally 0 in the initial state) by the input of (a).

In this state, the JK flip-flop 101 at the first stage, which receives the clock signal 1 (c), starts operating and Q
The terminal outputs the signal of 3a (e) as the least significant digit.
At the same time, the inverted signal of bar 3a is output from the bar Q terminal.
(K) is output. Next, the AND of 3a (e) and the up / down switching signal 2 (d) changes from AND gate 103 to 1
03a (SE), the AND of the inverted signal bar 2 of the bar 3a and the up / down switching signal 2 is from the AND gate 102 to 10.
The OR signals of 2a (s) and 103a and 102a are output from the OR gate 104 as 3a '(so).

The second-stage JK flip-flop 111 starts operation and outputs the signal of 3b as the next digit from the Q terminal. At the same time, the inverted signal bar 3b
Is output. Next, 3b and up / down switching signal 2
(D) And is AND gate 112 to 112b
(Ta), bar 3a (h) and up / down switching signal 2
The AND of the inversion signal of (D) is 1 from the AND gate 113.
The OR signals of 13b (H) and 112b (T) and 113b (H) are output from the OR gate 114 as 3b '(T).

The third-stage JK flip-flop 121 starts its operation and outputs a signal of 3c (ki) as the next digit from the Q terminal. At the same time, the inverted signal is output from the bar Q terminal. Next, 3c and the AND of the up / down switching signal 2 (D) are AND gates 122 to 122c (TE), the bar 3
c and the inverted signal bar 2 of the up / down switching signal 2 (d) are AND gates 123 to 123c.
(G), the OR signals of 122c and 123c are output from the OR gate 124 as 3c '(na).

The fourth stage JK flip-flop 121 starts its operation and outputs a signal of 3d (h) as the next and next digit from the Q terminal.

Here, for example, a clock signal (c) is input and counting up from 0 (hexadecimal number) is performed, 5
It is assumed that the up / down switching signal 2 is set to 0 in the (hexadecimal) state to switch to the down counting operation. Then, although the count value should not change unless the counter pulse is input, the counter output (3
a, 3b, 3c, 3d output) has a problem that it is changed from 5 (hexadecimal number) to 6 (hexadecimal number) as described in detail below. (Or, there may be other states due to variations in the delay time of the gate.) Therefore, in the asynchronous up / down counter of FIG. 10, the down count operation starts not from 5 (hexadecimal number) but from 6 (16). It has a serious drawback that the count is wrong because it is a decimal number. Hereinafter, a phenomenon in which counting is performed due to the above-mentioned malfunction even though these counter pulses are not input is referred to as disorder of the count value.

In FIG. 10, first, considering the case of 5 (hexadecimal number), 20 is equal to 1 for 3a (e), similarly 21: 3b (f) is 0, and 22: 3c (ki) is 1, 23:
3d (h) is 0. In this state, when the up / down switching signal 2 (d) changes from 1 to 0 (up counting to down counting), the Q output of 20 is 1 and the up / down switching signal 2 (d) is 1. Becomes 0, the output 102a (s) of the gate 102 in FIG. 10 changes, and as a result, the output 3a '(so) of the gate 104 becomes 1.
From 0 to 0, the circuit having the SW function is affected by the switching control signal of the SW itself, and the falling signal is input. Therefore, the expected action is not 4 (hexadecimal number), 20 is 0, 21 is 1, 22 is 1, 23 is 1, that is, E
(Hexadecimal number), which means a malfunction. Therefore, the reset signal forcibly sets the count value to 0 and cancels the erroneous count.
If you do not want to miscount even if the count value is a little,
A strobe pulse circuit was added to prevent erroneous counting, and its output was input to the set terminal of the counter to deal with it.

FIG. 12 is a circuit diagram of the strobe pulse circuit. This strobe pulse circuit is composed of a circuit (hereinafter referred to as a CR circuit) having a time constant with a capacitor C and a resistor R. When a pulse signal is input to the input terminal (d), it is branched into two, one of which is the inverter 14
After being input to 1, the polarity is inverted (141a), it is input to the inverter 142 through the CR circuit. Here, the time for charging the capacitor C through the resistor R to the sensing level SR of the inverter 142 is the delay time due to CR. The output (142a) of the inverter 142 is logically ORed with the other branched signal of the pulse input by the AND circuit 143 to be a strobe signal output (ne).

FIG. 13 is a timing chart for explaining the operation of the strobe pulse circuit shown in FIG. Reference numerals in FIG. 13 correspond to those in FIG. FIG.
In, the pulse signal input (d) has its polarity inverted by the inverter 141, and the output (141a) enters the CR circuit. At that time, C is charged through R, and the terminal voltage of C becomes (n) in FIG. This terminal voltage (nu) of C enters the inverter 142, but its output becomes a voltage rising at the threshold level S of the inverter 142, and CR
The strobe signal output (ne) causes a delay time due to.

[0015]

When an asynchronous up / down counter is used, there is a problem that the "count value is disturbed" when the up / down counting operation is switched in the counting direction. If a strobe pulse circuit is added to avoid this problem, it is composed of a circuit that has a time constant that matches the timing with a clock signal with a certain pulse width or more. When the width becomes narrower than the delay time of CR, the terminal voltage of C does not reach the threshold level S of the inverter 142. Therefore, the strobe pulse is not output, and there is a problem that a malfunction such as “disturbance of count value” occurs eventually.

The present invention has been made in order to solve the above problems, and does not generate an unintended pulse (hazard) due to the influence of the operation delay time of each logic element even if the clock pulse width changes. Another object is to prevent malfunction of the counter due to the timing of the counter clock and the timing of the up / down switching signal.

[0017]

According to a first aspect of the present invention, an asynchronous up / down counter receives a clock signal and an up / down switching signal, detects the switching of the count direction, and detects a switching detection signal. And an up / down detecting means for outputting a fixed up / down switching signal by this switching detection signal, and a count value output signal by inputting the clock signal and the fixed up / down switching signal. A counting means for stopping the counting operation by a signal is provided.

The asynchronous up / down counter according to the second aspect of the present invention inputs the clock signal and the up / down switching signal, detects the switching of the count direction, outputs the switching detection signal, and switches the switching direction. Up / down detecting means for outputting a confirmed up / down switching signal according to a detection signal, and confirmed up / down by inputting the switching detection signal
An edge detecting means for outputting a down switching signal and a counting means for outputting a count value output signal by inputting the clock signal and the fixed up / down switching signal and stopping the counting operation by the switching detection signal are provided. It is a thing.

In the asynchronous up / down counter according to the invention of claim 3, clock signal detecting means for outputting a clock signal when detecting the up-count clock signal or the down-count clock signal, the up-count clock signal and the down-counter A count switching signal generating means for discriminating the counting direction from the count clock signal and outputting an up / down switching signal, and the clock signal and the up / down switching signal are inputted to detect the switching of the counting direction. To output a switching detection signal, and to output a fixed up / down switching signal by the switching detection signal, and to output a count value output signal by inputting the clock signal and the fixed up / down switching signal. Stop the counting operation by the switching detection signal It is obtained so as to include a count unit.

[0020]

According to the first aspect of the present invention, the up / down detecting means for counter lock detects the up / down counting direction switching operation and outputs a switching detection signal to the counter to generate a disturbance in the count value. Only when the counter is locked, the count direction is switched, and the count value is prevented from being disturbed when the direction switching is completed and the count value is not disturbed, the count value is prevented from being disturbed.

The edge detecting means according to the second aspect of the present invention detects the edge of the up / down switching signal, outputs a fixed up / down switching signal, and switches up / down from the time when the up / down switching signal changes. Confirm the direction.

The clock signal detecting means in the invention of claim 3 outputs the clock signal from the up-count clock signal and the down-count clock signal, and the count switching signal generating means outputs the up-count clock signal and the down-count clock signal. The count direction is discriminated from and the up / down switching signal is output.

[0023]

EXAMPLES Example 1. FIG. 1 is a block diagram showing the principle of an asynchronous up / down counter according to the first aspect of the invention. An embodiment of the present invention will be described below with reference to the drawings. First, the operation steps of this asynchronous up / down counter are shown below. Step 1: Up / down detection Step 2: Counter lock Step 3: Up / down operation switching Step 4: Counter lock release Step 5: Count operation Clock signals to be counted in the figure are input to the counting means and the up / down detection means. The switching detection signal for locking the counting means and the confirmation of switching the up / down operation direction during the locking of the counting means are counted up / down and the switching signal together with the clock signal without being affected by the hazard.

FIG. 2 is a logic diagram of an asynchronous up / down counter according to an embodiment of the present invention.
In FIG. 2, 1 is a clock signal for performing a counting operation, 2 is an up / down switching signal for controlling an up-counting or down-counting operation, 3a to 3d are count value output signals (3a is the lowest digit to 3d). Represents the most significant digit), and bars 3a to 3c indicate count value output signals 3a to 3c.
3c polarity inversion signal, 4 as 1 as count inversion means
Bit counters 510, 520, 530 are T-type flip-flop circuits as flip-flops, 610, 6
20 and 630 use an exclusive OR circuit as a polarity inverting means for switching the effective edge of the clock signal to the T-type flip-flops 510, 520 and 530 according to the state of the up / down switching signal 2. 6a ~
6c is the output. 7 is a D flip-flop 80
1. Up / down detection means for detecting up / down count switching composed of exclusive OR circuit 601, 9 is a definite up / down switching signal whose counting operation is definite, and bar 9 is a definite up / down switching signal. An inverted output of 10 is a switching detection signal for detecting a change in the up / down switching signal and locking the counting means, 14
Is a timing control circuit composed of an AND circuit, and 14a is its output.

Next, the operation will be described with reference to the timing chart showing the operation sequence of the asynchronous up / down counter when the up / down count is switched as shown in FIG. In FIG. 3, corresponding parts in FIG. 2 are designated by the same reference numerals. In FIG. 2, the clock signal 1 (FIG. 3 (no)) passes through the timing control circuit 14,
When applied to the clock input terminal Ta of the 1-bit counter 4, the toggle operation is performed and the count output 3a (see FIG.
(M)) is output. The polarity inversion signal bar Qa of the count output 3a is the exclusive OR circuit 610 output 6a (see FIG.
(M)), the T-type flip-flop 5b of the next stage, which receives the valid edge of the clock input terminal Tb of the T-type flip-flop of the next stage, performs a toggle operation,
The count output 3b (Fig. 3 (mo)) is output. A polarity inversion signal bar Qb of the count output 3b (FIG. 3 (m))
Is input to the clock input terminal Tc of the T-type flip-flop of the next stage through the exclusive OR circuit 620 output 6b (FIG. 3 (m)), and the T-type flip-flop 5c of the next stage which has received its valid edge Performs a toggle operation, and the count output Rc (FIG. 3 (Y)) is output. The polarity inversion signal bar Qc of the count output 3c (FIG. 3A) passes through the exclusive OR circuit 630 output 6c (FIG. 3M) to the clock input terminal Td of the T-type flip-flop of the next stage. The T-type flip-flop 5d at the next stage, which has been input and received the valid edge, performs the toggle operation, and the count output 3d (FIG. 3 (Y)) is output. Here, the exclusive OR circuit 61
0, 620, and 630 are used to select whether or not to perform polarity inversion. One side input is 1 when the polarity is inverted, and one side input is 0 when the polarity is not inverted. The confirmed up / down switching signal 9 is input to this one-sided input. The operation of this counter is 3a = 6a, 3b = 6b, 3
When c = 6c, that is, when the confirmed up / down switching signal 9 is 1, the down count operation is performed. When bar Qa = 6a, bar Qb = 6b, bar Qc = 6c, that is, when the confirmed up / down switching signal 9 is 0, the up-count operation is performed. In this way, the up / down count operation switching is determined by the state of the definite up / down switching signal 9 (FIG. 3F). The toggle operation speed of each flip-flop can be half that of the previous flip-flop. At this time, the power consumption of the flip-flops is almost proportional to the operation speed, so that the power consumption decreases as the flip-flops in the subsequent stages are reduced.

In FIG. 3, the up / down switching signal 2
(When FIG. 3C is changed, the up / down detection means 7 operates as follows. In FIG. 2, the value held by the D flip-flop 8 and the next clock edge are taken. When the value is different, the switching detection signal 10 becomes "0", the T-type flip-flops 510, 520 and 530 are locked, and the T-type flip-flops 510 and 52 are locked.
It does not operate even if a valid edge is applied to the clock input of 0,530. Therefore, it is possible to prevent the count value from being disturbed because a hazard (extra pulse having a very narrow width) is generated at the time of up / down count switching and the hazard is counted. After that, the clock signal 1 is applied to the D-type flip-flop 8, the definite up / down switching signal 9 is output, the switching of the valid edge is performed by the exclusive OR circuit 6, and then the switching detection signal 10 is set to "1". , The T-type flip-flop 5 is unlocked. After that, counting is performed in the direction in which the up / down count is switched by the input of the clock signal 1.

The switching of the valid edge by the polarity inverting means may be realized by a data selector (multiplexer) not shown in place of the exclusive OR circuits 610, 620, 630, and the exclusive OR circuits 610, 62.
It operates similarly to the case of 0,630. After confirming that the T-type flip-flops 510, 520, 530 are unlocked, a valid edge is applied to the 1-bit counter 4. The timing control circuit 14 adjusts the application timing of the effective edge. In the timing control circuit 14, the switching detection signal 10 becomes "1" and the T-type flip-flop 51
After confirming that the locks of 0, 520, and 530 have been released, timing control for accepting the valid edge of the count clock is performed. This makes it possible to perform a reliable up / down switching operation.

Example 2. FIG. 4 is a logic diagram of an asynchronous up / down counter according to a second embodiment of the present invention. In the example of FIG. 4, the up / down detecting means of FIG. 2 is devised. Output timing time Tr between the fixed up / down switching signal 9 and the switching detection signal 10
This is an example in which a D-type flip-flop 802 that triggers on a falling edge is added as an edge detection means in order to widen the margin of the above, compared with the case of the embodiment of the invention of claim 1.
Since the definite up / down switching signal 9a is definite from the time when the up / down switching signal 2 changes, the time before the application of the next clock signal to be counted can be widened to allow a margin, and the timing between the signals can be increased. Easy to adjust. After that, the configuration is almost the same as that of the example of FIG. 2 and the operation is also the same as that of the example of FIG. 2. Therefore, the same parts as those of FIG. In the embodiment of the invention of claim 2, there is a margin in the output timing, and malfunctions due to changes in operating temperature are less likely to occur. In addition, there is a margin in the output timing design of the logic circuit when the circuit is required to operate at high speed.

FIG. 5 shows the clock signal 1 (g) to bar 3d.
The description up to (b) is omitted because it corresponds to the same reference numerals in FIG. 3 except 9a (di). 5a in FIG. 5 is 9 in FIG.
Compared to (F), the timing is earlier at both the rising and falling edges. It can be seen that the signal rise of 9a (di) in FIG. 5 occurs at the rise of the switching signal 2 (go), and the time Tr before the application of the clock signal for the next counting is widened and has a margin.

Example 3. FIG. 6 is a logic diagram of an asynchronous up / down counter according to an embodiment of the present invention. In the figure, 11 is a clock dedicated to down counting,
12 is a clock dedicated to up-counting, 13 is a clock 11 dedicated to down-counting, clock 1 is dedicated to up-counting
An RS (Reset Set) flip-flop, which is a count switching signal generating means for outputting the up / down switching signal 2a from 2, a clock signal detecting means 16 for detecting the clock signal 1a from the down counting dedicated clock 11 and the up counting dedicated clock 12. The OR circuit 17 is an AND circuit which functions as the timing control shown in FIG.

In the embodiment of the invention of claim 1, the counting operation is determined by the state of the up / down switching signal, but in the embodiment of the invention of claim 3, in FIG. The count-dedicated clock 11 is input, and the count direction is determined by applying each clock. The polarity of the two clocks in FIG. 6 is a case of a negative, determines whether the advance either direction of the count by the RS flip-flop 13 is counted switching signal generating means. Up by this judgment /
The down switching signal 2a is generated. Furthermore, OR circuit 1
When the down count dedicated clock 11 and the up count dedicated clock 12 are input to 6 to output the clock signal 1a, the up / down switching signal 2a and the clock signal 1 and the up / down switching signal 2 in the circuit of FIG. The signals of are gathered. Therefore, since the configuration of FIG. 6 and thereafter is almost the same as that of the example of FIG. 2, the same parts as those of FIG.
The counter operation becomes possible without inputting the down switching signal 2a.

FIG. 7 is a timing chart showing the operation sequence of the asynchronous up / down counter when the up / down count is switched in the circuit of FIG. Clock for exclusive use of up count 1 in FIGS.
2, When changing the clock 11 for down count,
D-type flip-flop 801, exclusive OR circuit 601
The up / down detecting means 7 consisting of operates as follows. In FIG. 7, when the value held by the D-type flip-flop 8 and the value taken at the next clock edge are different, the switching detection signal 10 becomes "0" and the T-type flip-flops 510, 520, 530 are Locked, that T
Even if a valid edge is applied to the clock input of each type flip-flop 510, 520, 530, it does not operate. Even if this effective edge is applied, it will not operate,
It is possible to prevent a hazard from occurring when the up / down count is switched, and the count value is disturbed by counting the hazard. Then D-type flip-flop 801
After the clock 1 is applied to the output, the definite up / down switching signal 9 is output, and the switching of the valid edge is performed by the exclusive OR circuit 602, the switching detection signal 10 is "1".
The T-type flip-flops 510, 520, 530 are unlocked. Then, when the lock is released, it becomes a countable state.

[0033]

According to the first aspect of the present invention, the up / down detecting means for up / down switching causes the clock signal and the change of the switching signal to have a constant timing, so that the counter operation is stopped and counting is performed during the hazard occurrence period. By preventing the value from being disturbed, it is possible to obtain a highly reliable up / down counter.

According to the second aspect of the present invention, since the edge detection circuit is provided, the definite up / down switching signal is definite from the time when the up / down switching signal changes, so that the time until the next count clock is applied is set. It becomes possible to have a margin, and there is an effect that the timing adjustment between each signal can be easily performed.

According to the invention of claim 3, in addition to preventing the disturbance of the count, there is an effect that the up / down count can be switched by the up count clock signal and the down count clock signal without inputting the up / down switching signal from the outside.

[Brief description of drawings]

FIG. 1 is a principle block diagram of an asynchronous up / down counter of the invention of claim 1.

FIG. 2 is a logic diagram of an asynchronous up / down counter according to an embodiment of the present invention.

FIG. 3 is a timing chart of an asynchronous up / down counter according to an embodiment of the present invention.

FIG. 4 is a logic diagram of an asynchronous up / down counter according to an embodiment of the present invention.

FIG. 5 is a timing chart of an asynchronous up / down counter according to an embodiment of the present invention.

FIG. 6 is a logic diagram of an asynchronous up / down counter according to an embodiment of the invention as claimed in claim 3;

FIG. 7 is a timing chart of an asynchronous up / down counter according to an embodiment of the present invention.

FIG. 8 is a block diagram showing the principle of a conventional asynchronous up / down counter.

FIG. 9 is a logic diagram showing an up / down switching circuit used in a conventional asynchronous up / down counter.

FIG. 10 is a logic diagram of a conventional asynchronous up / down counter.

FIG. 11 is a timing chart for explaining the operation of a conventional asynchronous up / down counter.

FIG. 12 is a circuit diagram of a strobe pulse generation circuit used in a conventional asynchronous up / down counter.

FIG. 13 is a timing chart for explaining the operation of the strobe pulse generation circuit.

[Explanation of symbols]

 1 Clock signal 2 Up / down switching signal 3 Count value output signal 4 1-bit counter 510, 520, 530 T-type flip-flop 601, 610, 620, 630 Exclusive OR circuit 7 Up / down detecting means 801, 802 D type Flip-flop 9, 9a Definite up / down switching signal 10, 10a, 10b Switching detection signal 11 Down-count clock 12 Up-count clock 13 RS flip-flop 14 Timing control circuit (AND circuit) 16 OR circuit 17 AND circuit

Front page continuation (72) Inventor Izaki Lighting 8-1-1 Tsukaguchi Honcho, Amagasaki City Mitsubishi Electric Corporation Communication Equipment Works (72) Inventor Yusuke Mashiba 2-5-1 Inadera, Amagasaki Mitsubishi Electric Microcomputer Equipment Within the corporation

Claims (3)

[Claims] 1. Up / down detection means for inputting a clock signal and an up / down switching signal, detecting that there has been a switching in the counting direction, and outputting a switching detection signal and a fixed up / down switching signal, An asynchronous up / down counter comprising a counting means for outputting a count value output signal by inputting a clock signal and the fixed up / down switching signal and stopping the counting operation by the switching detection signal. 2. Up / down detection means for inputting a clock signal and an up / down switching signal, detecting that there has been switching in the counting direction and outputting a switching detection signal, said up / down switching signal and said An edge detecting means for outputting a fixed up / down switching signal by inputting a switching detection signal, and a count value output signal by inputting the clock signal and the fixed up / down switching signal to perform a counting operation by the switching detection signal. An asynchronous up / down counter having a counting means for stopping. 3. A clock signal detecting means for outputting a clock signal when an up-count clock signal or a down-count clock signal is detected, and a count direction is discriminated from the up-count clock signal and the down-count clock signal, and the up-count clock signal is detected. A count switching signal generating means for outputting a down / down switching signal, the clock signal and the up / down switching signal are input, a switching detection signal is output by detecting the switching of the counting direction, and this switching detection is performed. Up / down detection means for outputting a fixed up / down switching signal by a signal, and output of a count value output signal by inputting the clock signal and the fixed up / down switching signal, and stopping the counting operation by the switching detection signal Asynchronous assembly characterized by having counting means Up / down counter.