KR100711092B1 - Stacked Chip Devices - Google Patents

Abstract

The present invention relates to a stacked chip device which improves attenuation in the stopband and improves the frequency deviation between the unit devices in a stacked array chip in which a plurality of unit devices are made of one chip. An electronic device pattern formed; A first inner electrode pattern formed to be connected to a first outer terminal of the first side of the body; A second inner electrode pattern formed to be connected to a second outer terminal of the second side of the body; A third inner electrode pattern formed to be connected to a third outer terminal of the third side of the body; And auxiliary electrode patterns that are not directly connected to the first to third external terminals, one side of the electronic element pattern is connected to the first external terminal, and the other side of the electronic element pattern is connected to the second external terminal. A part of the auxiliary electrode pattern is connected to the first and second internal electrode patterns, respectively.

Description

Laminated chip device

1 is an external perspective view of a conventional stacked chip device;

2 is a perspective view illustrating a lamination structure of an internal electrode pattern of the stacked chip device of FIG. 1;

3 is a schematic cross-sectional view of the stacked chip device of FIG. 1;

4 is an equivalent circuit diagram of FIG. 3;

5 is a characteristic graph of a conventional stacked chip device;

6 is an external perspective view of a stacked chip device according to a first exemplary embodiment of the present invention;

7 is a perspective view showing a laminated structure of a pattern employed in the first embodiment of the present invention;

8 is a schematic cross-sectional view of the stacked chip device of FIG. 6;

9 is an equivalent circuit diagram of FIG. 8;

10 is a characteristic graph of a stacked chip device according to a first embodiment of the present invention;

11 is a view for explaining a manufacturing process of the stacked chip device according to the first embodiment of the present invention;

12 is a schematic cross-sectional view of a stacked chip device according to a second embodiment of the present invention;

13 is a schematic cross-sectional view of a stacked chip device according to a third embodiment of the present invention;

14 is a perspective view showing a laminated structure of a pattern employed in the third embodiment of the present invention;

15 is a perspective view showing a laminated structure of a pattern employed in the fourth embodiment of the present invention;

16 is a schematic cross-sectional view of a stacked chip device according to a fourth exemplary embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

10, 120: first sheet 12, 122: first internal electrode pattern

14, 124: second internal electrode pattern 20, 130: second sheet

22, 126: third internal electrode pattern 30, 140: cover sheet

50: third sheet 52, 132: auxiliary electrode pattern

60: element 62: first external terminal

64: second external terminal 66: third external terminal

68: resistor pattern 60a, 60b, 60c, 60d: unit element

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to stacked chip devices, and more particularly, to stacked chip devices designed to improve insertion loss characteristics.

In general, the resistor R serves to control the current flow or lower the voltage in the circuit. In particular, the resistor plays a role of impedance matching or the like in the AC circuit. The resistor is combined with other passive elements such as capacitor (C) or inductor (L) to implement various filters and performs the function of frequency selection as well as the removal of high frequency noise.

In addition, the capacitor (C) basically serves to cut off the DC and to pass the AC signal, and also constitutes a time constant circuit, a time delay circuit, an RC, and an LC filter circuit. The capacitor itself also serves to remove noise.

In addition, varistors are widely used as protection devices for protecting important electronic components and circuits from overvoltage (surge voltage) and static electricity because the resistance changes according to the applied voltage. In other words, no current flows through the varistors arranged in the circuit. However, if an overvoltage is applied at both ends of the varistor due to an overvoltage or the like exceeding a certain voltage, the resistance of the varistor decreases rapidly and almost all current flows to the varistor, and no current flows to other elements, so that the circuit in which the varistor is disposed is protected from overvoltage. .

The varistor acts as a capacitor in a steady state without overvoltage. Capacitors not only have capacitance values but also parasitic inductance values, and inductors are devices having the property of preventing a change in current when a current flows through the wire. The inductor has a parasitic capacitance value in addition to the inductance value. This changes the function of the device at a specific high frequency, which is called the self-resonant frequency.

The resistive-varistor composite chip formed by combining a resistive component and a varistor component together in a single chip removes noise that may occur in a high frequency line simultaneously with protection from overvoltage and static electricity. By combining the varistor element and the resistance element as described above, it is possible not only to effectively protect important electronic components, small motors and circuits from overvoltage, but also to ensure stable operation of electronic components or circuits by securing a stable power supply voltage and removing noise components. I can guarantee it.

Therefore, the combination of the inductor-varistor realizes a pi (π) type filter made of an inductor-capacitor having good high frequency noise rejection.

Such a resistance-varistor coupling element or an inductor-varistor coupling element immediately exhibits the function of the varistor when an abnormal overvoltage in the circuit is introduced, thereby protecting the electronic component or circuit from the overvoltage and removing noise components.

In particular, in recent years, in response to the miniaturization of electronic devices, demands for highly integrated circuit chip elements have increased.

In accordance with this trend, various types of stacked chip devices have been proposed, and one example is a stacked chip device having a configuration as illustrated in FIG. 1.

1 illustrates a stacked chip device in which four unit devices 40a, 40b, 40c, and 40d are arranged in one chip. The stacked chip device of FIG. 1 is set and implemented as a pie type RC filter.

In the conventional stacked chip device, first to third external terminals 42, 44, and 46 are formed on the side surface of the body 40, and a resistor pattern 48 is formed on the top surface of the body 40. That is, the first outer terminal 42 is formed to be spaced apart from each other on one side portion of the body 40 is connected to the inner electrode pattern (not shown) exposed to the side portion and one end extends to the upper surface of the body 40 . The second outer terminal 44 is formed to be spaced apart from each other on the side portion opposite to the side portion on which the first outer terminal 42 is formed, and is connected to an internal electrode pattern (not shown) exposed to the side portion, and one end is the body 40. Extends to the top of the surface. The third outer terminal 46 is formed on each of the two opposite side portions of the body 40 and is connected to an inner electrode pattern (not shown) exposed to the corresponding side portion, and one end thereof extends upward. The third external terminal 46 is a common terminal (ground electrode). The resistor pattern 48 is formed to interconnect the first and second external terminals 42 and 44 which face each other on the upper surface of the body 40.

2 is a perspective view illustrating a stacked structure of an internal electrode pattern of the stacked chip device of FIG. 1, and FIG. 3 is a schematic cross-sectional view of the stacked chip device of FIG. 1. The stacked chip device of FIG. 1 has a structure in which a plurality of sheets on which internal electrode patterns are formed as illustrated in FIG. 2 are stacked.

In FIG. 2, the first sheet 10 has a first inner electrode pattern 12 extending from one end in the lateral direction to the other end and a second inner electrode pattern 14 extending from the other end in the lateral direction to the one end. One unit element is formed for each of the unit elements 40a, 40b, 40c, and 40d. The first internal electrode pattern 12 and the second internal electrode pattern 14 are spaced apart from each other, and the spaced distances are the same for each unit element. That is, the first sheet 10 includes a plurality of first internal electrode patterns 12 connected to the external terminals 42 and 44 on the side surfaces of the unit elements 40a, 40b, 40c, and 40d, respectively, and spaced apart from each other. And a second internal electrode pattern 14 are formed. In FIG. 2, the first and second internal electrode patterns 12 and 14 have extension parts 12a and 14a. One side of the internal electrode pattern is directly provided without the extension parts 12a and 14a. It may be exposed to the one end part in the horizontal direction, or the other end part of the said unit element. In FIG. 2, a third internal electrode pattern 22 is formed on the second sheet 20 to cross the opposite ends in a direction crossing the first and second internal electrode patterns 12 and 14. In FIG. 2, although the extension part 22a is formed in the both ends of the longitudinal direction of the said 3rd internal electrode pattern 22, you may have a shape without the extension part 22a. Here, the internal electrode patterns 12, 14, and 22 are also called internal conductor patterns.

When the first sheet 10 and the second sheet 20 having the internal electrode patterns are manufactured as described above, the first sheet 10 is laminated on the second sheet 20 as the lowermost layer, and then the cover is laminated. The sheet 30 is further laminated. After that, pressing and then sequentially performing the cutting, baking out, and firing step to form the desired body. The body formed after the firing process is a body in which the first to third external terminals 42, 44, 46 and the resistor pattern 48 are not formed. After the firing process, the first to third external terminals 42, 44, and 46 and the resistor pattern 48 are formed.

In FIG. 2, the number of sheets on which the internal electrode patterns are formed is set to two, and the number of sheets may be increased as necessary. That is, the capacitance value may be adjusted by forming a single chip by stacking three or more manufactured first and second sheets 10 and 20 in various combinations.

FIG. 3 is a view in which any one of a plurality of unit elements 40a, 40b, 40c, and 40d is vertically cut, C1 corresponds to the first internal electrode pattern 12, and C2 corresponds to the second internal portion. Corresponds to the electrode pattern 14, and G corresponds to the third internal electrode pattern 22.

4 is an equivalent circuit diagram of FIG. 3, in which a resistor R is connected between an input terminal IN and an output terminal OUT, and capacitors C1 and C2 are connected between both ends of the resistor R and ground. The input terminal IN and the output terminal OUT of FIG. 4 correspond to the first and second external terminals 42 and 44 of FIG. 3, and the capacitor C1 of FIG. 4 corresponds to C1 of FIG. 3, and FIG. 4. Capacitor C2 corresponds to C2 of FIG. 3. In addition, the resistor R of FIG. 4 corresponds to the resistor pattern 48 of FIG. 1. In Fig. 4, the capacitors C1 and C2 may be viewed as varistors. FIG. 4 is a typical PI-type RC filter structure, in which a varistor has a characteristic of acting as a capacitor when a rated voltage, which is a normal operating voltage, is applied, not an overvoltage.

When the first external terminal 42 of FIG. 3 is used as the input terminal IN of FIG. 4 and the second external terminal 44 of FIG. 3 is used as the output terminal OUT of FIG. 4, the first external terminal 42 of FIG. When a predetermined high frequency signal is input to the external terminal 42, the signal of the predetermined frequency band determined by the resistor R and the capacitors C1 and C2 is directed toward the ground electrode, and a substantial portion of the predetermined high frequency signal is input. This attenuated signal is output to the second external terminal 44 which is an output terminal OUT.

On the contrary, even when the second external terminal 44 used as the output terminal is used as the input terminal and the first external terminal 42 used as the input terminal, the same filtering function is implemented.

5 is a characteristic graph of a conventional stacked chip device. In Fig. 5, characteristic (X) represents insertion loss. When the capacitance values of the capacitor C1 and the capacitor C2 of FIG. 4 are the same, the characteristic (X) shows a characteristic that the insertion loss (i.e., attenuation) decreases for the passbands around about 900 MHz. In the frequency band around 900 MHz (i.e. stop band (a)), the insertion loss is increased.

However, in the conventional stacked chip device exhibiting such an operation characteristic, the attenuation in the stop band a is not so large that the signal removal of the desired frequency band is not performed well. That is, in the cross-sectional view of FIG. 3, capacitances are formed between C1 and G and G2 and G for each unit element, but the parasitic inductance is not formed, but the parasitic inductance is not obtained. .

In the array chip in which four unit elements 40a, 40b, 40c, and 40d are arranged in parallel, the frequency characteristics of each unit element are different from each other. Referring to the unit element 40a and the unit element 40b as an example, the signal input from the input side of the unit element 40a (for example, the first external terminal 42) is the third external terminal which is the common terminal at the shortest distance. Exit to terminal 46. Similarly, in the case of the unit element 40b, the signal input from the input side goes out to the third external terminal 46 at the shortest distance. However, since the unit element 40b has a longer exit length than the unit element 40a and the equivalent inductance increases, the resonance frequency of the unit element 40b is the resonance frequency of the unit element 40a. Will decrease more. As a result, a frequency characteristic difference (frequency deviation) between the unit element 40a and the unit element 40b occurs.

The present invention has been proposed to solve the above-described problems. In the stacked array chip in which a plurality of unit devices are manufactured as one chip, the frequency deviation between the unit devices is improved and the attenuation in the stopband is improved. It is an object of the present invention to provide a stacked chip device.

In order to achieve the above object, a stacked chip device according to a preferred embodiment of the present invention includes an electronic device pattern formed on an upper surface of a body; A first inner electrode pattern formed to be connected to a first outer terminal of the first side of the body; A second inner electrode pattern formed to be connected to a second outer terminal of the second side of the body; A third inner electrode pattern formed to be connected to a third outer terminal of the third side of the body; And auxiliary electrode patterns that are not directly connected to the first to third external terminals,

One side of the electronic device pattern is connected to the first external terminal, the other side of the electronic device pattern is connected to the second external terminal, and a part of the auxiliary electrode pattern is respectively the first and second internal electrode patterns; It is characterized by opposing.

The electronic device pattern is a resistor pattern or an inductor pattern.

The first and second internal electrode patterns are formed to be spaced apart from each other on one sheet, and the auxiliary electrode pattern is formed by interposing a sheet above or below the first and second internal electrode patterns. One side of is opposite to the first inner electrode pattern and the other side of the auxiliary electrode pattern is opposite to the second inner electrode pattern.

The first internal electrode pattern, the second internal electrode pattern, and the auxiliary electrode pattern may be stacked vertically and symmetrically around the third internal electrode pattern, and the first and second internal electrode patterns may be formed around the third internal electrode pattern. Patterns corresponding to the first and second internal electrode patterns and the auxiliary electrode pattern are stacked to be symmetrical with the auxiliary electrode pattern.

The first and second internal electrode patterns may be formed on different sheets in each unit device. In this case, the first to third internal electrode patterns are stacked vertically and symmetrically around the auxiliary electrode pattern, wherein one of the first and second internal electrode patterns and the third internal part are disposed on the auxiliary electrode pattern. An electrode pattern is stacked, and a pattern corresponding to another one of the first and second internal electrode patterns and the third internal electrode pattern is stacked below the auxiliary electrode pattern.

Alternatively, the stacked chip device according to an embodiment of the present invention, the cover sheet is formed on the upper surface of the body and the electronic device pattern is formed; A first inner sheet having a first inner electrode pattern formed to be connected to a first outer terminal of the first side of the body and a second inner electrode pattern formed to be connected to a second outer terminal of the second side of the body; A second inner sheet having a third inner electrode pattern formed to be connected to a third outer terminal of the third side of the body; And an auxiliary inner sheet having an auxiliary electrode pattern not directly connected to the first to third external terminals.

One side of the electronic device pattern is connected to the first external terminal, the other side of the electronic device pattern is connected to the second external terminal, and a part of the auxiliary electrode pattern is respectively the first and second internal electrode patterns; It is characterized by opposing.

Here, the first inner sheet and the auxiliary inner sheet are stacked up and down symmetrically about the second inner sheet.

Alternatively, the stacked chip device according to an embodiment of the present invention, the cover sheet is formed on the electronic device pattern is formed on the upper surface of the body; A first inner sheet having a first inner electrode pattern formed to be connected to a first outer terminal of the first side of the body; A second inner sheet having a second inner electrode pattern formed to be connected to a second outer terminal of the second side of the body; A third inner sheet having a third inner electrode pattern formed to be connected to a third outer terminal of the third side of the body; And an auxiliary inner sheet having an auxiliary electrode pattern not directly connected to the first to third external terminals.

One side of the electronic device pattern is connected to the first external terminal, the other side of the electronic device pattern is connected to the second external terminal, and a part of the auxiliary electrode pattern is respectively the first and second internal electrode patterns; It is characterized by opposing.

Here, one of the first and second inner sheets and the third inner sheet are laminated on the upper portion of the auxiliary inner sheet, and the other of the first and second inner sheets is lowered on the lower portion of the auxiliary inner sheet. Sheets corresponding to the third inner sheet are laminated.

Hereinafter, a multilayer chip device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

(Description of the first embodiment)

FIG. 6 is an external perspective view of a stacked chip device according to a first embodiment of the present invention, in which the stacked chip device of the present invention is identical to the conventional stacked chip device described above, and is different from the pattern stacked structure inside the body.

That is, in the stacked chip device of the first embodiment, the first to third external terminals 62, 64, and 66 are formed on the side surface of the body 60, and the resistor pattern 68 is formed on the upper surface of the body 60. It is formed for each unit element 60a, 60b, 60c, 60d. That is, the first outer terminal 62 is formed to be spaced apart from each other on one side portion of the body 60 is connected to the inner electrode pattern (not shown) exposed to the side portion and one end thereof extends to the upper surface of the body 60 . The second outer terminal 64 is formed to be spaced apart from each other on a side portion opposite to the side portion on which the first outer terminal 62 is formed, and is connected to an internal electrode pattern (not shown) exposed to the side portion, and one end is the body 60. Extends to the top of the surface. The third outer terminal 66 is formed at each of the two opposite side portions of the body 60 and is connected to an inner electrode pattern (not shown) exposed to the corresponding side portion, and one end thereof extends upward. The third external terminal 66 is a common terminal (ground electrode). The resistor pattern 68 is formed to interconnect the first and second external terminals 62 and 64 which face each other on the upper surface of the body 60.

FIG. 7 is a perspective view illustrating a stacked structure of a pattern employed in the first embodiment of the present invention, in which the first sheet 10 and the third inner electrode pattern 12 having the first and second inner electrode patterns 12 and 14 are formed; And a second sheet 20 on which 22 is formed, a third sheet 50 on which the auxiliary electrode pattern 52 is formed, and a cover sheet 30. Since the third sheet 50 is further provided as compared with FIG. 2, the same reference numerals are given to the same elements as those described in FIG. 2, and the description thereof will be described with reference to FIG. 2. Replace.

An auxiliary electrode pattern 52 is formed in each of the unit elements 60a, 60b, 60c, and 60d in the third sheet 50. The auxiliary electrode pattern 52 is not directly connected to any of the first to third external terminals 62, 64, and 66. The separation distance between the auxiliary electrode patterns 52 formed for each unit element 60a, 60b, 60c, or 60d is the same. Of course, if necessary, the separation distances between the auxiliary electrode patterns 52 may be adjusted differently. In this case, the arrangement of the resistor pattern 68 and the internal electrode patterns 12 and 14 formed for each unit element 60a, 60b, 60c, or 60d may also be adjusted. Then, in order to improve the frequency deviation between the unit elements 60a, 60b, 60c, and 60d (that is, to match), the auxiliary electrode pattern 52 formed for each of the unit elements 60a, 60b, 60c, and 60d may be used. It is desirable to vary the size (area). The auxiliary electrode pattern 52 is also referred to as a floating electrode pattern.

FIG. 8 is a cross-sectional view of any one of the unit devices 60a, 60b, 60c, and 60d of the stacked chip device of FIG. 6 vertically cut, C1 corresponding to the first internal electrode pattern 12, and C2. Corresponds to the second internal electrode pattern 14. C3 corresponds to the auxiliary electrode pattern 52 and G corresponds to the third internal electrode pattern 22. C1 may be referred to as a first internal electrode, C2 may be referred to as a second internal electrode, C3 may be referred to as an auxiliary electrode, and G may be referred to as a third internal electrode.

9 is an equivalent circuit diagram of FIG. 8. A resistor R is connected between the input terminal IN and the output terminal OUT, and capacitors C1 and C2 are connected between both ends of the resistor R and ground. The capacitor C3 is connected in series with the capacitors C1 and C2.

The input terminal IN and the output terminal OUT of FIG. 9 correspond to the first and second external terminals 42 and 44 of FIG. 8, and the resistor R of FIG. 9 corresponds to the resistor pattern 68 of FIG. 8. do. An electrode connected to the input terminal IN of the two electrodes of the capacitor C1 of FIG. 9 becomes C1 of FIG. 8, and an electrode connected to the output terminal OUT of the two electrodes of the capacitor C2 of FIG. 9 is illustrated in FIG. It becomes C2 of 8. Thus, capacitor C1 of FIG. 9 has a capacitance formed between C1 and G of FIG. 8. The capacitor C2 of FIG. 9 has a capacitance formed between C2 and G of FIG. 8. And capacitor C3 of FIG. 9 has a capacitance between C1 and C3 of FIG. 8 and a capacitance between C2 and C3. Accordingly, those skilled in the art will be described with reference to C1, C2, and C3 of FIG. 9 for the case of C1, C2, C3, C4, C5, and C6 of the second and third embodiments to be described later. It is well understood.

In Fig. 9, C1 and C2 may be viewed as varistors. FIG. 9 shows a capacitor C3 installed in series in a typical PI-type RC filter structure. This structure has a characteristic of acting as a capacitor when a varistor is applied with a normal operating voltage instead of an overvoltage. .

When the first external terminal 62 of FIG. 8 is used as the input terminal IN of FIG. 9 and the second external terminal 64 of FIG. 8 is used as the output terminal OUT of FIG. 9, the first external terminal 62 of FIG. 1 When a predetermined high frequency signal is input to the external terminal 62, the signal of the predetermined frequency band determined by the resistor R and the capacitors C1 and C2 is directed toward the ground electrode, and a substantial portion of the predetermined high frequency signal is input. This attenuated signal is output to the second external terminal 64 which is an output terminal OUT. At this time, the capacitance is also formed by the capacitor C3 connected in series with the capacitors C1 and C2, thereby further improving attenuation characteristics. In other words, when the resonant frequencies of the capacitors C1, C2, and C3 of FIG. 9 are adjusted to be equal to each other, the attenuation poles appear to be one as shown in FIG. 10, and the order of the filters increases. The insertion loss characteristic (Y) is better than the insertion loss characteristic (X) of the stacked chip device. That is, the conventional stacked chip device and the stacked chip device of the present invention can be seen that the insertion loss (that is, attenuation) is increased in the frequency band (i.e., stop band (a)) of about 900MHz, about 900MHz frequency band ( That is, since the insertion loss amount of the conventional stacked chip device in the stop band (a) is about 32 dB and the insertion loss amount of the stacked chip device according to the embodiment of the present invention is about 49 dB, in the stacked chip device according to the embodiment of the present invention, It can be seen that the insertion loss characteristic of is superior to the insertion loss characteristic of the conventional stacked chip device. In Fig. 10, Y denotes a characteristic of insertion loss due to the structure of the first embodiment. Of course, by adjusting the capacitances of the capacitors C1, C2, and C3 and their equivalent series inductance values, the resonant frequency of each unit element can be changed, thereby widening the bandwidth. As described above, the present invention can freely adjust each capacitance value.

As such, the attenuation characteristic in the stop band a is improved, so that signal removal in a desired frequency band can be reliably performed as compared with a conventional stacked chip element.

On the contrary, even though the second external terminal 64 used as the output terminal in the description of FIG. 9 is used as the input terminal and the first external terminal 62 used as the input terminal, the same filtering function as described above is realized. Done.

On the other hand, for example, the auxiliary electrode pattern 52 and the first and second internal electrode patterns 12 and 14 formed on the inner unit elements 60b and 60c among the unit elements 60a, 60b, 60c, and 60d, and If the opposing area of is different from the opposing area between the auxiliary electrode pattern 52 formed in the outer unit elements 60a and 60d and the first and second internal electrode patterns 12 and 14, the resonance frequency of each unit element is different. The value can be adjusted to correct the deviation between the channels in the unit elements 60b and 60c, thereby improving the frequency deviation between the unit elements 60a, 60b, 60c and 60d.

11 is a view for explaining a manufacturing process of the stacked chip device according to the first embodiment of the present invention. The following manufacturing process is merely one example of various manufacturing processes capable of manufacturing the stacked chip device of the first embodiment of the present invention, and is not limited to the following manufacturing process. Any method can be adopted as long as it can produce the stacked chip device to be implemented in the present invention without following the manufacturing process as it is.

First, a desired molded sheet for an element is produced. If the varistor element is manufactured, a ball mill (ball or ball) is used for 24 hours using water or alcohol in a desired composition using raw material powder of a commercial varistor element or adding an additive such as Bi ₂ O ₃ , CoO, MnO to ZnO powder. mill) to prepare the raw powder. In order to prepare a molded sheet, PVB-based binder (Binder) is measured as an additive to the prepared varistor powder, and then dissolved in toluene / alcohol (toluene / alcohol) -based solvent (solvent) as an additive. A slurry is prepared by milling and mixing for about 24 hours in a small ball mill. This slurry is manufactured into a molded sheet having a desired thickness by a method such as a doctor blade. At this time, the raw material powder of the composition for the capacitor element, the raw material powder of the composition for the PTC (positive temperature coefficient) thermistor element, or the raw material powder of the composition for the negative temperature coefficient (NTC) thermistor element is also produced into a molded sheet having a desired thickness in the same manner. can do.

A sheet having an internal electrode pattern is formed by forming a conductive paste such as Ag, Pt, or Pd on a formed sheet by forming a thin film such as screen printing, or a thin film manufacturing method such as sputtering, evaporation, vapor chemical vapor deposition, or sol gel coating. do.

That is, as shown in FIG. 7, the plurality of first inner electrode patterns 12 extend from one end in the lateral direction to the other end and the plurality of second inner electrode patterns 14 extend from the other end in the lateral direction to the one end. A second sheet 20 having a first sheet 10 formed therein and having a third inner electrode pattern 22 crossing both opposing ends in a direction crossing the first and second inner electrode patterns 12 and 14. ), And each of the unit elements 60a, 60b, 60c, and 60d has a second electrode pattern 52 formed therein, which is not connected to any one of the first to third external terminals 62, 64, and 66. The sheet 50 is manufactured.

Subsequently, the first sheet 10 is laminated on the second sheet 20 as the lowermost layer, the third sheet 50 is laminated thereon, and the cover sheet 30 is laminated. After that, it is crimped, and then a cutting, baking out, and firing process is sequentially performed to form a desired body 60 (see FIG. 11A). It is considered that the capacitor C of the R-C filter or the varistor of the R-V filter is implemented to implement the EMI characteristic. In the first embodiment, the number of sheets on which patterns are formed is three, but the number of sheets may be four or more. That is, the capacitance value may be adjusted by forming a single chip by stacking four or more manufactured first to third sheets 10, 20, and 50 in various combinations. In addition, the shapes of the patterns formed on the first sheet 10, the second sheet 20, and the third sheet 50 may be different from those of FIG. 7. In FIG. 11A, four unit elements constituting the body 60 are used, but at least one unit may be used. This is applied to the following description of the embodiment as it is.

Subsequently, in order to connect the internal electrode patterns 12 and 14 formed inside the body 60 and the resistor pattern 68 to be formed on the upper surface and to facilitate surface mounting, the body (using a conventional termination system) may be used. First to third external terminals 62, 64, and 66 are formed on the side surface of the 60. That is, the first outer terminal 62 is formed to be spaced apart from each other on one side portion of the body 60, but connected to each of the inner electrode pattern 12 (more precisely the extension 12a) exposed to the side portion once It extends to the upper surface of the body 60. The second outer terminal 64 is formed to be spaced apart from each other on a side portion opposite to the side portion on which the first outer terminal 62 is formed, and each of the inner electrode patterns 14 exposed to the side portion; more precisely, the extension portion 14a. ) And one end is extended to the upper surface of the body (60). The third outer terminal 66 is formed on another side portion of the body 60 and is connected to the inner electrode pattern 22 (more precisely, the extension portion 22a) exposed to the side portion, and one end thereof extends upward. In FIG. 11B, only one third external terminal 66 is visible, but the same external terminal as that of the third external terminal 66 is also formed on the side portion opposite to the side portion where the third external terminal 66 is visible. Of course, you may form the 3rd external terminal 66 only in any one side part as needed.

Subsequently, the first heat treatment is performed at a temperature of about 500 to 850 ° C. in order to bond the first to third external terminals 62, 64, and 66 with the ceramic body 60.

After the first heat treatment, a resistor pattern 68 is formed on the upper surface of the body 60 as shown in FIG. 11C to implement the resistance R of the RC filter or the RV filter. The term "electronic device pattern" in the claims of the present invention includes all of the conductive patterns including predetermined resistances such as the inductor pattern including the resistor pattern. The resistor pattern 68 forming process is to adjust the insertion loss and the resonant frequency of the EMI filter, to increase the noise attenuation effect, and to electrically connect the input / output terminals to serve as a data transmission line. The resistor pattern 68 is implemented through a printing process using a paste having a constant sheet resistance value by adding glass, Pd, Ti, and the like to a conductor based on RuO ₂ . That is, the resistor pattern 68 is formed in each unit element 60a, 60b, 60c, 60d in a straight line as shown in FIG. Accordingly, the bottom of one side of the resistor pattern 68 is printed to be connected to the top of one end of the first outer terminal 62 and the bottom of the other side to be connected to the top of one end of the second outer terminal 64. .

In general, the resistance value is inversely proportional to the printing width and thickness of the resistor and directly proportional to the length. When the external terminals 62 and 64 are directly used as pads for resistance printing, the shortest distance between both ends of the external terminals 62 and 64 exposed on the upper surface of the body 60 may not be constant, which may cause difficulty in adjusting the resistance tolerance. do. Therefore, after forming conductive metal pads on the first and second external terminals 62 and 64 to facilitate contact with the external terminals 62 and 64 and to uniformly control the separation distance, the resistor pattern 68 is formed. ) May be formed.

When the resistor pattern 68 is formed, secondary heat treatment is performed on the bodies on which the resistor pattern 68 is formed. The first to third external terminals 62, 64, and 66 and the resistor pattern 68 are coupled to each other by the secondary heat treatment. The temperature at the time of secondary heat treatment is about 500-850 degreeC.

After the second heat treatment, in order to protect the upper surface of the body 60 on which the resistor pattern 68 is formed from an external environment such as moisture, overglazing is performed using a material such as glass or epoxy.

In this way, the stacked chip element of the first embodiment is manufactured. On the other hand, in the above description of the first embodiment, the external terminal 62, 64, 66 is formed and then the resistor pattern 68 is formed. On the contrary, after the resistor pattern 68 is formed, the external terminal 62, 64 and 66) may be formed.

(Explanation of the second embodiment)

12 is a schematic cross-sectional view of a stacked chip device according to a second exemplary embodiment of the present invention, and has a structure in consideration of the directionality of a manufacturing process of the stacked chip device. In general, in manufacturing a stacked chip device, a plurality of sheets having various internal electrode patterns formed thereon are stacked to form a body, and then a resistor pattern is formed on a top cover sheet of the body. Therefore, since the resistor pattern is formed only on the upper surface of the body, there is a hassle to distinguish the orientation of the upper surface and the lower surface of the body. If the resistive pattern is formed without the upper and lower sorting of the bodies mixed with the upper and lower parts, not only the normal product having the resistor pattern formed on the upper surface of the body but also the abnormal products having the resistor pattern formed on the lower surface of the body result in increased production yield. Dropped.

Therefore, in order to eliminate the time required for top and bottom sorting and the decrease in production yield, the second embodiment is configured to be vertically symmetric about the internal electrode pattern G to be connected to the third external terminal, which is a common terminal. That is, when FIG. 12 is compared with FIG. 8, the first to third internal electrode patterns C1, C2, and G and the auxiliary electrode pattern C3 are formed inside the body of FIGS. 12 and 8. 12 are the same, but in FIG. 12, auxiliary electrodes having the same shape as the internal electrode patterns C4 and C5 and the auxiliary electrode pattern C3 having the same shape as the first and second internal electrode patterns C1 and C2. The pattern C6 is further provided below the third inner electrode pattern G.

When the inside of the body is configured as described above, since the pattern stacking structure inside the body is stacked vertically and symmetrically, when the resistor pattern is formed, the resistor pattern can be immediately formed without selecting the top and bottom parts of the body. Although not shown in the equivalent circuit diagram of FIG. 12, the auxiliary electrode pattern C3 is connected in series to the first and second internal electrode patterns C1 and C2, and the auxiliary electrode pattern C6 is an internal electrode. It is connected in series to the patterns C4 and C5.

 FIG. 12 described above shows the structure of the second embodiment of the present invention so as to be convenient for comparison with the first embodiment, and more precisely, reference numerals C1, C2, C3, C4, C5, C6, and G described in FIG. The capacitance in may be understood according to the description of FIGS. 8 and 9 described above. Anyone can appreciate this understanding will be apparent to those skilled in the art.

The structure of FIG. 12 described above is particularly useful when free space is generated depending on the total size of the body and the capacitance value to be implemented. The structure of FIG. 12 has an insertion loss characteristic superior to that of the conventional structure as in the first embodiment described above. In particular, the attenuation electrode having a larger capacitance than that of the first embodiment has a larger insertion loss than that of the first embodiment. You get

And, the structure of Fig. 12 can be sufficiently manufactured by manufacturing according to the manufacturing process in the above-described first embodiment.

(Description of the third embodiment)

FIG. 13 is a schematic cross-sectional view of a stacked chip device according to a third exemplary embodiment of the present invention, and FIG. 14 is a perspective view illustrating a stacked structure of a pattern employed in the third exemplary embodiment of the present invention. The structure of the third embodiment is also a structure in consideration of the directionality of the manufacturing process of the stacked chip device as in the second embodiment.

In the third embodiment, in order to eliminate the time required for top and bottom sorting and the decrease in production yield, the top and bottom point symmetry is configured around the auxiliary electrode pattern C3. As compared with the second embodiment, the number of sheets laminated inside the body is equal to five. However, while the second embodiment has a structure in which the first inner electrode pattern C1 and the second inner electrode pattern C2 are formed in one sheet, the third embodiment has a structure in which the first inner electrode pattern C1 and the first inner electrode pattern C1 are formed. The second internal electrode pattern C2 is formed on different sheets. In addition, while the second embodiment has a structure in which the auxiliary electrode pattern C3 and the pattern C6 corresponding to the auxiliary electrode pattern are stacked on the uppermost and lowermost portions inside the body, the third embodiment has a third internal electrode pattern ( The structure G2) and the pattern G2 corresponding to the third internal electrode pattern are laminated on the uppermost and lowermost part in the body.

The first inner electrode pattern C1 of FIG. 13 corresponds to the pattern 72 of the sheet 70 in FIG. 14, and the second inner electrode pattern C2 of FIG. 13 corresponds to the pattern of the sheet 80 in FIG. 82). In addition, the third internal electrode pattern G1 of FIG. 13 corresponds to the pattern 92 of the sheet 90 in FIG. 14, and the internal electrode pattern G2 of FIG. 13 corresponds to the pattern of the sheet 110 in FIG. 14. 112). In addition, the auxiliary electrode pattern C3 in FIG. 13 corresponds to the pattern 102 of the sheet 100 in FIG. 14. Although the extension part was formed in each pattern also in FIG. 14, it is not necessary to form the extension part. In FIG. 14, the pattern 72 is connected to the first external terminal (not shown), the pattern 82 is connected to the second external terminal (not shown), and the patterns 92 and 112 are connected to the third external terminal. (Not shown). However, in FIG. 14 the pattern 102 is not directly connected to any external terminals. In addition, although the cover sheet in which the resistor pattern 68 of FIG. 13 is formed is not illustrated in FIG. 14, the cover sheet is naturally provided.

The first and second internal electrode patterns C1 and C2 of FIG. 13 may be different from the pattern forming structure of FIG. 14. For example, although all the patterns are formed in the sheet | seat 70 of FIG. 14 from the one end part to the other end side in the lateral direction of the sheet | seat, respectively, you may form this in meandering form. That is, in the pattern formation structure of the sheet 70, the first and third patterns may be left as it is, and the remaining second and fourth patterns may be opposite shapes (that is, the same shape as the pattern 82). In this case, the second and fourth patterns in the pattern forming structure of the sheet 80 of FIG. 14 should be left as they are, and the remaining first and third patterns should be in opposite shapes (that is, the same shape as the pattern 72).

On the other hand, although the equivalent circuit diagram for Figure 13 is not shown, the auxiliary electrode pattern (C3) is connected in series with the first and second internal electrode patterns (C1, C2).

FIG. 13 described above shows the structure of the third embodiment of the present invention so as to be convenient for comparison with the first embodiment, and more precisely, the capacitance between reference numerals C1, C2, C3, G1, G2 described in FIG. It should be understood according to the description of Figs. 8 and 9 described above. Anyone can appreciate this understanding will be apparent to those skilled in the art.

The structure of FIG. 13 described above is particularly useful when free space is generated depending on the total size of the body and the capacitance value to be implemented. The structure of FIG. 13 has an insertion loss characteristic superior to that of the conventional structure as in the first embodiment described above. In particular, the attenuation electrode having a larger capacitance than that of the first embodiment has a larger insertion loss than that of the first embodiment. You get

In addition, the structure of the third embodiment is different in the pattern forming process as compared with the first and second embodiments described above, and the rest of the manufacturing process is not very different. Therefore, those skilled in the art who can manufacture the structure of the above-described first or second embodiment can sufficiently manufacture the structure of the third embodiment using conventional techniques well known.

(Description of the fourth embodiment)

FIG. 15 is a perspective view showing a stacked structure of a pattern employed in the fourth embodiment of the present invention, and FIG. 16 is a schematic cross-sectional view of the stacked chip device according to the fourth embodiment of the present invention. The fourth embodiment has a structure in which the number of manufacturing processes can be reduced by reducing the number of stacked sheets of the stacked chip element.

Although the fourth embodiment has a structure in which all of the above-described first to third embodiments are contrasted with each other, even if only the differences from the first embodiment are explained, the fourth embodiment can be clearly seen as a difference from the other embodiments. The explanation of the difference from the example is omitted.

In order to implement the stacked chip device of the first embodiment, at least four sheets are required as shown in FIG. 7, but in the fourth embodiment, three sheets are possible as shown in FIG. 15. The fourth embodiment differs from the first embodiment in that all of the first to third internal electrode patterns of the first embodiment are formed in one sheet.

The first sheet 120 of the fourth embodiment has a first internal electrode pattern 122 and a second internal electrode pattern 124 formed on both opposing end sides, and the first and second internal electrode patterns 122, respectively. And a third internal electrode pattern 126 for the common terminal spaced apart from the first and second internal electrode patterns 122 and 124 and intersecting with the direction connecting the opposite ends. Here, the first to third internal electrode patterns 122, 124, and 126 are formed on the sheet 120 using a silk screen printing technique, and are simultaneously printed on respective predetermined areas.

In the second sheet 130 of the fourth embodiment, the auxiliary electrode pattern 132 is formed as in the third sheet of the first embodiment. The cover sheet 140 of the fourth embodiment may be regarded as the same as the cover sheet of the first embodiment.

A person skilled in the art can sufficiently manufacture the first and second sheets 120 and 130 and the cover sheet 140 based on the sheet manufacturing process of the first embodiment described above, and thus a detailed description thereof will be omitted.

When the first and second sheets 120 and 130 and the cover sheet 140 are manufactured in this manner, the second sheet 130 is laminated on the first sheet 120 as the lowermost layer, and then the cover sheet 140 is formed. )). After that, it is compressed and then a cutting, baking out, and baking process are carried out sequentially to form a desired body. After that, when the external terminal forming process and the resistive pattern forming process are performed on the upper surface of the body, a stacked chip element is manufactured. The description of the external terminal forming process and the resistor pattern forming process can also be replaced by the description of the corresponding forming process in the above-described first embodiment, which will be fully understood by those skilled in the art according to the above-described description of the first embodiment.

When one unit device of the manufactured stacked chip device is vertically cut, it has a cross-sectional structure as shown in FIG. In Fig. 16, reference numeral 62 denotes a first external terminal formed on the first side portion of the body, reference numeral 64 denotes a second external terminal formed on the second side portion opposite to the first side portion, and reference numeral 68 denotes a cover sheet 140. It is a resistor pattern formed on the upper surface of). The first and second external terminals 62 and 64 and the resistor pattern 68 can be sufficiently understood by referring to the first embodiment described above.

Although the third external terminal is not shown in Figs. 15 and 16, the third external terminal is formed on a side surface different from the side parts on which the first and second external terminals 62 and 64 are formed as in the first embodiment. And a third internal electrode pattern 126 for a common terminal. The third external terminal can be sufficiently seen by referring to the first embodiment described above.

The equivalent circuit diagram of FIG. 16 is the same as the equivalent circuit diagram of FIG. In FIG. 16, a capacitor having capacitance in the overlapping area between the first inner electrode pattern 122 and the auxiliary electrode pattern 132 and the overlapping area between the third inner electrode pattern 126 and the auxiliary electrode pattern 132 is shown in FIG. 9. A capacitor having a capacitance in the overlapping area between the second inner electrode pattern 124 and the auxiliary electrode pattern 132 and the overlapping area between the third inner electrode pattern 126 and the auxiliary electrode pattern 132. 9 may be referred to as C2 of FIG. 9, and the capacitance at the overlapped area between the first inner electrode pattern 122 and the auxiliary electrode pattern 132 and the overlapped area between the second inner electrode pattern 124 and the auxiliary electrode pattern 132 may be referred to as C2 of FIG. The capacitor having a may be referred to as C3 of FIG.

According to the fourth embodiment configured as described above, the number of sheets stacked may be reduced compared to the above-described embodiments, thereby reducing the number of manufacturing processes. As a result, the size of the chip device can be made more compact.

In addition, various capacitance values may be adjusted by variously combining the first sheet 120 and the second sheet 130.

On the other hand, although not shown in the figure, it is also possible to reduce the size of G in Fig. 8 to eliminate the overlapping area with C1 and C2 and to have a structure with only the overlapping area with C3.

As described in detail above, according to the present invention, by adding a sheet formed with an electrode pattern not connected to any external terminal, but by circuitry in series with other capacitors (or varistors) of the body, the attenuation characteristics of the conventional filter Compared with the improved damping properties.

In particular, it is possible to effectively improve the frequency deviation between the unit elements of the arrayed filter to be a very useful chip element.

On the other hand, the present invention is not limited only to the above-described embodiment, but can be modified and modified within the scope not departing from the gist of the present invention, the technical idea to which such modifications and variations are also applied to the claims Must see

Claims (17)

An electronic device pattern formed on the upper surface of the body; A first inner electrode pattern formed to be connected to a first outer terminal of the first side of the body; A second inner electrode pattern formed to be connected to a second outer terminal of the second side of the body; A third inner electrode pattern formed to be connected to a third outer terminal of the third side of the body; And An auxiliary electrode pattern not directly connected to the first to third external terminals; One side of the electronic device pattern is connected to the first external terminal, the other side of the electronic device pattern is connected to the second external terminal, and a part of the auxiliary electrode pattern is respectively the first and second internal electrode patterns; Laminated chip device, characterized in that opposed. The method of claim 1, The electronic device pattern is a stacked chip device, characterized in that the resistor pattern or inductor pattern. The method of claim 1, The stacked chip device may include a plurality of unit devices arranged in parallel to form an array chip. The method according to any one of claims 1 to 3, The first and second internal electrode pattern is a stacked chip device, characterized in that formed in one sheet spaced apart from each other. The method of claim 4, wherein The auxiliary electrode pattern is a stacked chip device, characterized in that formed on the upper or lower portion of the first and second internal electrode patterns via a sheet. The method according to any one of claims 1 to 3, The first chip electrode, the second internal electrode pattern and the auxiliary electrode pattern is a stacked chip device, characterized in that stacked up and down symmetrical around the third internal electrode pattern. The method of claim 6, Patterns corresponding to the first and second internal electrode patterns and the auxiliary electrode pattern are stacked to be symmetrical with the first and second internal electrode patterns and the auxiliary electrode pattern based on the third internal electrode pattern. Stacked Chip Device. The method of claim 3, wherein The first chip and the second internal electrode pattern is a stacked chip device, characterized in that formed in different sheets in each unit device. The method of claim 8, The first to third internal electrode patterns are stacked vertically and symmetrically with respect to the auxiliary electrode pattern. The method according to claim 8 or 9, One of the first and second internal electrode patterns and the third internal electrode pattern are stacked on the auxiliary electrode pattern, and the other of the first and second internal electrode patterns on the bottom of the auxiliary electrode pattern. And a pattern corresponding to the third internal electrode pattern is stacked. The method according to any one of claims 1 to 3, The first to third internal electrode patterns are formed in a single sheet spaced apart from each other stacked chip device. A cover sheet on which an electronic device pattern is formed and disposed on an upper surface of the body; A first inner sheet having a first inner electrode pattern formed to be connected to a first outer terminal of the first side of the body and a second inner electrode pattern formed to be connected to a second outer terminal of the second side of the body; A second inner sheet having a third inner electrode pattern formed to be connected to a third outer terminal of the third side of the body; And An auxiliary inner sheet having an auxiliary electrode pattern not directly connected to the first to third external terminals, One side of the electronic device pattern is connected to the first external terminal, the other side of the electronic device pattern is connected to the second external terminal, and a part of the auxiliary electrode pattern is respectively the first and second internal electrode patterns; Laminated chip device, characterized in that opposed. The method of claim 12, The first inner sheet and the auxiliary inner sheet is stacked chip element, characterized in that stacked up and down symmetrical around the second inner sheet. A cover sheet on which an electronic device pattern is formed and disposed on an upper surface of the body; A first inner sheet having a first inner electrode pattern formed to be connected to a first outer terminal of the first side of the body; A second inner sheet having a second inner electrode pattern formed to be connected to a second outer terminal of the second side of the body; A third inner sheet having a third inner electrode pattern formed to be connected to a third outer terminal of the third side of the body; And An auxiliary inner sheet having an auxiliary electrode pattern not directly connected to the first to third external terminals, One side of the electronic device pattern is connected to the first external terminal, the other side of the electronic device pattern is connected to the second external terminal, and a part of the auxiliary electrode pattern is respectively the first and second internal electrode patterns; Laminated chip device, characterized in that opposed. The method of claim 14, One of the first and second inner sheets and the third inner sheet are stacked on an upper portion of the auxiliary inner sheet, and the other of the first and second inner sheets and the first sheet is stacked on a lower portion of the auxiliary inner sheet. 3. A stacked chip device, wherein a sheet corresponding to an inner sheet is stacked. A cover sheet on which an electronic device pattern is formed and disposed on an upper surface of the body; A first inner electrode pattern formed to be connected to a first outer terminal of the first side of the body, and a second second electrode formed to be connected to a second outer terminal of the second side of the body and spaced apart from the first inner electrode pattern First and second internal electrodes connected to an internal electrode pattern and a third external terminal on the third side of the body and spaced apart from the first and second internal electrode patterns and between the first and second internal electrode patterns An inner sheet having a third inner electrode pattern formed in a direction crossing the direction connecting the patterns; And An auxiliary inner sheet having an auxiliary electrode pattern not directly connected to the first to third external terminals, One side of the electronic device pattern is connected to the first external terminal, the other side of the electronic device pattern is connected to the second external terminal, and a part of the auxiliary electrode pattern is respectively the first to third internal electrode patterns; Laminated chip device, characterized in that opposed. The method according to any one of claims 12 to 16, The stacked chip device may include a plurality of unit devices arranged in parallel to form an array chip.

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