KR100578296B1 - Inductor-Capacitor Composite Multilayer Chip Devices - Google Patents

Abstract

The present invention relates to a laminate in which a first laminate sheet portion in which a first electrode, a common electrode and a second electrode are formed, and a second laminate sheet portion in which an inductor pattern is formed are stacked, and the first electrode is disposed on an outer surface of the laminate. First and third external terminal electrodes respectively connected to the electrode and the second electrode, wherein the first external terminal electrode is connected to one terminal of the inductor pattern and the first electrode, and the third external terminal electrode is Provided is a composite stacked chip device connected to the other terminal of the inductor pattern and the second electrode and having a linear or plate shape in which the first and second electrode ends are refracted by an outer axis. By combining multiple passive elements in a single chip, it is possible to improve frequency characteristics, protect internal circuits from external overvoltage and static electricity, simplify the pattern of stacked chips, and space between internal electrode patterns. By varying the shape and the pattern, it is possible to reduce the difference in frequency characteristics between the multiple chips and provide various types of filters composed of inductors and capacitors.

Multilayer Chips, Varistors, Inductors, Capacitors, Filters

Description

Laminated complex chip element of combining with inductor and capacitor

1 is a graph for explaining the frequency characteristics of the device according to the present invention.

2 is a manufacturing process diagram of the stacked chip device according to the first embodiment of the present invention.

3 is an equivalent circuit diagram of a stacked chip device according to a first embodiment of the present invention.

4 is a manufacturing process diagram of the laminated chip device according to the second embodiment of the present invention.

5 is a manufacturing process diagram of the laminated chip device according to the third embodiment of the present invention.

6 is a manufacturing process diagram of the laminated chip device according to the fourth embodiment of the present invention.

7 is a manufacturing process diagram of the laminated chip device according to the fifth embodiment of the present invention.

8A and 8B are manufacturing process diagrams of a stacked chip device according to a sixth embodiment of the present invention.

9A and 9B are manufacturing process diagrams of a stacked chip device according to a seventh embodiment of the present invention.

10 is an equivalent circuit diagram of a stacked chip device according to a seventh embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

Electrodes: 11, 31, 121, 122, 211, 231, 311, 331, 411, 431, 511, 531, 611, 631, 711, 731, 811, 831, 921

Common electrode: 21, 111, 131, 221, 321, 421, 521, 621, 721, 821, 911

Inductor pattern: 50, 150, 250, 350, 450, 550, 650, 750, 951, 952, 953, 954, 951a, 952a, 951, 952, 953, 954, 951a, 952a

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inductor-capacitor composite multilayer chip device. The present invention relates to a multilayer chip device that is excellent in high frequency characteristics and that can be fabricated to combine desired elements to have desired electrical characteristics.

Representative passive elements in electronic circuits include resistors (R), capacitors (C), and inductors (L), and their functions and roles vary widely. For example, the resistor controls the flow of current through the circuit and also plays a role in achieving impedance matching in the AC circuit. Capacitors basically block DC and pass AC signals, but they also form time constant circuits, time delay circuits, RC and LC filter circuits, and the capacitor itself also removes noise. In the case of the inductor, it removes high frequency noise and performs impedance matching.

In addition, the varistor element is widely used as a protection element to protect important electronic components and circuits from overvoltage (surge voltage) and static electricity because the resistance changes according to the applied voltage. In other words, current does not flow to a varistor element disposed in a circuit, but if an overvoltage is applied to both ends of a varistor element due to an overvoltage or lightning strike over a certain voltage, the resistance of the varistor element is rapidly decreased, and almost all currents flow through the varistor element. No current flows through the device, which protects the circuit from overvoltages. In particular, such varistor devices have recently been miniaturized and arrayed in order to protect high integration circuit chip devices from static electricity and overvoltage in response to the miniaturization of electronic devices.

The combination of the varistor element and the resistance element as described above not only effectively protects important electronic components and circuits from overvoltage, but also eliminates noise components by combining the varistor element and inductor elements. Can ensure stable operation.

In the absence of an overvoltage, the resistor-varistor coupling element performs the coupling element function of the resistor-capacitor. In addition, the combination of the inductor-varistor can realize a pi (π) type filter made of an inductor-capacitor with good high frequency noise rejection. Such a resistance-varistor coupling element or an inductor-varistor coupling element immediately exhibits the function of a varistor when an abnormal overvoltage flows in a circuit, thereby blocking the overvoltage as described above. In general, typical passive devices, such as resistors, inductors, and capacitors, can be properly combined with each other to perform impedance matching, high frequency and low frequency noise cancellation, or select a signal in a specific frequency band.

FIG. 1 is a graph showing the characteristics of a low pass filter of a pie type high frequency noise filter using a passive element, and the solid line shows the characteristics of a pie type filter (LC type) including an inductor (L) and a capacitor (C). , Dotted line shows the characteristic of the piezoelectric filter (RC) consisting of a resistor (R) and a capacitor (C). As shown in FIG. 1, the LC type of the piezoelectric filter exhibits a good Chebyshev characteristic due to the L component. It is possible to drastically reduce the insertion loss after the cut-off frequency. In addition, it can be confirmed that there is no signal attenuation due to the resistance component. However, from the standpoint of digital signals, problems such as overshooting or group delay of signals occur due to excessive L values. In the case of the RC type, there is a problem that signal attenuation occurs due to the R component. In recent mobile phones, the noise band is fixed at 800MHz to 1.8GHz, which is the main carrier frequency band. In other words, components of this frequency band act as noise from an audio or video signal point of view. The frequency of audio and video signals is getting higher and higher as the demand for high-speed data transmission increases. Therefore, there is a need for a low pass filter having good cut-off characteristics such as the LC type to increase the baseband processing frequency while removing high frequency noise.

When the passive element is used as each single element in an electronic circuit including a low pass filter circuit, the length of the conducting wire through which the current flows becomes long, so that the equivalent series inductance value and the equivalent series resistance value are different. Therefore, a high frequency current does not flow well, and the insertion loss may increase due to the power consumed by each device. For this reason, a multilayer chip device in which various devices are combined has been developed.

However, it is difficult for the conventional stacked chip device to precisely adjust various characteristics required for the circuit system, for example, resonance frequency, insertion loss, equivalent series resistance, and the like to the intended use.

In addition, in the conventional stacked chip device, due to the complexity and difficulty in the manufacturing process, it is difficult to manufacture a heterogeneous chip by combining heterogeneous devices in a single chip, and it is difficult to form a plurality of devices that can accommodate a plurality of devices in a single chip.

Accordingly, an object of the present invention is to solve the above problems, by combining a plurality of passive elements in a single chip, it is possible to improve the frequency characteristics, to protect the internal circuit from external overvoltage and static electricity, lamination It is an object of the present invention to provide a composite multilayer chip device capable of simplifying a chip pattern and reducing a difference in frequency characteristics between a plurality of chips when a plurality of chips are manufactured in an array type.

Another object of the present invention is to provide a laminated chip device that can be manufactured to have various high capacitance values as desired while having excellent high frequency characteristics.

Another object of the present invention is to provide a varistor device and a multilayer chip device fabricated by combining various devices for efficiently protecting expensive semiconductor integrated circuits and critical electronic components from overvoltage and static electricity. .

The first electrode, the first electrode, the common electrode and the second electrode and the second laminated sheet portion formed with a second electrode, the inductor pattern formed second laminated sheet portion is laminated and the first electrode is located on the outer surface of the laminate, And first to third external terminal electrodes respectively connected to the common electrode and the second electrode, wherein the first external terminal electrode is connected to one terminal of the inductor pattern and the first electrode, and the third external terminal electrode. Is connected to the other terminal of the inductor pattern and the second electrode, and provides a composite multilayer chip device having linear shapes in which end portions of the first and second electrodes are refracted by the outer axis.

In addition, the first laminated sheet portion formed with the first electrode, the common electrode and the second electrode according to the present invention, the second laminated sheet portion formed with the inductor pattern is laminated and the laminate is located on the outer surface of the first And first to third external terminal electrodes respectively connected to an electrode, a common electrode, and a second electrode, wherein the first external terminal electrode is connected to one terminal of the inductor pattern and the first electrode, and the third external terminal. The terminal electrode is connected to the other terminal of the inductor pattern and the second electrode, and the first and second electrodes provide a composite multilayer chip device having a plate shape.

The laminate may include a first laminate sheet on which the first electrode is formed, a second laminate sheet on which the common electrode is formed, a third laminate sheet on which the second electrode is formed, and an inductor laminate sheet on which the inductor pattern is formed. The first to third laminate sheets may be stacked such that portions of the first and second electrodes overlap with the common electrode, respectively.

The inductor laminated sheet part may include a first inductor laminated sheet on which a first inductor pattern is formed, a second inductor laminated sheet on which a second inductor pattern is formed, and a first through hole connecting the first and second inductor patterns. And a third inductor laminated sheet having a third inductor pattern formed thereon and a second through hole connecting the second and third inductor patterns. In this case, the inductor pattern may be straight, refracted straight or meandering.

The inductor laminated sheet part may include a first inductor laminated sheet having a spiral inductor pattern and a second inductor laminated sheet having a crosslinking pattern formed thereon and a through hole connecting the inductor pattern and the crosslinking pattern.

In this case, each of the first and second electrodes has two electrodes formed on both sides with respect to the center of the first laminated sheet and the third laminated sheet, respectively, and the second and third first and second electrodes positioned at the center are respectively formed. It is effective that the electrodes are adjacent.

The laminate includes a first laminate sheet on which the common electrode is formed, a second laminate sheet formed so that the first and second electrode pairs are spaced apart from each other, and an inductor laminate sheet portion on which the inductor pattern is formed. The third laminated sheet may be laminated so that a part of the first and second electrode pairs overlap the common electrode. Here, the inductor stacking sheet part may include a first inductor stacking sheet in which a first inductor pattern is formed, a second inductor stacking in which a second inductor pattern is formed, and a first through hole connecting the first and second inductor patterns. The sheet and the third inductor pattern is formed, it is preferable to include a third inductor laminated sheet having a second through hole for connecting between the second and third inductor pattern. In this case, the inductor pattern may be at least one of a straight line, a curved straight line, and a meandering line.

The inductor laminated sheet part may include a first inductor laminated sheet having a spiral inductor pattern and a second inductor laminated sheet having a crosslinking pattern formed thereon and a through hole connecting the inductor pattern and the crosslinking pattern. In the first and second electrodes, two electrodes are formed on both sides with respect to the center of the second laminated sheet, and the second and third first and second electrodes positioned at the center are adjacent to each other. to be.

As described above, the multilayer chip device may be manufactured in an array type in a single chip by being arranged in parallel. It is effective that a said 1st laminated sheet part is a varistor sheet.

In addition, a laminate in which one electrode and a common electrode according to the present invention are formed, a laminate in which a second laminate sheet portion in which an inductor pattern is formed is laminated, and first to third external terminal electrodes disposed on an outer surface of the laminate may be formed. Wherein the inductor pattern is connected in series between the first and third external terminal electrodes, the one electrode is connected to a node between the inductor patterns connected in series, and the common electrode is connected to a second external terminal electrode. Provided is a stacked chip device.

The laminate may include a first inductor laminated sheet portion having a first inductor pattern, a first connecting through hole connected to a portion of the first inductor pattern, a first laminated sheet having the common electrode formed thereon, and the one electrode And a second laminated sheet and a second inductor pattern having a second connection through hole connecting the one electrode and the first connection through hole to each other, and a first through hole connecting the second inductor pattern and one electrode. It includes a second inductor laminated sheet portion formed, wherein the first and second laminated sheet is preferably laminated so that a portion of the one electrode overlaps with the common electrode, respectively. In this case, the first and second inductor patterns are preferably at least one of a straight line, a curved straight line and a meandering line.

Each of the first and second inductor laminated sheet portions may include a first inductor laminated sheet having a first linear inductor pattern extending from one cross section, a second through hole connected to the other end of the first linear inductor pattern; It is effective to include a second inductor laminated sheet on which a second linear inductor pattern extending from the second through hole is formed. Each of the first and second inductor laminated sheets may include a first inductor laminated sheet having a spiral inductor pattern and a second inductor laminated sheet having a crosslinking pattern formed thereon, and through holes connecting the inductor pattern and the crosslinking pattern. It is effective to include. Said one electrode is any one of a linear shape, the shape of which the edge part is refracted, and plate shape, The composite laminated chip element.

The plurality of stacked chip devices may be arranged in parallel and manufactured in an array in a single chip. It is preferable that a said 1st laminated sheet part is a varistor sheet.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

2 is a manufacturing process diagram of the stacked chip device according to the first embodiment of the present invention, Figure 3 is an equivalent circuit diagram of the stacked chip device according to the first embodiment of the present invention.

2 and 3, the stacked chip device according to the first exemplary embodiment of the present invention may include a first laminated sheet 10 having a plurality of first electrodes 11 formed therein and a second having a common electrode 21 formed thereon. A fourth laminated layer 20, a third laminated sheet 30 having a plurality of second electrodes 31 formed therein, a laminated sheet portion 40 having a plurality of inductor patterns 50 formed thereon, and a fourth protecting the lower pattern The laminated sheet 60 is included. In this case, the first external terminal electrode 81 connected to the first electrode 11, the second external terminal electrode 82 connected to the common electrode 21, and the third third terminal connected to the second electrode 31 may be used. An external terminal electrode 83 is further included. Here, the inductor pattern 50 is preferably connected in parallel between the first and third external terminal electrodes 81 and 83.

It is preferable that the first to fourth laminated sheets 10, 20, 30, and 60 and the laminated sheet portion 40 use an insulating material sheet having the same size. Moreover, the 1st-3rd laminated sheets 10, 20, 30, the laminated sheet part 40, and the 4th laminated sheet 60 are laminated | stacked sequentially. In the present embodiment, four first and second electrodes 11 and 31 are formed on the first and third laminated sheets 10 and 30, respectively. Accordingly, the inductor pattern 50 is also formed in the same number, and the figure shows a shape in which four single chips including them are arrayed. The composite stacked chip device of the present invention is not limited thereto and includes at least one varistor capacitor and an inductor.

The first electrode 11 extends a predetermined length from one end face of the first laminated sheet 10, and the second electrode 31 extends a predetermined length from the other end face of the third laminate sheet 30. Thus, when the sheets are stacked, the first and second electrodes 11 and 31 may be exposed on one side and the other side of the stacked sheets, respectively.

It is preferable that the first and second electrodes 11 and 31 are formed in a straight shape in which the ends are refracted outward. This eliminates the risk of shorting with common terminals. In addition, it is effective that two electrodes are formed on both sides with respect to the center of the laminated sheet, and the refractive patterns of both electrodes are symmetrical. In order to eliminate the frequency characteristic difference between the first and second electrodes 11 and 31, the second and third first and second electrodes 11 and 31 located in the center are preferably adjacent to each other. That is, the distance between the second and third first and second electrodes 11 and 31 is the distance between the first and second first and second electrodes 11 and 31 and the third and fourth first and second electrodes 11. , 31). In the above, the second and the third means two positioned at the center of the sheet, and the first and the fourth means located at the outside of the second and third, respectively. The same applies to the following.

Of course, the present invention is not limited thereto, and in a multi-layer chip device in which a plurality of unit devices are arranged in parallel and manufactured as a single chip, intervals between electrodes may be the same or different from each other to reduce a difference in frequency characteristics of the unit devices. There is a number. For example, the first and second and third and fourth first and second electrodes 11 and 31 may be adjacent to each other.

As described above, the distance between the electrodes can be adjusted to reduce the frequency characteristic difference of the arrayed chips, and the ends of the electrodes are refracted to make the interval between the electrodes exposed to the outside of the stack constant so that the distance between the external electrodes is constant. I can keep it.

The common electrode 21 is formed in a plate shape on the second laminated sheet 20, but is preferably formed in a direction crossing the plurality of first and second electrodes 11 and 31. In other words, when the ends extending in the longitudinal direction of the first and second electrodes 11 and 31 are refracted linearly, the common electrode 21 is formed in a plate shape having a long length in the lateral direction. In addition, when a plurality of sheets are stacked by exposing a part of the common electrode 21 to both end surfaces of the second laminated sheet 20, the first and second electrodes 11 and 31 may be different from each other. The common electrode 21 is exposed through both sides. A portion of the common electrode 21 and the first and second electrodes 11 and 31 overlap with each other. In this case, it is preferable that the linear regions of the first and second electrodes 11 and 31 overlap the common electrode 21.

In the multilayer sheet part 40 having the inductor pattern 50 described above, the first inductor laminated sheet 41 having the first inductor pattern 51, the second inductor pattern 52 are formed, and the second inductor pattern The second inductor laminated sheet 42 having the first through hole 53 for connection between the 52 and the first inductor pattern 51 and the third inductor pattern 54 are formed, and the third inductor pattern ( And a third inductor laminated sheet 43 having a second through hole 55 for connection between the second inductor pattern 54 and the second inductor pattern 52.

The first inductor pattern 51 may be formed in a 'c' shape extending from one end surface of the first inductor laminate sheet 41. That is, as shown in FIG. 2A, the first inductor pattern 51 may include a first line extending from one end surface of the first inductor laminate sheet 41, a second line refracting and extending from the end of the first line. And a third line connected to the second line and extending in parallel with the first line. The second inductor pattern 52 may be formed in a 'c' shape in which the first through hole 53 and a part thereof overlap, and are connected through the first inductor pattern 51 and the first through hole 53. Do. That is, as shown in FIG. 2A, the first through hole 53 is formed to overlap the end of the third line of the first inductor pattern 51. The second inductor pattern 52 includes a first line extending from the first through hole 53, a second line refracting at the end of the first line, and a third line refracting at the end of the second line. The third inductor pattern 54 extends from the other end surface of the third inductor laminate sheet 43 to form a '-' shape in which the second through hole 55 and a portion thereof overlap, thereby forming the second inductor pattern 52. It is preferable to be connected through the 2nd through-hole 55. That is, as illustrated in FIG. 2A, the second through hole 55 is formed to overlap the end of the third line of the second inductor pattern 52. The third inductor pattern 54 may include a first line extending from the second through hole 55, a second line refracted at the end of the first line, and the second line to the other end surface of the third inductor laminate sheet 43. An elongated third line. In the drawings, the angle lines are shown to form a 90 degree refraction, the angle of refraction at the time of refraction is possible 0 to 360 degrees, preferably 30 to 150 degrees is effective. As described above, the first to third inductor patterns are connected to each other to form one winding type inductor pattern, and the inductor pattern may have the same effect as one line rotated by 720 degrees. Of course, the present invention is not limited thereto, and the shape of the inductor pattern may vary in number to obtain a target inductor value.

The first to third external terminal electrodes 81, 82, and 83 are formed by stacking the first to third laminated sheets 10, 20, and 30, the laminated sheet portion 40, and the fourth laminated sheet 60. It is formed in a shape surrounding the side region. That is, the first external terminal electrode 81 is formed in a shape surrounding the surface where the first electrode 11 and the third inductor pattern 54 are exposed, and the second external terminal electrode 82 is the common electrode 21. ) Is formed to surround the exposed surface, and the third external terminal electrode 83 is formed to surround the exposed surface of the second electrode 31 and the first inductor pattern 51. Thus, as shown in FIG. 3, the inductor pattern 50 is connected between the first external terminal electrode 81 and the third external terminal electrode 83, and the first external terminal electrode 81 and the second external terminal are connected to each other. An equivalent capacitor formed by the first electrode 11 and the common electrode 21 is formed between the electrodes 82, and the common electrode 21 is between the second external terminal electrode 82 and the third external terminal electrode 83. And an equivalent capacitor formed by the second electrode 31. Therefore, an equivalent pie type ESD filter can be manufactured using the first and third external terminal electrodes 81 and 83 as the input terminal or the output terminal and the second external terminal electrode 82 as the ground.

 Hereinafter, the manufacturing method of the composite multilayer chip device of the present embodiment having the above-described structure will be described.

As shown in FIG. 2A, the first laminated sheet 10 on which the first electrode 11 is formed, the second laminated sheet 20 on which the common electrode 21 is formed, and the second electrode 31 formed on the second laminated sheet 10 are formed. A third laminated sheet 30, a laminated sheet portion 40 having an inductor pattern 50 formed thereon, and a fourth laminated sheet 60, which is a dummy sheet to protect the lower element, are provided. Preferably, the above-described laminated sheet is formed in a rectangular shape, but is not limited thereto according to the use and use of the final composite laminated chip device, and may include a square, a polygonal shape including a pentagon, a circular shape, an elliptical shape, and the like. . In addition, the exemplary embodiment illustrates one chip including four pairs of unit devices, but is not limited thereto.

To this end, a molded laminated sheet for a desired device is produced. That is, the molded laminated sheet for varistors and the molded laminated sheet for inductors are manufactured. To do this, use a raw material powder of a commercial varistor element or ball mill with water or alcohol for 24 hours in a desired composition in which additives such as Bi ₂ O ₃ , CoO, MnO, etc. are added to ZnO powder. Prepare the powder. In order to prepare a molded laminated sheet, PVB-based binders were measured as an additive to the prepared varistor powder by about 6wt% of the raw material powder, and then dissolved in toluene / alcohol-based solvents. After the milling and mixing for about 24 hours in a small ball mill (slurry) to prepare a slurry (slurry), such a slurry by a method such as a doctor blade (Doctor blade) molded laminate sheet of the desired thickness (Fig. 2) (a) 10, 20, 30). At this time, the raw material powder of the composition for the capacitor element, the raw material powder of the composition for the PTC (positive temperature coefficient) thermistor element, or the raw material powder of the composition for the negative temperature coefficient (NTC) thermistor element is also manufactured into a molded laminated sheet having a desired thickness in the same manner. can do.

Or you may use the shaping | molding sheet for general insulators. In addition, a ferrite pattern may be printed on the dummy sheet and used as a molded laminated sheet for an inductor. Alternatively, an inductor sheet such as a separate ferrite sheet may be manufactured separately.

A conductive pattern is formed by printing a conductive paste such as Ag, Pt, or Pd by screen printing using a screen of a specially designed internal electrode pattern on the sheet manufactured as described above.

The first electrode 11 is formed to be refractively extended to a predetermined region in the other cross-sectional direction from one cross section of the upper surface of the first laminated sheet 10, and one cross section from the other cross section of the upper surface of the third laminated sheet 30. Direction is formed to extend the second electrode 31 to a predetermined region. It is preferable to form the 1st and 2nd electrodes 11 and 31 by printing a conductive paste using a silk screen. The plate-shaped common electrode 21 is formed on the upper surface of the second laminated sheet 20.

In addition, a first inductor pattern 51 having a predetermined shape is formed on an upper surface of the first inductor laminated sheet 41. A portion of the second inductor laminated sheet 42 is removed using a punching device to form a first through hole 53, and a second inductor pattern 52 having a predetermined shape extending from the first through hole 53. ). A portion of the third inductor laminated sheet 43 is removed to form a second through hole 55, and a third inductor pattern 54 having a predetermined shape extending from the second through hole 55 is formed. In this case, the through holes 53 and 55 and the inductor patterns 52 and 54 may form the through holes 53 and 55 after the inductor patterns 52 and 54 are formed, and vice versa. In addition, the through holes 53 and 55 may be filled with a conductive material at the same time when the inductor patterns 52 and 54 are formed. In addition, a separate filling process may be performed to fill the first and second through holes 53 and 55 with a conductive material. Of course, the present invention is not limited thereto, and a predetermined region of the through hole may be coated with a conductive material to electrically connect the inductor patterns of the respective inductor stack sheets. The inductor pattern may be manufactured using a metal paste such as Ag, Pt, Pd, Ni-Cr, or RuO ₂ .

As shown in FIG. 2B, the first laminated sheet 10 on which the first electrode 11 is formed, the second laminated sheet 20 on which the common electrode 21 is formed, and the second electrode 31 are formed on the first laminated sheet 10. The third laminated sheet 30, the first inductor laminated sheet 41 on which the first inductor pattern 51 is formed, the second inductor laminated sheet 42 on which the second inductor pattern 52 is formed, and the third inductor pattern A third inductor laminated sheet 43 with 54 is formed, and a fourth laminated sheet 60 for protecting them is laminated. Through the stacking, a part of the first electrode 11 and the common electrode 21 overlap each other, and a part of the common electrode 21 and the second electrode 31 overlap each other. In addition, the first to third inductor patterns 51, 52, and 54 are connected to each other by a conductor filled in the through holes 53 and 55.

The laminate stacked as described above is pressed and then cut into an appropriate size. For example, when the unit elements are individually cut, the unit elements are cut into a single chip, and when a plurality of elements are periodically cut, the plurality of elements are cut into a single chip. That is, as shown in FIG. 2A, when the four unit elements are cut to be arranged, the four unit elements may be cut into an array type single chip arranged in parallel.

In fact, a pattern formed on one device is repeatedly formed on a sheet so as to appear in plural numbers, and these sheets are stacked, and then cut into the desired size of the device, for example, as shown in FIG. Cutting together may be suitable for mass production.

In order to remove all organic components such as binders in the cut laminate as described above, it is heated at about 300 ° C. and baked out, and then the temperature is raised to a suitable firing temperature (for example, about 1100 ° C.). The laminate is fired.

Outside of the stack, each electrode pattern inside the stack and external terminal electrodes 81, 82, and 83 connected to the inductor pattern are formed to complete the stacked chip device. The external terminals are made of silver paste (Ag) on rubber discs grooved on the circumferential surface according to the number of electrodes to be formed (the number of external terminals printed on the side of the body, for example, 4 or 1) and the position thereof. After the paste is applied, the disc is placed in close contact with the body (dipping action), the electrode is printed and then fired at an appropriate temperature.

In addition, as described above, the common electrode is disposed between the first electrode and the second electrode, which are terminal electrodes, and the distance between the plurality of first and second electrodes is adjusted to eliminate the difference in frequency characteristics between the terminals of the arrayed chips. Can be.

In addition, the present invention can reduce the frequency characteristic difference between the terminals by different position and arrangement between the common electrode and the terminal electrode, it is possible to provide an inductor-varistor composite laminated chip device. This second embodiment of the present invention will be described with reference to the drawings. In the following embodiment, a description overlapping with the first embodiment described above will be omitted.

<Example 2>

4 is a manufacturing process diagram of a multilayer chip device according to a second exemplary embodiment of the present invention.

Referring to FIG. 4, a first laminated sheet 110 having a first common electrode 111 formed thereon, a second laminated sheet 120 having a plurality of pairs of first and second electrodes 121 and 122 formed therein, and a second The third stacked sheet 130 having the common electrode 131 formed thereon, the stacked sheet portion 140 having the plurality of inductor patterns 150 formed thereon, and the fourth stacked sheet 160 protecting the lower pattern. In this case, the first external terminal electrode 181 connected to the first electrode 121, the second external terminal electrode 182 connected to the first and second common electrodes 111 and 131, and the second electrode ( And a third external terminal electrode 183 connected with 122. The inductor pattern 150 is connected to the first and third external terminal electrodes 181 and 183. In this embodiment, either one of the first or third laminated sheets 110 and 130 may be omitted. In addition, the fourth laminated sheet 160 may also be omitted, which may be replaced by a separate protective layer such as glass or a resin film.

In the present embodiment, as shown in the drawing, four pairs of the first and second electrodes 121 and 122 are formed on the second laminated sheet 120.

The first electrode 121 extends a predetermined length in one cross section of the second laminated sheet 120, and the second electrode 122 extends a predetermined length in another cross section of the second laminated sheet 120. That is, the first and second electrodes 121 and 122 to be used as the signal lines are straight lines in which respective ends positioned at both end surfaces of the second laminated sheet 120 are refracted, and at each other except the ends. It is printed side by side on the same side. Due to the pair of the first and second electrodes 121 and 122 of the second laminated sheet 120, the pattern is not complicated in the lamination process, and mutual interference between terminals may be reduced in terms of frequency characteristics. The distance between the second and third pairs of first and second electrodes 121 and 122 is the distance between the first and second pairs of first and second electrodes 121 and 122, and the third and fourth first and second electrodes ( 121, 122) can be formed narrower than the distance between the pair.

The first and second common electrodes 111 and 131 may be formed in a plate shape on the first and third laminated sheets 110 and 130, and may cross the pair of first and second electrodes 121 and 122. It is preferable to form.

In addition, since the inductor pattern 150 is the same as described in the first embodiment, a detailed description thereof will be omitted.

The manufacturing method of the composite multilayer chip device of the present embodiment as described above is as follows.

Each laminated sheet was manufactured in the same manner as in Example 1, and as shown in FIG. 4A, the first laminated sheet 110 on which the first common electrode 111 was formed, and the first and second electrodes ( 121, 122, a second laminated sheet 120 having a pair, a third laminated sheet 130 having a second common electrode 131, a laminated sheet portion 140 having an inductor pattern 150, and a fourth The laminated sheet 160 is prepared.

The first and second common electrodes 111 and 131 are formed on the first and third laminated sheets 110 and 130 through screen printing techniques, and the first and second electrodes 121 and 122 are also screen printing techniques. It forms on the second laminated sheet 120 through. In this embodiment, the common electrode is formed on two laminated sheets, each separated, and the first and second electrodes are formed on one laminated sheet.

As shown in FIG. 4B, the first laminated sheet 110, the second laminated sheet 120, the third laminated sheet 130, the laminated sheet portion 140, and the fourth laminated sheet 160 described above. ) Are stacked sequentially. As a result, the pair of first and second electrodes 121 and 122 and a part of the first and second common electrodes 111 and 131 overlap with each other. The laminate is then cut to the desired size, pressed and fired.

As shown in FIG. 4C, the first external electrode terminal 181 connecting the first electrode 121 and the third inductor pattern 154, and the first and second common electrodes 111 and 131. A second external electrode terminal 182 connecting the terminals and a third external electrode terminal 183 connecting the second electrode 122 and the first inductor pattern 151 are formed. Thereby, the piezoelectric ESD filter which the inductor is connected in series between the input / output terminals, and each capacitor connected between the input / output terminal and the ground can be manufactured.

As described above, in the present exemplary embodiment, an inductor-varistor composite multilayer chip device may be provided in which a pattern of an internal electrode is formed on one laminate sheet, so that the pattern is not complicated and the interference between terminals can be reduced.

In addition, the present invention can provide an inductor-varistor composite multilayer chip device capable of adjusting a capacitor value by increasing an area between the common electrode and the terminal electrode. Such a third embodiment of the present invention will be described with reference to the drawings. In the following embodiment, a description overlapping with the above-described first and second embodiments will be omitted. In addition, the present embodiment can be applied to the first and second embodiments described above.

<Example 3>

5 is a manufacturing process chart of the stacked chip device according to the third embodiment of the present invention.

Referring to FIG. 5, a first laminated sheet 1100 having a first common electrode 1110, a second laminated sheet 1200 having a plurality of first and second electrodes 1210 and 1220 formed therein, and a second The third stacked sheet 1300 having the common electrode 1310 formed therein, the fourth stacked sheet 1350 having the plurality of first and second electrodes 1351 and 1352 formed thereon, and the plurality of inductor patterns 1500 formed therein. The sheet part 1400 and a fifth laminated sheet 1600 for protecting the lower pattern are included. In this case, the first external terminal electrode 1810 connected to the first electrodes 1210 and 1351, the second external terminal electrode 1820 connected to the first and second common electrodes 1110 and 1310, and the second And a third external terminal electrode 1830 connected to the electrodes 1220 and 1352. The inductor pattern 1500 is connected to the first and third external terminal electrodes 1810 and 1830. In this embodiment, either one of the first or third laminated sheets 1100 and 1300 may be omitted, and either one of the second or fourth laminated sheets 1200 and 1350 may be omitted.

In the present embodiment, as shown in the drawings, four pairs of the first and second electrodes 1210, 1220, 1351, and 1352 are formed on the second and fourth laminated sheets 1200 and 1350, respectively.

The first electrodes 1210 and 1351 are formed in a plate shape extending from one end surface of the second and fourth laminated sheets 1200 and 1350, and the second electrodes 1220 and 1352 are formed of the second and fourth laminated sheets. It is formed in the shape of a plate extending from the other cross-section (1200, 1350). In this case, the first electrodes 1210 and 1351 and the second electrodes 1220 and 1352 may be formed to correspond to each other. As such, the pair of the first and second electrodes 1210, 1220, 1351, and 1352 of the second and fourth laminate sheets 1200 and 1350 do not complicate the pattern in the lamination process, and the frequency characteristics between the terminals Mutual interference can be reduced. In addition, the distance between the pair of second and third first and second electrodes 1210, 1220, 1351, and 1352 is the distance between the pair of first and second first and second electrodes 1210, 1220, 1351, 1352, and the third. And the fourth pair of first and second electrodes 1210, 1220, 1351, and 1352 may be narrower than a distance between the pairs.

The first and second common electrodes 1110 and 1310 connect both ends of the first and second electrodes 1210, 1220, 1351, and 1352 that are not in contact with the first and third laminated sheets 1100 and 1300. It is preferably formed in the shape of a plate, but a portion of the region corresponding to the first and second electrodes 1210, 1220, 1351, 1352 is preferably formed to protrude.

Since the inductor pattern 1500 is the same as that described in the first embodiment, detailed description thereof will be omitted.

The manufacturing method of the composite multilayer chip device of the present embodiment as described above is as follows.

Each laminated sheet was manufactured in the same manner as in Example 1, and as shown in FIG. 5A, the first laminated sheet 1100 having the first common electrode 1110 and the first and second electrodes ( 1210, 1220, a second laminated sheet 1200 having a pair formed therein, a third laminated sheet 1300 having a second common electrode 1310 formed therein, and a fourth laminated sheet formed with a pair of first and second electrodes 1351, 1352 formed therein. 1350, the laminated sheet part 1400 on which the inductor pattern 1500 is formed, and the fifth laminated sheet 1600 are provided.

As shown in FIG. 5B, the first laminated sheet 1100, the second laminated sheet 1200, the third laminated sheet 1300, the fourth laminated sheet 1350, and the laminated sheet portion 1400 are described above. ) And the fifth laminated sheet 1600 are sequentially stacked. As a result, the pair of first and second electrodes 1210, 1220, 1351, and 1352 and a portion of the first and second common electrodes 1110 and 1310 overlap. The laminate is then cut to the desired size, pressed and fired.

As illustrated in FIG. 5C, the first external electrode terminal 1810 connecting the first electrodes 121 and 1351 and the third inductor pattern 1540, the first and second common electrodes 1110, and the like. 1310, a second external electrode terminal 1820 connecting the terminals, and a third external electrode terminal 1830 connecting the second electrodes 1220 and 1352 and the first inductor pattern 1510 are formed. Thereby, the piezoelectric ESD filter which the inductor is connected in series between the input / output terminals, and each capacitor connected between the input / output terminal and the ground can be manufactured.

As described above, in the present embodiment, an inductor-varistor capable of forming a pattern of internal electrodes on one laminated sheet does not complicate the pattern, reduces interference between terminals, and increases a capacitor value through a plate-shaped electrode. A composite laminated chip device can be provided.

In addition, the present invention is not limited thereto, and an aspect of the inductor pattern may be variously changed. Hereinafter, a fourth embodiment of the present invention in which the inductor pattern is formed in a meander shape will be described with reference to the drawings. In the following embodiment, the internal terminal electrode patterns of the first embodiment will be described as a basis, but are not limited thereto. The internal terminal electrode patterns of the second and third embodiments may be applied. In addition, description overlapping with 1st thru | or 3rd embodiment is abbreviate | omitted. In addition, the present embodiment may be applied to the first to third embodiments described above.

<Example 4>

6 is a manufacturing process chart of the stacked chip device according to the fourth embodiment of the present invention.

Referring to FIG. 6, the stacked chip device according to the fourth embodiment of the present invention may include a first stacked sheet 210 and a common electrode 221 on which a plurality of first electrodes 211a, 211b, 211c, 211d; 211 are formed. ) Is formed a second laminated sheet 220, a third laminated sheet 230 formed with a plurality of second electrodes (231a, 231b, 231c, 231d; 231), and the first and second electrodes (211, 231). ) And a multilayer sheet part 240 having a plurality of inductor patterns 250 formed thereon, and a fourth laminated sheet 260 for protecting the lower pattern. A first external terminal electrode 281 to which the first electrode 211 and the inductor pattern 250 are connected, a second external terminal electrode 282 connected to the common electrode 221, and a second electrode 231. The semiconductor device further includes a third external terminal electrode 283 to which the inductor pattern 250 is connected.

In the present embodiment, four first and second electrodes 211 and 231 are formed on the first and third laminated sheets 210 and 230, respectively. Accordingly, the inductor pattern 250 is also formed in the same number, and the figure shows a shape in which four single chips including them are arrayed. The composite multilayer chip device of the present invention is not limited thereto, and includes at least one varistor capacitor and an inductor.

The laminated sheet part 240 on which the inductor pattern 250 is formed includes first to fourth inductor laminated sheets 241, 242, 243, and 244. The first inductor laminate sheet 241 is formed in a meandering shape, and a first inductor pattern 251 corresponding to the first and second electrodes 211a and 231a is formed. A second inductor pattern 252 is formed on the second inductor stack sheet 242 in a meandering shape and corresponding to the second first and second electrodes 211b and 231b. A third inductor pattern 253 is formed on the third inductor laminated sheet 243 in a meandering shape and corresponding to the third first and second electrodes 211c and 231c. A fourth inductor pattern 254 is formed on the fourth inductor stack sheet 244 in a meandering shape and corresponding to the fourth first and second electrodes 211d and 231d. Here, the inductor pattern 250 is exposed on one end surface where the first electrode 211 is exposed and the other end surface where the second electrode 231 is exposed, and is a meandering shape based on a 'r' character between the exposed surfaces. Is formed.

As illustrated in FIG. 2B, the first external terminal electrode 281 is formed to surround the plurality of exposed first electrodes 211 and the inductor pattern 250. The second external terminal electrode 282 is formed in a shape surrounding the common electrode 221. The third external terminal electrode 283 is formed to surround the second electrode 231 and the inductor pattern 250, respectively.

The manufacturing method of the composite multilayer chip device according to the present embodiment as described above is as follows. Each laminated sheet was manufactured in the same manner as in Example 1, and the first laminated sheet 210 and the common electrode 221 having the plurality of first electrodes 211 formed thereon as shown in FIG. The formed second laminated sheet 220 and the second laminated sheet 230 having a plurality of second electrodes 231 are provided. Meanwhile, the first and second electrodes 211 and 231 are formed to overlap each other with respect to the common electrode 221 in four phases, respectively. First to fourth inductor laminated sheets 241, 242, 243, and 244 corresponding to exposed surfaces of the first to fourth pairs of first and second electrodes 211 and 231, respectively, and having an inductor pattern 250 formed in a meandering shape. ). In addition, the fourth laminated sheet 260 is provided.

As shown in FIG. 6B, the aforementioned first to third laminated sheets 210, 220, and 230, first to fourth inductor laminated sheets 241, 242, 243, and 244, and fourth The lamination sheet 260 is laminated sequentially. The laminate is then cut to the desired size, pressed and fired. Metal pads 262 are formed on the fourth laminated sheet 260 to respectively correspond to the inductor pattern 250.

As shown in FIG. 6C, a first external terminal electrode 281 connecting the first electrode 211 and the inductor pattern 250 and a second external terminal electrode 280 surrounding the common electrode 221 are provided. ) And a third external terminal electrode 283 connecting the second electrode 231 and the inductor pattern 250 to each other.

As such, in the present exemplary embodiment, one first electrode 211, one common electrode 221, one second electrode 231, and the first inductor pattern 251 may operate as one unit element. In addition, various circuits in which an inductor and a capacitor are combined may be configured by adjusting a connection relationship between external terminal electrodes. Preferably, the second external terminal electrode 282 is connected to the ground, and the first and third external terminal electrodes 281 and 283 are connected to the input and output terminals, whereby a pie type filter can be manufactured, and the filter has an ESD function. Can be done. In this embodiment, it is possible to manufacture an array chip in which four pie type filters are formed, and the manufacturing process can be simplified because inductors corresponding to each chip are formed on one sheet.

In addition to the meandering type described above, a linear crossing type that crosses linearly on different inductor laminated sheets is possible. Hereinafter, a fifth embodiment of the present invention in which the inductor pattern is formed in a straight cross shape will be described with reference to the drawings. In the following embodiment, the internal terminal electrode patterns of the first embodiment will be described as a basis, but are not limited thereto. The internal terminal electrode patterns of the second and third embodiments may be applied. In addition, description overlapping with 1st-4th embodiment is abbreviate | omitted. In addition, the present embodiment can be applied to the first to fourth embodiments described above.

Example 5

7 is a manufacturing process chart of the stacked chip device according to the fifth embodiment of the present invention.

Referring to FIG. 7, the stacked chip device according to the present exemplary embodiment may include a first stacked sheet 310 having a plurality of first electrodes 311, a second stacked sheet 320 having a common electrode 321, and A third laminated sheet 330 having a plurality of second electrodes 331, a laminated sheet portion 340 having a plurality of linearly crossing inductor patterns 350 formed therein, and a fourth laminated sheet for protecting the lower pattern 360. At this time, the first external terminal electrode 381 connected to the first electrode 311, the second external terminal electrode 382 connected to the common electrode 321, and the third electrode connected to the second electrode 331 are provided. An external terminal electrode 383 is further included.

The laminated sheet part 340 having the inductor pattern 350 may include a first inductor laminated sheet 341 having a first inductor pattern 351, a second inductor pattern 352, and a second inductor pattern 352. ) And a second inductor stack sheet 342 having a first through hole 353 for connection between the first inductor pattern 351, a third inductor pattern 354, and a third inductor pattern 354. And a third inductor laminated sheet 343 having a second through hole 355 for connection between the second inductor pattern 352 and the second inductor pattern 352.

The first inductor pattern 351 may be formed in a straight line extending from the other end surface of the first inductor laminated sheet 341. The second inductor pattern 352 may be formed of a first through hole 353 overlapping the first inductor pattern 351 and a portion thereof, and a straight line extending from the first through hole 353. The third inductor pattern 354 overlaps the second inductor pattern 352 and a portion thereof and extends from the second through hole 355 and the second through hole 355 to one cross section of the third inductor laminated sheet 343. It is preferable to form in the straight line.

The first to third inductor laminated sheets 341, 342, and 343 are sequentially stacked, and the first to third inductor patterns 351 are filled by filling the inside of the first and second through holes 353 and 355 with a conductive material. An inductor pattern 340 is formed in which 352 and 354 are connected by one line.

The manufacturing method of the composite multilayer chip device of the present invention according to the present embodiment described above is as follows.

Each laminated sheet was manufactured in the same manner as in Example 1, and as shown in FIG. 7A, the first laminated sheet 310 on which the first electrode 311 was formed and the common electrode 321 were formed The 2nd laminated sheet 320 and the 3rd laminated sheet 330 in which the 2nd electrode 331 was formed are provided. The laminated sheet part 340 having the inductor pattern 350 is provided.

The first inductor pattern 351 having a linear shape extending from the other end surface is formed on the first inductor laminate sheet 341 of the laminate sheet 340. A portion of the second inductor stack sheet 342 is formed with a first through hole 353 corresponding to the end of the first inductor pattern 351, and a straight second inductor pattern extending from the first through hole 353. 352 is formed. A part of the third inductor laminated sheet 343 is formed with a second through hole 355 corresponding to the end of the second inductor pattern 352, and has a linear shape extending from the second through hole 355 to one end surface. The third inductor pattern 354 is formed. In this case, after the first and second through holes 353 and 355 are formed, the inside thereof may be filled with a conductive material.

The first to third laminated sheets 310, 320, and 330, the laminated sheet portion 340, and the fourth laminated sheet 360 are sequentially laminated, and then the laminated laminate is pressed and fired. In this case, the third inductor pattern 354 is exposed to the same cross section as the first electrode 311, and the first inductor pattern 351 is exposed to the same cross section as the second electrode 331. Thereafter, a first external terminal electrode 381 having a shape surrounding the exposed first electrode 311 and the third inductor pattern 354 is formed, and a second external terminal electrode 382 having a shape surrounding the common terminal 321. ) And a third external terminal electrode 383 formed to surround the exposed second electrode 331 and the first inductor pattern 351.

As a result, a composite multilayer chip having a structure in which an inductor-varistor is stacked can be manufactured, and a plurality of inductor stack sheets are stacked by using a straight line and through-holes, and adjacent chips are formed through a straight line inductor pattern forming one inductor. Interference can be minimized.

As an inductor pattern of the composite multilayer chip device of the present invention, a linear inductor as well as a spiral inductor pattern may be formed. Hereinafter, a sixth embodiment of the present invention in which the inductor pattern is spirally formed will be described with reference to the drawings. In the following embodiment, the internal terminal electrode patterns of the first embodiment will be described as a basis, but are not limited thereto. The internal terminal electrode patterns of the second and third embodiments may be applied. In addition, description overlapping with 1st thru | or 5th embodiment is abbreviate | omitted. In addition, the present embodiment can be applied to the first to fifth embodiments described above.

<Example 6>

8A and 8B are manufacturing process diagrams of the stacked chip device according to the sixth embodiment of the present invention.

8A and 8B, the stacked chip device according to the present exemplary embodiment may include a first stacked sheet 410 having a plurality of first electrodes 411 and a second stacked sheet 420 having a common electrode 421. ), A third stacked sheet 430 having a plurality of second electrodes 431, and a stacked sheet portion having a plurality of inductor patterns 450 corresponding to the first and second electrodes 411 and 431, respectively. 440 and a fourth laminated sheet 460 stacked on the laminated sheet portion 440. The first external terminal electrode 481 connected to the first electrode 411, the second external terminal electrode 482 connected to the common electrode 421, and the third external terminal electrode 431 connected to the second electrode 431. An external terminal electrode 483 is further included.

The laminated sheet portion 440 includes first to fourth inductor laminated sheets 441, 442, 443, and 444 as shown in FIG. 8A. On the first inductor laminated sheet 441, a spiral second and a part of which is exposed to the other end surface of the first inductor laminated sheet 441 so as to correspond to the second second electrode 431 and the fourth second electrode 431, respectively. Fourth inductor patterns 452a and 454a are formed. That is, the starting point of the helical second inductor pattern 452a is formed so as to gradually decrease in size, starting from the upper part of the exposed surface (the other end surface) of the second second electrode 431 and rotating inward. In this embodiment, it was rotated about 3 turns counterclockwise. This is not limited to this, and may be variously changed according to a target inductance value.

The second inductor laminated sheet 442 includes second and fourth through holes 452c and 454c respectively formed in regions overlapping the inner spirals of the spiral second and fourth inductor patterns 452a and 454a, and the second first. The second and fourth crosslinking patterns 452b and 454b are formed to partially correspond to the electrode 411 and the fourth first electrode 411, and part of the second inductor laminate sheet 442 is exposed to one end surface of the second inductor stack sheet 442. The second and fourth crosslinking patterns 452b and 454b are formed in a curved line shape, and regions exposed in one end surface are exposed on the same region as the second first electrode 411 and the fourth first electrode 411, respectively. It is desirable to. The inside of the through hole is filled with a conductive material to correspond to the first and second electrodes 411 and 431 through the spiral second inductor pattern 452a, the second through hole 452c, and the second crosslinking pattern 452b. An inductor pattern 450 is formed.

Spiral first and third inductor patterns 451a and 453a are formed on the third inductor laminated sheet 443. At this time. The first and third inductor patterns 451a and 453a of the spiral are partially cross-sections of the third inductor stack sheet 443 so as to correspond to the first second electrode 431 and the third second electrode 431, respectively. Exposed.

First and third through holes 451c and 453c respectively formed in regions overlapping the inner spirals of the spiral first and third inductor patterns 451a and 453a on the fourth inductor stack sheet 444, and the first first. First and third crosslinking patterns 451b and 453b are formed in which portions of the fourth inductor laminate sheet 444 are exposed at one end thereof so as to correspond to the electrode 411 and the third first electrode 411. It is preferable to form said 1st and 3rd bridge | crosslinking patterns 451b and 453b in linear form.

In addition, inductor patterns can be formed on different sheets to effectively adjust the inductance value. That is, as illustrated in FIG. 8B, the laminated sheet part 440 includes first to eighth inductor laminated sheets 441a, 441b, 442a, 442b, 443a, 443b, 444a, and 444b.

A spiral first inductor pattern 451a is formed on the first inductor laminated sheet 441a so that a portion thereof is exposed to the other end surface of the first inductor laminated sheet 441a so as to correspond to the fourth second electrode 431. A part of the second inductor stack sheet 442a is formed so as to correspond to the first through hole 451c and the fourth first electrode 411 formed in an area overlapping with the end of the inner spiral of the spiral first inductor pattern 451a. The first crosslinked pattern 451b exposed on one end surface of the second inductor laminated sheet 442a is formed.

A spiral second inductor pattern 452a is formed on the third inductor laminated sheet 441b so that a portion thereof is exposed to the other end surface of the third inductor laminated sheet 441b so as to correspond to the third second electrode 431. A part of the fourth inductor laminated sheet 442b is formed to correspond to the second through hole 452c and the third first electrode 411 formed in an area overlapping with the end of the inner spiral of the spiral second inductor pattern 452a. A second crosslinking pattern 452b is formed on one end surface of the fourth inductor stack sheet 442b.

A spiral third inductor pattern 453a is formed on the fifth inductor stack sheet 443a so that a portion thereof is exposed to the other end surface of the fifth inductor stack sheet 443a so as to correspond to the second second electrode 431. A part of the sixth inductor stack sheet 444a is formed so as to correspond to the third through hole 453c and the second first electrode 411 formed in an area overlapping with the end of the inner spiral of the spiral third inductor pattern 453a. A third crosslinking pattern 453b exposed on one end surface of the sixth inductor stack sheet 444a is formed.

A spiral fourth inductor pattern 454a is formed on the seventh inductor stack sheet 443b so that a portion thereof is exposed to the other end surface of the seventh inductor stack sheet 443b so as to correspond to the first second electrode 431. A part of the eighth inductor stack 444b may correspond to the fourth through hole 454c and the first first electrode 411 formed in an area overlapping with the end of the inner spiral of the spiral fourth inductor pattern 454a. A fourth crosslinking pattern 454b is formed on one end surface of the eighth inductor stack sheet 444b.

Looking at the manufacturing method of the multilayer chip device of the present invention having the above-described structure with reference to Figure 8a as follows.

Each laminated sheet was manufactured in the same manner as in Example 1, and the first laminated sheet 410 on which the first electrode 411 was formed and the common electrode 421 were formed, as shown in FIG. 8A (a). A second laminated sheet 420, a third laminated sheet 430 on which the third electrode 431 is formed, a laminated sheet portion 440 on which the inductor pattern 450 is formed, and a fourth laminated sheet portion 460 is provided. do.

Spiral second and fourth inductor patterns 452a and 454a are formed on the first inductor laminated sheet 441 of the laminated sheet part 440. Two second and fourth through holes 452c and 454c are formed in the second inductor stack sheet 442, and second and fourth crosslinked patterns extending from the through holes 452c and 454c to one cross-section, respectively. 452b, 454b). Spiral first and third inductor patterns 451a and 453a are formed on the third inductor laminated sheet 443. Two first and third through holes 451c and 453c are formed in the fourth inductor laminated sheet 444, and the first and third crosslinked patterns extending from the through holes 451c and 453c to one cross section, respectively. 451b, 453b).

Next, the first to third laminated sheets 410, 420, and 430, the laminated sheet portion 440, and the fourth laminated sheet portion 460 are sequentially stacked. As a result, the first electrode 411 is exposed to one end surface of the stack, and the first to fourth crosslinking patterns 451b, 452b, 453b and 454b, which are part of the inductor pattern 450, are exposed, and the second electrode to the other end surface. 431 is exposed, and the spiral first to fourth inductor patterns 451a, 452a, 453a, and 454a, which are part of the inductor pattern 450, are exposed. The common electrode 421 is exposed to the other two end surfaces of the stack. The laminate is pressed and cut to the desired size, which is then heated to remove various organic components and fire.

Thereafter, an external terminal electrode is formed. A first external terminal electrode 481 is formed to surround the first electrode 411 and the inductor pattern 450. A second external terminal electrode 482 is formed to surround the common electrode 421. A third external terminal electrode 483 is formed to surround the second electrode 431 and the inductor pattern 450.

As described above, in this embodiment, the inductor pattern may be spirally formed to obtain the maximum inductance value, and the inductor pattern for two chips may be formed in one sheet to realize four channels using two sheets.

Moreover, this invention can also manufacture the T-type filter using LC. Hereinafter, a seventh embodiment of the present invention will be described with reference to the drawings. In the following embodiment, a description will be given based on an electrode pattern in which any one of the first and second electrodes according to the first to third embodiments is deleted. The description overlapping with the first to sixth embodiments is omitted. In addition, the present embodiment can be applied to the first to sixth embodiments described above.

<Example 7>

9A and 9B are manufacturing process diagrams of a stacked chip device according to a seventh exemplary embodiment of the present invention.

10 is an equivalent circuit diagram of a multilayer chip device according to a seventh embodiment of the present invention.

9A, 9B, and 10, the multilayer chip device according to the present exemplary embodiment may include a first inductor sheet 941 having other inductor patterns 951, 952, 953, 954, 951a, and 952a extending from other cross sections. , 942, second inductor sheets 943 and 944 having one inductor patterns 955, 956, 957, 958, 953a and 954a extending in one cross section, and other inductor patterns 951, 952, 953 and 954. And a first laminated sheet 610 having first connection through holes 912 connected to the first and second ends 951a and 952a and a common electrode 911 exposed on both sides thereof, and one inductor pattern 955, 956, 957, 958, 953a. , 954a and a second laminated sheet 920 having a first electrode 921 connected to the first connection hole 912, and a third laminated sheet 960 which is a dummy sheet for protecting the internal electrode and the pattern. 960a). Here, one inductor pattern (955, 956, 957, 958, 953a, 954a) is connected to the first external terminal electrode 981, and the other inductor patterns (951, 952, 953, 954, 951a, 952a) are the third The external terminal electrode 983 is connected, and the common electrode 911 is connected to the second external terminal electrode 982. Here, the fourth laminated sheet 960b which is a dummy sheet may be further included below the laminate.

The first and second inductor sheets 941, 942, 943, 944 may each consist of two sheets, and may comprise more or fewer sheets, on each sheet. One inductor pattern may be formed, or one sheet may be formed by connecting different sheets with through holes. In addition, the shapes of the common electrode and the first electrode may also vary. That is, as shown in FIG. 9A, a first inductor pattern 951 extending in a straight line shape from the other end surface thereof to the center is formed on the first inductor laminated sheet 941. A predetermined through hole 952a filled with a conductive material may be formed in the first inductor laminate sheet 941 at the end of the first inductor pattern 951. Of course, a predetermined pad may be formed instead of the through hole. The pad is formed to facilitate the connection between the lower first inductor pattern 951 and the upper second inductor pattern 953. On the second inductor stack sheet 942, a first through hole 952b corresponding to the predetermined through hole 952a (physical and electrical connection) and filled with a conductive material is formed, and the first through hole 952 is formed. The second inductor pattern 953 extending in the other cross-sectional direction from to is formed, and the second through hole 954 is formed at the end of the second inductor pattern 953. Of course, a predetermined conductive pad may be formed instead of the second through hole 954.

A comb-shaped common electrode 911 is formed on the first laminated sheet 910, and a second through hole 954 and a first connection through hole 912 corresponding to the common electrode 911 are formed. . Here, the shape of the common electrode 911 is not limited, and any shape capable of adjusting the capacitance value by adjusting the connection area with the first electrode 921 is possible. The second connection through hole 922 overlapping with the first electrode 921 and a part of the first electrode 921 that is not exposed to the outside on the second laminated sheet 920 and corresponding to the first connection through hole 912. Is formed. At this time, it is preferable that a part of the first electrode 921 protrudes in the other cross-sectional direction, and a second connection through hole 922 corresponding to the first connection through hole 912 is formed by overlapping a part of the protruding region. Do.

A third through hole 955 corresponding to one end of the first electrode 921 is formed on the third inductor stack sheet 943, and the fourth inductor extends from the third through hole 955 in the other cross-sectional direction. Pattern 956 is formed. On the fourth inductor stack sheet 944, a fourth through hole for connecting the fifth inductor pattern 957 extending from one end surface to the other end direction and between the fourth inductor pattern 956 and the fifth inductor pattern 957. A ball 958 is formed.

As a result, the first inductor pattern 951 and the second inductor pattern 953 are connected through the first through hole 952b, and the other ends of the second inductor pattern 953 and the first electrode 921 are connected to the first end. And second connection through holes 912 and 922. In addition, one end of the first electrode 921 and the third inductor pattern 956 are connected through the third through hole 955, and the third inductor pattern 956 and the fourth inductor pattern 957 are connected to the fourth. It is connected through the through hole 958.

9B, a U-shaped first inductor pattern 951a extending from the other end surface is formed on the first inductor laminated sheet 941, and a first inductor pattern is formed on the second inductor laminated sheet 942. The first through hole 952a corresponding to the other end surface of the 951a is formed.

The common electrode 911 is formed on the first laminated sheet 910, and is separated from the common electrode 911 to form a first connection through hole 912 corresponding to the first through hole 952a. A first electrode 921 is formed on the second laminated sheet 920, and a second connection through hole 922 for connecting between the first electrode 921 and the first connection through hole 912 is formed.

A second inductor pattern 954a having a U-shape extending from one cross section is formed on the third inductor stack sheet 943, and a second through hole for connecting between the second inductor pattern 954a and the first electrode 921. A ball 953a is formed.

Through this, the first inductor pattern 951a and the other end of the first electrode 921 are connected through the first through hole 952a and the first and second connection through holes 912 and 922. One end of the first electrode 921 and the second inductor pattern 954a are connected through the second through hole 953a.

As described above, one inductor pattern 955, 956, 957, 958, 953a, 954a is connected to the first external terminal electrode 981, and the other inductor patterns 951, 952, 953, 954, 951a, 952a are connected. A first electrode connected to the third external terminal electrode 983 and between one inductor pattern 955, 956, 957, 958, 953a, 954a and the other inductor pattern 951, 952, 953, 954, 951a, 952a 921 is connected, and a common electrode 911 connected to the second external terminal electrode 982 is disposed below the first electrode 921. Thus, when the first and third external terminal electrodes 981 and 983 are connected to an input / output terminal to which signals are input / output, and the second external terminal electrode 982 is connected to ground, a series connection is made between the input terminal and the output terminal. And an inductor pattern, and a capacitor connected between a node between the inductor pattern and the inductor pattern and ground.

As described above, the present invention can combine a plurality of passive elements in a single chip to improve frequency characteristics, protect internal circuits from external overvoltage and static electricity, and simplify the pattern of the stacked chip.

In addition, it is possible to reduce the difference in frequency characteristics between a plurality of chips by changing the interval and pattern shape between the internal electrode patterns.

In addition, various types of filters including inductors and capacitors may be provided.

Claims (22)

A first laminated sheet portion having a plurality of first and second electrodes successively arranged to be disposed respectively per unit element, a first laminated sheet portion having a common electrode formed to be connected across the unit elements, and a plurality of inductors successively formed to be respectively arranged per unit element A laminate in which a second laminated sheet portion having a pattern is laminated; And A plurality of first and third external terminal electrodes positioned on an outer surface of the stack and connected to the first and second electrodes, respectively, and a second external terminal electrode connected to a common electrode; The first external terminal electrode is connected to one terminal of the inductor pattern and the first electrode, the third external terminal electrode is connected to the other terminal of the inductor pattern and the second electrode, The composite multilayer chip device of claim 1, wherein the first and second electrode ends are linearly refracted to one side. A first laminated sheet portion having a plurality of first and second electrodes successively arranged to be disposed respectively per unit element, a first laminated sheet portion having a common electrode formed to be connected across the unit elements, and a plurality of inductors successively formed to be respectively arranged per unit element A laminate in which a second laminated sheet portion having a pattern is laminated; And A plurality of first and third external terminal electrodes positioned on an outer surface of the stack and connected to the first and second electrodes, respectively, and a second external terminal electrode connected to a common electrode; The first external terminal electrode is connected to one terminal of the inductor pattern and the first electrode, the third external terminal electrode is connected to the other terminal of the inductor pattern and the second electrode, And the first and second electrodes are straight or plate-shaped, and the first and second electrodes at the center of the first laminated sheet portion are disposed adjacent to the outside than the outside. A first laminated sheet portion having a plurality of first and second electrodes successively arranged to be disposed respectively per unit element, a first laminated sheet portion having a common electrode formed to be connected across the unit elements, and a plurality of inductors successively formed to be respectively arranged per unit element A laminate in which a second laminated sheet portion having a pattern is laminated; And A plurality of first and third external terminal electrodes positioned on an outer surface of the stack and connected to the first and second electrodes, respectively, and a second external terminal electrode connected to a common electrode; The first external terminal electrode is connected to one terminal of the inductor pattern and the first electrode, the third external terminal electrode is connected to the other terminal of the inductor pattern and the second electrode, The first and second electrodes are straight or plate-shaped The common electrode of claim 1, wherein a part of a region corresponding to the first and second electrodes protrudes. The laminate according to any one of claims 1 to 3, wherein A first laminated sheet on which each of the first electrodes is formed per unit element; A second laminated sheet on which the common electrode is formed to be connected across the unit elements; A third laminated sheet on which the second electrode is formed per unit element, respectively; And Each of the unit device includes an inductor laminated sheet portion formed with the inductor pattern, The first to third laminate sheets are stacked in such a way that a part of the first and second electrodes are respectively overlapped with the common electrode. The method according to claim 4, wherein the inductor laminated sheet portion, A first inductor laminated sheet having a first inductor pattern formed for each unit element; A second inductor laminated sheet having a second inductor pattern formed for each unit element, and a first through hole connecting the first and second inductor patterns for each unit element; And And a third inductor pattern formed on each of the unit elements, and a third inductor laminated sheet having a second through hole connecting the second and third inductor patterns for each unit element. The method according to claim 5, The inductor pattern is a straight, refracted straight or meander composite stacked chip device. The method according to claim 4, wherein the inductor laminated sheet portion, A first inductor laminated sheet having a spiral inductor pattern formed in each unit element; And And a second inductor laminated sheet having a crosslinking pattern for each unit element, and a through hole connecting the spiral inductor pattern and the crosslinking pattern for each unit element. The laminate according to any one of claims 1 to 3, wherein A first laminated sheet on which the common electrode is formed to be connected across the unit elements; A second laminated sheet formed such that the first and second electrodes are spaced apart from each other per unit element; And Each of the unit device includes an inductor laminated sheet portion formed with the inductor pattern, The first to third laminate sheets are stacked in such a way that a part of the first and second electrodes are respectively overlapped with the common electrode. The method according to claim 8, wherein the inductor laminated sheet portion, A first inductor laminated sheet having a first inductor pattern formed for each unit element; A second inductor laminated sheet having a second inductor pattern formed for each unit element, and having a first through hole connecting the first and second inductor patterns for each unit element; And And a third inductor laminated sheet having a third inductor pattern formed for each unit element, and having a second through hole connecting the second and third inductor patterns for each unit element. The method according to claim 9, And the inductor pattern is at least one of a straight line, a curved straight line, and a meandering line. The method according to claim 8, wherein the inductor laminated sheet portion, A first inductor laminated sheet having a spiral inductor pattern formed in each unit element; And And a second inductor laminated sheet having a cross-linking pattern formed in each unit element and having through holes connecting the inductor pattern and the cross-linking pattern. The method according to claim 8, Each of the first and second electrodes of each of the unit devices may be a straight line that extends refractively at both ends of the second laminated sheet and may be parallel to each other except for the ends thereof. The method according to claim 1 or 3, The composite multilayer chip device of which the first and second electrodes of the central portion of the first laminated sheet portion are disposed adjacent to the outer side. The method according to any one of claims 1 to 3, The first laminated sheet portion is a varistor sheet composite laminated chip device. A first stacked sheet portion in which a plurality of electrodes formed in succession to be disposed per unit element and a common electrode are formed so as to be connected across the unit elements, and a second stack in which a plurality of at least two inductor patterns per unit element are continuously arranged A laminate in which sheet portions are stacked; And A plurality of first and third external terminal electrodes and a second external terminal electrode disposed per unit element on an outer surface of the stack, The at least two inductor patterns are connected in series between the first and third external terminal electrodes, the one electrode is connected to a node between the inductor patterns connected in series, and the common electrode is connected to a second external terminal electrode. Stacked chip devices. The method of claim 15, wherein the laminate, A first inductor stacked sheet unit in which a first inductor pattern is formed in each unit element; A first laminated sheet having a first connection through hole connected to a part of the first inductor pattern per unit element and the common electrode to be connected across the unit elements; A second laminated sheet on which the one electrode is formed per unit element, and a second connection through hole connecting the one electrode and the first connection through hole is formed; And A second inductor pattern is formed in each unit element, and each of the unit elements includes a second inductor laminated sheet having a first through hole connecting the second inductor pattern and one electrode. The first and second laminated sheets are stacked in such a way that a part of the one electrode overlaps the common electrode, respectively. The method according to claim 16, And the first and second inductor patterns are at least one of a straight line, a curved straight line, and a meandering line. The method of claim 16, wherein each of the first and second inductor laminated sheet portion, A first inductor laminated sheet having a first linear inductor pattern extending from one cross section of each unit element; A second inductor laminated sheet having a second through hole connected to the other end of the first linear inductor pattern for each unit element, and a second linear inductor pattern extending from the second through hole for each unit element; Composite laminated chip device comprising. The method of claim 16, wherein each of the first and second inductor laminated sheet portion, A first inductor laminated sheet having a spiral inductor pattern formed in each unit element; And And a second inductor laminated sheet having a cross-linking pattern formed for each unit element, and through holes connecting the inductor pattern and the cross-linking pattern. The method according to claim 16, The one electrode is a straight line, the end portion is a composite chip element of the shape or plate shape refracted. The method according to claim 15, The composite stacked chip device of the one electrode in the center of the first laminated sheet portion is disposed adjacent to the outer side. The method according to any one of claims 15 to 20, The first laminated sheet portion is a varistor sheet composite laminated chip device.

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