KR100698257B1 - Integrated circuit manufacturing method - Google Patents

Abstract

The present invention relates to an integrated circuit manufacturing method. The present invention provides a method for manufacturing an integrated circuit having a plurality of logic elements, the method comprising: (a) forming redundant logic not connected to the plurality of logic elements; And (b) forming one or more via holes and one or more layers of deposition material on the redundant logic device if a logic device is formed in the redundant logic. Provide a method. According to the integrated circuit manufacturing method according to the present invention, even if a design change after fabricating the integrated circuit is required at the time of fabricating the integrated circuit, the modification cost due to the design change of the logic can be minimized.

Description

Method for manufacturing a integrated circuit

Figure 1 (a) is a schematic diagram showing the schematic design of the integrated circuit in the integrated circuit fabrication

Figure 1 (b) is a schematic diagram showing the design of the integrated circuit when there is a design change in the structure of Figure 1 (a)

2 is a cross-sectional view of a physical cell that may be constructed by one embodiment of an integrated circuit manufacturing method in accordance with the present invention.

3 shows a net-list for redundant logic elements;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit manufacturing method, and more particularly, to an integrated circuit manufacturing method that can reduce the cost of design modification for a logic element of an integrated circuit.

In the manufacture of conventional integrated circuits, a system is determined and a schematic design of a circuit that performs the relevant functions of the determined system. After verifying the designed circuit, place and routing operations are performed, and when verification of layout is completed, a process of creating a mask of an integrated circuit is performed. Go through

As described above, in order to revision a conductive deposition material such as metal in the presence of logics in an integrated circuit, the conductive deposition material may be modified without modifying a mask constituting a transistor in the integrated circuit. Phosphorus metal was modified.

As described above, when the conventional logic elements are difficult to modify, all layers in the integrated circuit must be corrected (full layer revision), which is expensive.

Therefore, in general, in the manufacture of integrated circuits, an additional logic device is additionally designed in the integrated circuit in preparation for changing a mask constituting a transistor in the integrated circuit later. And if there is an engine change order (ECO), the above-mentioned logic element prepared according to the order was used.

1 (a) and 1 (b) illustrate an example of reconfiguring an integrated circuit when there is an engine change order (ECO).

In the example of FIG. 1A, the logic element in the integrated circuit includes an AND gate X1 and an inverter S2 that is spare logic. In the example of FIG. 1 (a), the AND gate includes two inputs (.A (Net1), .B (Net2)) and one output (.Y (Net3)), and the inverter S2 is Input and output are defined at the time of fabrication of the integrated circuit, but are not connected to other logic elements.

In the integrated circuit including the logic device of FIG. 1 (a), when the inverter (inverter), which is the redundant logic device, is connected to the AND gate by an engine change order (ECO), the logic device of FIG. 1 (b) is connected. An integrated circuit may be included.

As shown in the examples of Figs. 1A and 1B, when the redundant logic element is configured, the redundant logic element closest to the logic element changed so as to minimize the logic changed when the integrated circuit is modified, and the Modify the connection.

Since no connection relationship is defined between the logical elements in the routing process, the input / output terminals of the existing logic elements are drawn to be connected to the input / output terminals of the extra logic elements.

The integrated circuit modified in FIG. 1 (b) uses the output of the AND gate X1 (.Y (Net3)) as the input of the inverter S2 (.Y (Net4)), and the output of the inverter before the logic modification of the integrated circuit. Logic to be the output of gate X1 (.Y (Net3)).

However, in the related art, since most physical cells of a logic device to be modified are configured only up to a first metal layer, when the spare logic is connected with other logic, a mask layer is increased. And, there is a problem in that the additional cost.

In other words, when routing to an extra logic element, it must be routed using various kinds of via holes and a plurality of higher deposition materials (metal in the above example) on the physical cell of the logic element. Even when extra logic devices are connected, a mask layer increases and a change cost increases.

The present invention is to solve the above problems, an object of the present invention relates to an integrated circuit manufacturing method that can minimize the modification cost when the integrated circuit is required to change the integrated circuit manufacturing.

In order to solve the above problems, the present invention provides a method of manufacturing an integrated circuit having a plurality of logic elements, the method comprising: (a) forming extra logic not connected to the plurality of logic elements; And (b) forming one or more via holes and one or more layers of deposition material on the redundant logic device if a logic device is formed in the redundant logic. Provide a method.

In the step (b), it is preferable to form a pin on the uppermost deposited material layer on the logic device.

In addition, the present invention provides a method of manufacturing an integrated circuit having a plurality of logic elements, comprising: (a) forming extra logic not connected to the plurality of logic elements; And (b) continuously forming one or more via holes and one or more layers of deposition material in the redundant logic at the same height as the top layer of the plurality of logic elements when forming the redundant logic. It provides a method for manufacturing an integrated circuit, characterized in that forming.

In the step (b), it is preferable to form a pin with the highest deposition material layer among the deposition material layers connected to the logic.

Preferably, the deposition material of step (b) is metal.

Hereinafter, the present invention for realizing the above object will be described with reference to the accompanying drawings, preferred embodiments. Prior to describing the present invention in detail, hereinafter, 'logic' refers to a logic device or a connection relationship including the logic device, or a space within an integrated circuit for installing additional logic devices in the integrated circuit. ).

2 illustrates a cross-sectional view of a physical cell that may be constructed by one embodiment of an integrated circuit manufacturing method in accordance with the present invention.

According to an embodiment of the integrated circuit manufacturing method according to the present invention, it is desirable to minimize the number of masks that are modified by routing to the uppermost layer of each logic in the logic configuration of the integrated circuit. It is not necessary to stack layers on logic in the form of stacks for routing, but it is sufficient if the top layer can be reached using the empty space on the integrated circuit. .

Therefore, in the conventional spare logic device including only the first metal, a plurality of metals and a plurality of via holes may be stacked until the top layer is reached.

3 shows a net-list for the redundant logic elements described in the above example. An embodiment of an integrated circuit manufacturing method according to the present invention will be described with reference to FIG. 3.

First, an arbitrary extra logic element is added during fabrication of an integrated circuit. In the case of adding an extra logic element, it is preferable to add a floating net that is not connected to another logic element for each pin of the extra logic element.

In the example of FIG. 3, an inverter S2, which is an extra logic element, adds a floating net for the input (.A (S2_A_Net)) and the output (.Y (S2_A_Net)) together, and the or gate (or gate) S3 represents an example in which a floating net is added for a first input (.A (S3_A_Net)), a second input (.B (S3_A_Net)), and an output (.Y (S3_A_Net)).

In addition, the pin is pinned from the region where the extra logic element is located to the uppermost metal layer so as not to affect the signal routing of the uppermost layer of the existing logic element other than the redundant logic element. To form.

If there is a change in the design of the integrated circuit formed as described above, routing is performed by connecting inputs and outputs of the redundant logic device using pins of the uppermost layer of the redundant logic device. In the routing, it is desirable to connect logic elements so that they can be connected at a minimum distance.

In addition, the deposition material of the integrated circuit has been described as a metal (metal) as an example, in the integrated circuit manufacturing method according to the present invention is not necessarily to use only the metal as a deposition material, the corresponding material, for example, a dielectric (dielectric), insulators, polymers and the like may be used.

In the case of designing and manufacturing an integrated circuit using the above method, even if there is a circuit design change according to a user later, a new logic element may be connected by modifying only one mask layer at least. Thus, further costs and additional process difficulties may be reduced.

It is easy for a person skilled in the art to change or modify the present invention from the present specification. Thus, although an embodiment of the present invention has been described above clearly, various modifications thereof should be made without departing from the spirit and the scope of the invention.

Referring to the effects of the integrated circuit manufacturing method according to the present invention described above are as follows.

According to the integrated circuit manufacturing method according to the present invention, even if a design change after fabricating the integrated circuit is required at the time of fabricating the integrated circuit, the modification cost due to the design change of the logic can be minimized.

Claims (5)

In the manufacturing method of an integrated circuit having a plurality of logic elements, (a) forming redundant logic not connected to the plurality of logic elements; And and (b) forming one or more via holes and one or more layers of deposition material on the redundant logic device if a logic device is formed in the redundant logic. . The method of claim 1, The step (b) is a manufacturing method of an integrated circuit, characterized in that to form a pin (pin) on the uppermost deposited material layer on the logic device. In the manufacturing method of an integrated circuit having a plurality of logic elements, (a) forming redundant logic not connected to the plurality of logic elements; And (b) forming one or more via holes and one or more layers of deposited material in the redundant logic at the same height as the top layer of the plurality of logic elements when forming the redundant logic; Method for manufacturing an integrated circuit, characterized in that. The method of claim 3, The step (b) of the integrated circuit manufacturing method, characterized in that to form a pin (pin) of the highest deposition material layer of the deposition material layer connected to the logic. The method of claim 3, The deposition material of step (b) is a manufacturing method of an integrated circuit, characterized in that the metal (metal).

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