KR100668500B1 - Data Verification Circuit of Semiconductor Memory - Google Patents

Abstract

A data verification circuit of a semiconductor memory according to the present invention includes: data level detection means for outputting first read data input in parallel as second read data at a common output node; Level comparison means for inputting write data and the second read data to output a first comparison signal and a second comparison signal; And error determination means for determining a pass or fail of a memory cell by inputting the first comparison signal and the second comparison signal.

Description

Data Verification Circuit of Semiconductor Memory

1 is a layout view of a data verification circuit of a general semiconductor memory;

FIG. 2 is a general circuit diagram of the data test unit shown in FIG. 1;

3 is a layout view of a data verifying circuit of a semiconductor memory according to the present invention;

4 is a block diagram of a data test unit shown in FIG. 3;

FIG. 5 is a detailed circuit diagram of the data test unit shown in FIG. 4.

<Description of the symbols for the main parts of the drawings>

100, 300: memory cell array 200, 400: data test unit

410: data level detection unit 430: level comparison unit

450: error determination unit

The present invention relates to a data verification circuit of a semiconductor memory, and more particularly, to a data verification circuit of a semiconductor memory for verifying a pass or fail by comparing read data with write data in a parallel test mode.

In general, in the case of a semiconductor memory device such as a DRAM (DRAM), data read and write operations must be performed accurately. To this end, a single bad cell (on chip) Fail Cell) should not exist. However, as the number of cells integrated in one chip increases to more than tens of millions due to the trend of ultra high integration, the possibility of defective cells is relatively higher despite the development of manufacturing process. have. If such a defective cell is not accurately tested, reliability as a semiconductor memory device cannot be secured.

In general, in a semiconductor memory device, a test for a highly integrated memory device is performed when each cell is tested to produce a memory chip to cover a pass / fail of a cell. Not only does it take longer, it also leads to an increase in cost.

Therefore, the parallel test mode is used to reduce the test time.

Parallel test uses an exclusive Nor logic circuit to write the same data to multiple cells and then read, and determines the pass as 1 when the same data is read. Reduce test time by failing to zero when any other data is read.

1 is a layout view illustrating a data verification circuit of a general semiconductor memory.

A data verification circuit of a general semiconductor memory tests a memory cell array 100 in which one write data WT_DATA is stored in four memory cells and read data RD_DATA <0: 3> read from the memory cells. The data test unit 200 determines whether the read data RD_DATA <0: 3> are the same level and outputs a result value.

FIG. 2 is a general circuit diagram of the data test unit shown in FIG. 1.

As shown in FIG. 2, generally, the data test unit uses an exclusive nor gate.

The data test unit 200 may include a first NAND gate ND1 and a first NOR gate NR1 and two read data RD_DATA <2: 3> as inputs of two read data RD_DATA <0: 1>. The third NOR gate ND2 and the second NOR gate NR2, the third NOR gate ND2 and the output value of the first NAND gate ND1 and the second NAND gate ND2. NR3, a third NAND gate ND3 for inputting output values of the first NOR gate NR1 and the second NOR gate NR2, and an inverting output value of the third NOR gate NR3. A first inverting means IV1, a first inverting means IV1, and a fourth NAND gate ND4 that accepts an output value of the third NAND gate ND3.

If the data test unit 200 has another level among the read data RD_DATA <0: 3>, the output OUTPUT is at a low level so that write and read operations are normally processed. If it is not possible, it is determined that the cells are Fail, and if they all have the same value, the cells are at a high level and the write and read operations are normally processed to determine that the cells are Pass.

When the write data WT_DATA is stored in four cells and one of the read data RD_DATA <0: 3> read from the four cells is a fail, the data test unit 200 fails. Although the failure of the cell can be accurately determined, if the read data RD_DATA <0: 3> are all defective, the data test unit 200 correctly processes read and write operations. As a result of this determination, a problem arises that reduces the reliability of the test.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a data verification circuit of a semiconductor memory capable of calculating accurate test results by comparing read data with data originally written during a read operation in a parallel test mode circuit. There are technical challenges to providing it.

According to another aspect of the present invention, there is provided a data verification circuit of a semiconductor memory, comprising: data level detection means for outputting first read data input in parallel as second read data at a common output node; Level comparison means for inputting write data and the second read data to output a first comparison signal and a second comparison signal; And error determination means for determining a pass or fail of a memory cell by inputting the first comparison signal and the second comparison signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention in more detail.

3 is a layout view of a data verification circuit of a semiconductor memory according to the present invention.

The data verification circuit of the semiconductor memory according to the present invention includes a memory cell array 300 in which write data WT_DATA is input to four cells, the write data WT_DATA, a write control signal WT_CTRL, and the memory cell array 300. ) Includes a data test unit 400 for determining a pass or a fail of a memory cell by inputting the first read data RD_DATA <0: 3>, which reads four pieces of data.

4 is a block diagram of the data test unit shown in FIG. 3.

As illustrated in FIG. 4, the data test unit 400 outputs one second read data RD_DATA_SUM by inputting first read data RD_DATA <0: 3> input in parallel. A level comparison unit outputting the first comparison signal LEVEL1_COM and the second comparison signal LEVEL2_COM by inputting the data 410, the write data WT_DATA, the write control signal WT_CTRL, and the second read data RD_DATA_SUM. 430 and an error determination unit 450 that determines a pass or fail of a memory cell by inputting the first comparison signal LEVEL1_COM and the second comparison signal LEVEL2_COM.

FIG. 5 is a detailed circuit diagram of the data test unit shown in FIG. 4.

The data level detector 410 may have the same resistance element R51 as the input line of the first read data RD_DATA <0: 3> to which the first read data RD_DATA <0: 3> is input in parallel. And a second read that is a parallel voltage level of the first read data RD_DATA <0: 3> at a common output node where the input lines of the first read data RD_DATA <0: 3> meet. Output the data RD_DATA_SUM.

The level comparison unit 430 may include a write data input unit 431 for inputting the write data WT_DATA in response to the write control signal WT_CTRL, the second read data RD_DATA_SUM and the write data WT_DATA. The first comparison unit 433 outputs a first comparison signal LEVEL1_COM and a second comparison signal LEVEL2_COM by comparing the second read data RD_DATA_SUM and the write data WT_DATA. It consists of two comparison parts 435.

The write data input unit 431 inputs the write control signal WT_CTRL to a gate terminal, and receives the first NMOS transistor N51 and the first NMOS transistor to receive the write data WT_DATA at a drain terminal. Inverted by the first inverting means IV51 connected to the source end of N51, the second inverting means IV52 forming a latch structure with the first inverting means IV51, and the first inverting means IV51. And third inverting means IV53 for inverting the write data WT_DATA.

The first comparator 433 may include a second NMOS transistor N52 having a source terminal connected to the ground terminal VSS and receiving the second read data RD_DATA_SUM from a gate terminal, and a source terminal of the second NMOS transistor N52. A third NMOS transistor N53 connected in common with a source terminal of the MOS transistor N52 and receiving the write data WT_DATA from a gate terminal, a source terminal connected to an external supply power supply VDD, and a gate terminal and a drain terminal A first PMOS transistor P51 and a source terminal connected to the drain terminal of the third NMOS transistor N53 are connected to the external supply power supply VDD, and a gate terminal thereof is connected to the gate terminal of the first PMOS transistor P51. The drain terminal includes a drain terminal of the second NMOS transistor N52 and a second PMOS transistor P52 connected at the first common node node_A.

The second comparator 435 may include a fourth NMOS transistor N54 having a source terminal connected to the ground terminal VSS and receiving the second read data RD_DATA_SUM from a gate terminal, and a source terminal of the fourth NMOS transistor N54. A fifth NMOS transistor N55 connected in common with the source terminal of the MOS transistor N54 and receiving the write data WT_DATA from the gate terminal, a source terminal connected to the external supply power supply VDD, and a gate terminal and a drain terminal connected to each other. A third PMOS transistor P53 and a source terminal connected to the drain terminal of the fourth NMOS transistor N54 are connected to the external supply power supply VDD, and a gate terminal thereof is a gate of the third PMOS transistor P53. A drain terminal of the fifth NMOS transistor N55 and a fourth PMOS transistor P54 are connected to each other at the second common node node_B.

In addition, the first comparator and the second comparator may be provided as a differential amplifier different from the above embodiment by inputting the second read data RD_DATA_SUM and the write data WT_DATA.

The error determination unit 450 receives, as an input, the first comparison signal LEVEL1_COM output from the first common node node_A and the second comparison signal LEVEL2_COM output from the second common node node_B. The first NAND gate ND51, the first NOR gate NR1 and the first comparison signal LEVEL1_COM and the second comparison signal LEVEL2_COM are inputted, and are output from the first NOR gate NR1. A fourth inverting means IV54 for inverting the signal and a second NAND gate ND52 for inputting the signal output from the first NAND gate ND51 and the signal output from the fourth inverting means IV54. do.

In addition, the error determiner 450 may be configured in the form of a logic circuit and a logic element for different output signals when two input signals are the same and when the two input signals are different. For example, the error determiner 450 may include an exclusive nor gate that receives the first comparison signal LEVEL1_COM and the second comparison signal LEVEL2_COM.

A data verification circuit of a semiconductor memory according to the present invention will be described with reference to FIGS. 3 to 5 as follows.

When one write data WT_DATA is stored in four cells of the memory cell array 300 by a write control signal WT_CTRL, the write data input unit 431 responds to the write control signal WT_CTRL. It receives (WT_DATA).

Subsequently, the first read data RD_DATA <0: 3> read by the data level detector 410 from the memory cell array 300 during the read operation may include the resistor elements R51. The second read data RD_DATA_SUM, which is a parallel voltage level of the first read data RD_DATA <0: 3>, is output at a common output node where the input lines of the first read data RD_DATA <0: 3> meet. do.

If the level of the first read data RD_DATA <0: 3> input to the data level detector 410 is the same, the output signal is output from a node where four input lines including the resistance element R51 meet. The level of the second read data RD_DATA_SUM becomes equal to the level of the first read data RD_DATA <0: 3> and the write data WT_DATA.

If a different level exists among the first read data RD_DATA <0: 3> input to the data level detector 410, the level of the second read data RD_DATA_SUM is different from that of the write data WT_DATA. do. When the write data WT_DATA level is high, the second read data RD_DATA_SUM level becomes lower than the write data WT_DATA level, and when the write data WT_DATA level is low, the second read data. The RD_DATA_SUM level is higher than the write data WT_DATA level.

When the write data WT_DATA is input to the memory cell array 300 by the write control signal WT_CTRL, the write data input unit 431 responds to the write control signal WT_CTRL in response to the write data WT_DATA. ) Is input and the write data WT_DATA is stored by the first inverting means IV51 and the second inverting means IV52 forming a latch structure and the write data WT_DATA through the third inverting means IV53. ) Is output.

The first comparator 433 compares the second read data RD_DATA_SUM level with the write data WT_DATA level and outputs a first comparison signal LEVEL1_COM through the first common node node_A. The second comparator 435 compares the second read data RD_DATA_SUM level with the write data WT_DATA level and outputs a second comparison signal LEVEL2_COM through the second common node node_B.

When the second read data RD_DATA_SUM level and the write data WT_DATA level are the same, the first comparison signal LEVEL1_COM and the second comparison signal LEVEL2_COM have the same level, and the second read data ( When the RD_DATA_SUM level is different from the write data WT_DATA level, the first comparison signal LEVEL1_COM and the second comparison signal LEVEL2_COM have different levels.

The error determiner 450 which receives the first comparison signal LEVEL1_COM and the second comparison signal LEVEL2_COM may have a different level than the first comparison signal LEVEL1_COM and the second comparison signal LEVEL2_COM. In this case, it is determined that the write and read operations are fail by outputting a low level, and when the first comparison signal LEVEL1_COM and the second comparison signal LEVEL2_COM are at the same level, a high level is output to write. And the read operation is determined as a pass.

As described above, the data verification circuit of the semiconductor memory according to the present invention compares the original write data WT_DATA stored in the memory cell with the read data RD_DATA read from the memory cell in the parallel test mode, thereby providing the read data. When all of the RD_DATA are fail, the problem of the conventional data verification circuit, which is determined as a pass, can be solved, thereby improving the reliability of the test.

The data verification circuit of the semiconductor memory according to the present invention has an effect of accurately determining even when all the data read during the read operation in the parallel test mode is a fail, thereby improving the reliability of the test mode device.

Claims (8)

Data level detection means for outputting first read data input in parallel as second read data at a common output node; Level comparison means for inputting write data and the second read data to output a first comparison signal and a second comparison signal; And And error determination means for determining a pass or fail of a memory cell by inputting the first comparison signal and the second comparison signal. The method of claim 1, The data level detection means, And a same resistance element is provided in each of the input lines of the first read data. The method of claim 1, The level comparison means, A write data input unit configured to input the write data in response to a write control signal; a first comparer configured to compare the second read data with the write data and output a first comparison signal; and the second read data and the write data. And a second comparator for outputting a second comparison signal by comparing with the second data. The method of claim 3, wherein The write data input unit, A first NMOS transistor receiving the write data at a drain terminal, a first inverting means connected to a source terminal of the first NMOS transistor, and a first inverting means; And second inverting means constituting a latch structure and third inverting means for inverting the write data inverted by the first inverting means. The method of claim 3, wherein The first comparison unit, And a differential amplifier having the second read data and the write data as inputs. The method of claim 3, wherein The second comparison unit, And a differential amplifier having the second read data and the write data as inputs. The method of claim 3, wherein The error determining means, And a logic element for inputting the first comparison signal and the second comparison signal. The method of claim 7, wherein And the logic element is an exclusive NOR gate.

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