KR100656424B1 - Delay circuit of semiconductor memory device - Google Patents

Abstract

The present invention relates to a delay circuit of a semiconductor memory device capable of having the same delay time regardless of a temperature change, comprising: temperature detecting means for detecting a temperature and outputting the digital code value by one or more bits, and a digital code output from the temperature detecting means. The delay time is determined according to the value, and includes a variable delay means for delaying and outputting the input signal by the determined delay time, so that the same signal delay operation is always performed under various temperature conditions in which the semiconductor memory device operates to improve reliability of the product. Can be.

Description

Delay circuit of semiconductor memory device

1 is a circuit diagram illustrating a delay circuit of a semiconductor memory device according to the prior art;

2 is a waveform diagram of each part of the delay circuit of FIG. 1;

3 is a circuit diagram illustrating a delay circuit of a semiconductor memory device according to the present invention;

4 is a waveform diagram of each part of the delay circuit according to FIG. 3;

5 is a circuit diagram showing a second embodiment of the delay circuit of the semiconductor memory device according to the present invention.

-Explanation of symbols for the main parts of the drawings-

31: temperature detector 32: delay time fixing unit

33: variable delay unit 34: second variable delay unit

35: timing controller 36: inverter

M0 to M4, M6 to M10: Transistors M5, M11: Capacitor

The present invention relates to a semiconductor memory device, and more particularly to a delay circuit of a semiconductor memory device.

As shown in FIG. 1, a delay circuit of a semiconductor memory device according to the related art includes a first delay unit 11 and an output of the first delay unit 11 that delay an input signal by a predetermined first delay time. A second delay unit 12 for delaying a signal by a predetermined second delay time, a NAND gate outputting a low signal during an interval in which the output signal of the second delay unit 12 and the input signal are 'high' (13) and an inverter (14) for inverting the output signal of the NAND gate (13).

The first delay unit 11 is connected to a power supply terminal (VDD) and a ground terminal (GND), respectively, and operates as an inverter (M0 and M1), a resistor (R0) and an output connected between the transistors (M0 and M1). And a capacitor M2 connected in parallel with the line. The first delay time of the first delay unit 11 is determined by the time constant of the resistor R0 and the capacitor M2, that is, the RC time constant. Therefore, as shown in FIG. 2, the first delay unit 11 delays the input signal IN by the first delay time Td1.

The second delay unit 12 is configured similarly to the first delay unit 11, and the second delay time of the second delay unit 12 is increased by time constants of the resistor R1 and the capacitor M5. Is determined. As shown in FIG. 2, the second delay unit 12 delays the output signal of the first delay unit 11 by a second delay time Td2.

The NAND gate 13 outputs a low signal during an interval in which the output signal of the second delay unit 12 and the input signal are 'high', thereby shifting the output signal of the second delay unit 12. The timing is matched with the transition timing of the input signal.

The inverter 14 inverts the output signal waveform of the NAND gate 13 to have the same phase as the input signal.

As a result, the output signal is a waveform obtained by delaying the input signal by the time Tdt of the sum of the first and second delay times.

However, in the delay circuit of the semiconductor memory device according to the related art, the delay time is determined according to the values of the resistors R0 and R1. However, since the values of the resistors R0 and R1 change as the temperature changes, the delay time is not uniform. There is a problem that a deviation occurs.

The present invention has been made to solve the above problems, and an object thereof is to provide a delay circuit of a semiconductor memory device capable of having the same delay time regardless of temperature change.

In the delay circuit of the semiconductor memory device according to the present invention, a delay time is determined according to temperature detecting means for detecting a temperature and outputting one or more bits as a digital code value, and a digital code value output from the temperature detecting means. And variable delay means for delaying and outputting the input signal by time.

In the delay circuit of the semiconductor memory device according to the present invention, a delay time is determined according to a digital code value output from the temperature detection means, and a second variable delay for delaying and outputting the output signal of the variable delay means by the determined delay time. Characterized in that it further comprises means.

The delay circuit of the semiconductor memory device according to the present invention may further include timing control means for causing the transition timing of the output signal of the variable delay means to coincide with the transition timing of the input signal.

The delay circuit of the semiconductor memory device according to the present invention further comprises delay time fixing means for fixing the delay time of the variable delay means regardless of the digital code value output from the temperature detection means according to an external control signal. do.

Hereinafter, a preferred embodiment of a delay circuit of a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

3 is a circuit diagram showing a delay circuit of the semiconductor memory device according to the present invention, FIG. 4 is a waveform diagram of each part according to FIG. 3, and FIG. 5 is a circuit diagram showing a second embodiment of the delay circuit of the semiconductor memory device according to the present invention. .

According to the first embodiment of the delay circuit of the semiconductor memory device according to the present invention, as shown in FIG. 3, a temperature detector 31 which detects a temperature and outputs one or more bits of a digital code value according to the digital code value. A time is determined, and includes a variable delay unit 33 for delaying and outputting the input signal by the determined delay time.

In addition, the timing control unit 35 may further include a timing control unit 35 so that the transition timing of the output signal of the variable delay unit 33 matches the transition timing of the input signal.

The delay time is determined according to the digital code value so as to increase the total delay time, and the second variable delay unit 34 delays and outputs the output signal of the variable delay unit 33 by the determined delay time. It may further include.

In addition, when the timing controller 35 and the second variable delay unit 34 are further included, the inverter 36 for inverting the output signal of the timing controller 35 so that the final output waveform is in phase with the input signal. ) Is further configured.

The temperature detector 31 may be configured inside or outside the semiconductor memory. In the embodiment of the present invention, the temperature detector 31 is configured to output a two-digit digital code value. The digital code values T1 and T2 according to temperature are as follows. .

If the temperature is above 70 degrees: T1 = H, T2 = H

For temperatures between 45 and 70: T1 = H, T2 = L

If the temperature is 15 to 45: T1 = L, T2 = H

If the temperature is below 15 degrees: T1 = L, T2 = L

At this time, H is high and L is low.

The variable delay unit 33 is a delay unit including at least two resistors R0 to R3 connected in series and a first driver M0 connected to one end of the delay unit and a power supply terminal and outputting the power level according to an input signal. And a second driver M1 connected to one end of the delay unit and a ground terminal to output a ground level according to an input signal, and selectively connected to the delay unit to the two or more resistors R0 to R3 according to the digital code value. It includes a switching unit consisting of transistors (M2 ~ M4) for operation, and a capacitor (M5) connected in parallel to the output terminal. The first driver M0 and the second driver M1 are transistors, and the input signal is input to the gate terminals of the first driver M0 and the second driver M1 through an input terminal IN.

The second variable delay unit 34 is configured in the same manner as the variable delay unit 33.

The timing controller 35 receives the input signal and the output signal of the variable delay unit 33, and the input signal and the output signal of the second variable delay unit 34 have the same level, that is, a high level. It consists of a logic element that outputs a low level signal, that is, a NAND gate.

Referring to the operation of the present invention configured as described above are as follows.

First, when the digital code values output from the temperature detector 31 are T1 = L and T2 = L:

Since all the transistors M2 to M4 of the switching section of the variable delay section 33 and all the transistors M8 to M10 of the switching section of the second variable delay section 34 are off, four resistors of the variable delay section 33 are turned off. Both R0 to R3 and the four resistors R4 to R7 of the second variable delay unit 34 operate. That is, a current path through the operating resistor is formed.

Therefore, as shown in FIG. 4, the input signal IN is delayed by each of the delay times Tdv1 and Tdv2 corresponding to the resistors R0 to R3 and the resistors R4 to R7 and is respectively caused by the first and second drivers. Inverted output.

As shown in FIG. 4, the timing controller 35 outputs the output signal of the second variable delay unit 34 and the low signal while the input signal is high, thereby outputting the output signal of the second variable delay unit 34. The transition timing of is equal to the transition timing of the input signal.

Subsequently, the inverter 36 inverts the output signal of the timing controller 35 to be in phase with the input signal as shown in FIG. 4.

Next, when the digital code values output from the temperature detector 31 are T1 = L and T2 = H:

Since all the transistors except the transistor M4 of the switching unit of the variable delay unit 33 and the transistor M10 of the switching unit of the second variable delay unit 34 are all in an OFF state, the three resistances of the variable delay unit 33 ( R0 to R2 and the three resistors R4 to R6 of the second variable delay unit 34 operate.

Therefore, as shown in FIG. 4, the input signal IN is delayed by each of the delay times Tdv1 and Tdv2 corresponding to the resistors R0 to R2 and the resistors R4 to R6 and is respectively caused by the first and second drivers. Inverted output.

In this case, the delay time is shorter than when all four resistors of the variable delay unit 33 and the second variable delay unit 34 operate.

Only the delay time is applied differently according to the number of operating resistors, and other operations are the same, and thus description thereof will be omitted.

Next, when the digital code values output from the temperature detector 31 are T1 = H and T2 = L:

Since all the transistors except the transistor M4 of the switching unit of the variable delay unit 33 and the transistor M10 of the switching unit of the second variable delay unit 34 are all in an on state, the two resistances of the variable delay unit 33 ( R2 and R3 and two resistors R6 and R7 of the second variable delay unit 34 are operated.

Therefore, as shown in FIG. 4, the input signal IN is delayed by each of the delay times Tdv1 and Tdv2 corresponding to the resistors R2 and R3 and the resistors R6 and R7, respectively, by the first and second drivers. Inverted output.

At this time, the delay time is shorter than when three resistors of the variable delay unit 33 and the second variable delay unit 34 operate.

Only the delay time is applied differently according to the number of operating resistors, and other operations are the same, and thus description thereof will be omitted.

Next, when the digital code values output from the temperature detector 31 are T1 = H and T2 = H:

Since the transistors M2 to M4 of the switching unit of the variable delay unit 33 and the transistors M8 to M10 of the switching unit of the second variable delay unit 34 are both in an on state, one resistor of the variable delay unit 33 ( R2) and one resistor R6 of the second variable delay unit 34 are operated.

Therefore, as shown in FIG. 4, the input signal IN is delayed by the respective delay times Tdv1 and Tdv2 corresponding to the resistors R2 and R6, and is inverted and output by the respective first and second drivers. .

At this time, the delay time is shorter than when two resistors of the variable delay unit 33 and the second variable delay unit 34 operate.

Only the delay time is applied differently according to the number of operating resistors, and other operations are the same, and thus description thereof will be omitted.

As a result, the delay times Tdv1 and Tdv2 are determined in accordance with the number of operating resistors. In other words, the larger the number of operating resistors, the greater the delay time.

That is, the present invention is to compensate for the circuit characteristics that the delay time is reduced when the temperature is lowered, and to set the digital code value of the temperature detector so that the number of operating resistors increases as the temperature is lowered The variable delay unit is configured. Of course, it is also possible to configure the opposite case with a simple circuit change.

In addition, in the embodiment of the present invention, an example of using a 2-bit digital code value has been described. However, if the number of bits of the digital code is increased and a related circuit is configured accordingly, more detailed delay compensation for each temperature is possible.

5 shows a second embodiment of the present invention, in which a delay time fixing unit 32 is added between the temperature detector 31 and the variable delay unit 33.

The delay time fixing unit 32 receives an external control signal and the digital code value, and when the external control signal is a high level, the variable delay unit 33 and the low level signal regardless of the digital code value. It consists of the 1st and 2nd NOR gates which input to the 2nd variable delay part 34. FIG. At this time, the transistors of the switching units of the variable delay unit 33 and the second variable delay unit 34 should use P type.

Noah gates have the characteristic that if one of their inputs is at a high level, the output is unconditionally low. Therefore, by applying an external control signal at a high level to output a low level signal irrespective of a digital code value, the number of resistors operating in the variable delay unit 33 and the second variable delay unit 34 is fixed. After all, the delay time is fixed.

This is to prepare for the case that the delay time variation is not necessary or the error of the circuit operation is caused by the delay time variation.

Of course, when the external control signal input to the NOA gate of the delay time fixing unit 32 is at a low level, the delay time variable operation according to temperature is normally performed as in the first embodiment of the present invention.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

Since the delay circuit of the semiconductor memory device according to the present invention compensates for the delay time reduced according to the current temperature, the same signal delay operation is always performed under the temperature condition in which the semiconductor memory device operates, thereby improving the reliability of the product.

Claims (12)

In a semiconductor memory device, Temperature detecting means for detecting the temperature and outputting the digital code value by one or more bits; And And a delay time is determined according to the digital code value output from the temperature detection means, and variable delay means for delaying and outputting the input signal by the determined delay time. The method of claim 1, The variable delay means includes a delay unit comprising at least two delay elements; A first driver connected to one end of the delay unit and a power supply terminal to output the power level according to an input signal; A second driver connected to one end of the delay unit and a ground terminal to output a ground level according to an input signal; And a switching unit connected to the delay unit for selectively operating the two or more delay elements in accordance with the digital code value. The method of claim 2, And the maximum controllable number of delay elements is determined according to the number of bits of the digital code. The method of claim 2, And the delay unit includes at least two resistors connected in series. The method of claim 2, The first driver and the second driver is a delay circuit of the semiconductor memory device, characterized in that the transistor for receiving an input signal to the gate. The method of claim 2, And the switching unit is a transistor having the digital code value input to a gate and a source and a drain thereof connected to both ends of the delay element. The method of claim 1, And a second variable delay means for determining a delay time according to the digital code value output from the temperature detection means, and delaying and outputting the output signal of the variable delay means by the determined delay time. Delay circuit of the device. The method of claim 7, wherein And the second variable delay means has the same configuration as the variable delay means. The method of claim 1, And timing control means for causing the transition timing of the output signal of the variable delay means to coincide with the transition timing of the input signal. The method of claim 9, The timing control means is a logic element that receives the input signal and the output signal of the variable delay means, and outputs a signal of a predetermined level during a period in which the input signal and the output signal of the variable delay means are the same level. A delay circuit of a semiconductor memory device. The method of claim 1, And a delay time fixing means for fixing the delay time of the variable delay means regardless of the digital code value output from the temperature detection means in accordance with an external control signal. The method of claim 11, The delay time fixing means receives an external control signal and the digital code value, and a logic element for inputting a fixed level signal to the variable delay means regardless of the digital code value when the external control signal has a predetermined level. The delay circuit of the semiconductor memory device characterized by the above-mentioned.

Images