JP2000201058A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a delay circuit for deciding the variations of a delay time in a delay circuit generated due to the variations of a process, and for adjusting a delay time corresponding to the variations. SOLUTION: A delay time D of a comparison delay circuit 3 varies due to the variations of process, and reference delay times Dref1 and Dref2 are preliminarily set in a reference delay circuit 2. In this case, when the delay time D < the reference time Dref1, the delay of a signal is operated by using a first delay circuit 51 whose delay time is the longest, and when Dref1$ D< Dref2, the delay of a signal is operated by using a second delay circuit 52 whose delay time is longer than that of the first delay circuit 51, and when D>=Dref2, the delay of a signal is operated by using a third delay circuit 53 whose delay time is the shortest.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a delay circuit, and more particularly to a semiconductor device having a delay circuit capable of adjusting a variation in delay time caused by a process variation.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram showing an example of a conventional delay circuit using an inverter. 7, a delay circuit 200 is formed by connecting a plurality of inverters, for example, inverters 201 to 206 in FIG. 7 in series.
Such a delay circuit 200 obtains a desired delay time by changing the number of inverters connected in series, and forms a semiconductor device in order to obtain a delay time corresponding to a delay caused by wiring. It is formed in a semiconductor integrated circuit.

[0003]

However, the delay time of the inverter varies due to the variation in the process of forming such a semiconductor integrated circuit, and the required delay time cannot be obtained in some cases. For this reason, in the semiconductor device, there is a case where the difference in the variation between the internal wiring and the inverter may hinder the circuit operation and result in a defective product. In such a case, the semiconductor device is changed by changing the circuit configuration and using a new circuit. Was created again. As described above, in order to cope with the variation in the delay time of the delay circuit due to the variation in the process or the like, it is necessary to perform a process of changing the circuit and forming the circuit again, and there is a problem that the cost increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. The present invention determines a variation in delay time in a delay circuit caused by a variation in a process, and adjusts the delay time according to the variation. It is an object of the present invention to obtain a semiconductor device including a delay circuit which can be performed.

Although the construction is different from that of the present invention,
In Japanese Patent Application Laid-Open No. 304484/2004, a circuit for comparing a preset reference delay value with an external clock cycle, an internal delay circuit composed of a main delay circuit and a plurality of adjustment delay circuits, There is disclosed a synchronous semiconductor memory device that automatically optimizes an internal delay value by comparing a delay value with a cycle of an external clock. Although the purpose and the configuration are different from those of the present invention, the output resistances of the (n + 1) cascaded inverters and the switches and capacitors connected between the connection points of the adjacent inverters and the common potential point, respectively. A variable delay circuit including a series circuit and capable of miniaturizing a minimum adjustment unit of the delay time is disclosed.

[0006]

A semiconductor device according to the present invention is a semiconductor device provided with a delay circuit, comprising: a comparison delay circuit portion comprising a delay circuit used to determine a variation in delay time; A reference delay circuit unit including a delay circuit set to at least one predetermined reference delay time serving as a reference value of the delay time, and a delay in the comparison delay circuit unit based on the reference delay time of the reference delay circuit unit A delay time determination circuit for determining a variation in time, and a plurality of delay circuits set to different delay times, and selecting one of the delay circuits according to a determination result of the delay time determination circuit; , A delay adjusting circuit for delaying a desired signal.

In a semiconductor device according to the present invention, in a semiconductor device having a delay circuit, a comparison delay circuit portion including a delay circuit used to determine a variation in delay time, and a delay time reference. A reference delay circuit unit including a delay circuit set to at least one predetermined reference delay time, and a delay time variation in the comparison delay circuit unit based on the reference delay time of the reference delay circuit unit. A delay time determination circuit unit to determine, a determination output circuit unit that outputs a determination result of the delay time determination circuit unit to an external device,
It has a plurality of delay circuits set to different delay times, and one of the delay circuits is selected by an external device according to the determination result output from the determination output circuit unit, and using the selected delay circuit And a delay adjusting circuit for delaying a desired signal.

Further, in the semiconductor device according to the present invention, in any one of the first and second aspects, specifically, the comparison delay circuit section is a delay circuit whose delay time varies according to process variations. And the reference delay circuit section is configured by at least one delay circuit formed using a resistor and a capacitor that are not affected by process variations, and the delay circuit is set to a predetermined reference delay time in advance. Things.

In the semiconductor device according to the present invention, the comparison delay circuit unit and the reference delay circuit unit may be configured such that a predetermined delay signal inputted when power is turned on is provided. Each of the signals is delayed, and the delay time determination circuit determines delay time variations from delay signals input from the comparison delay circuit and the reference delay circuit.

Further, the semiconductor device according to the present invention is a semiconductor device having a delay circuit, comprising a delay circuit used for judging a variation in delay time, wherein a delay of a signal input from an external device is reduced. And a plurality of delay circuits set at different delay times. One of the delay circuits is output from the external device according to the variation in the delay time in the comparison delay circuit unit. And a delay adjusting circuit unit for performing a delay on a desired signal by using the selected delay circuit.

According to a second aspect of the present invention, in the semiconductor device according to the second aspect of the present invention, the delay adjustment circuit section includes a fuse for selecting one of a plurality of delay circuits. Is provided, and one of the delay circuits is fixedly selected by blowing the fuse by an external device.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing an example of a semiconductor device according to the first embodiment of the present invention. In FIG.
The semiconductor device 1 is provided with a reference delay circuit 2 formed of process-stable resistors and capacitors which are not affected by transistors and set to a reference delay time, and for determining a delay time variation due to a process variation or the like. A delay time determination circuit 4 that determines the magnitude of the delay time of the comparison delay circuit 3 with respect to the delay time of the reference delay circuit 2 and outputs the determination result;
A delay adjusting circuit for variably adjusting the delay time in accordance with the result of the determination by the delay time determining circuit;

The input of the reference delay circuit 2 is supplied with an internal signal that changes from the ground potential to the power supply potential at a certain time when the power is turned on. A comparison delay circuit 3 is connected to the reference delay circuit 2, and the reference delay circuit 2 and the comparison delay circuit 3
Each is connected to the delay time determination circuit 4. Further, the delay time determination circuit 4 is connected to the delay adjustment circuit 5. The input of the delay adjustment circuit 5 receives an internal signal for delaying, and the internal signal is output after being delayed by the delay time adjusted by the delay adjustment circuit 5.

The reference delay circuit 2 includes inverters 11, 1
2. N-channel MOS transistor (hereinafter referred to as N-MO
S) 13, resistors 14, 15 and capacitors 16,
17. The resistor 14 and the capacitor 16 form one delay circuit set to a predetermined delay time, and the resistor 15 and the capacitor 17 form another delay circuit set to a predetermined delay time. The inverters 11 and 12 and the N-MOS 13 form a bypass circuit that bypasses the charges stored in the capacitors 16 and 17 to ground.

In the reference delay circuit 2, the inverter 11
And 12 are connected in series, the output of the inverter 12 forming the output of the series circuit is connected to one end of a resistor 14, and the other end of the resistor 14 is grounded via a capacitor 16.
The connection between the resistor 14 and the capacitor 16 is connected to one end of the resistor 15, and the connection is denoted by A. The other end of the resistor 15 is grounded via a capacitor 17 and the resistor 1
The connection between the capacitor 5 and the capacitor 17 is B. The connection between the inverters 11 and 12 is connected to the gate of the N-MOS 13, and in the N-MOS 13, the drain is connected to the connection B and the source is grounded. The input of the inverter 11 is an input of the reference delay circuit 2, and the output of the inverter 12, and the connection A and the connection B are outputs of the reference delay circuit 2, respectively.

The comparison delay circuit 3 includes seven inverters 21
27 are sequentially connected in series, a delay circuit is formed by the six inverters 21 to 26, and the signal level of the output signal of the delay circuit is inverted by the inverter 27. The input of the inverter 21 forms the input of the comparison delay circuit 3 and is connected to the output of the inverter 12.
Each output of 6 and 27 forms the output of the comparison delay circuit 3.

The delay time determination circuit 4 includes inverters 31 to
36, transfer gates 37 and 38 and 2-input NAN
D circuits 39 to 41, and inverters 31 and 32
Are connected in parallel in the opposite direction to form another latch circuit, and the signal level of the output signal of the latch circuit is inverted by the inverter 35. Similarly, inverters 33 and 3
4 are connected in parallel in the opposite direction to form one latch circuit, and the signal level of the output signal of the latch circuit is inverted by the inverter 36. The transfer gate 37 is formed by connecting input / output terminals of a P-channel MOS transistor (hereinafter, referred to as P-MOS) 37a and an N-MOS 37b in parallel. Similarly, the transfer gate 38 is formed by connecting the input / output terminals of the P-MOS 38a and the N-MOS 38b in parallel.

In the delay time determination circuit 4, a P-MOS
The gates of 37a and 38a are connected to each other, and the connection is connected to the output of the inverter 26 in the comparison delay circuit 3. The gates of the N-MOSs 37b and 38b are connected to each other, and the connection is connected to the output of the inverter 27 in the comparison delay circuit 3. In the transfer gate 37, one input / output terminal is connected to the connection A of the reference delay circuit 2, and the other input / output terminal is connected to the connection between the input of the inverter 31 and the output of the inverter 32. The connection between the output of the inverter 31 and the input of the inverter 32 is connected to the input of the inverter 35 and to one input of the NAND circuit 39, and the output of the inverter 35 is connected to one of the NAND circuits 40 and 41. Connected to input.

In the transfer gate 38, one input / output terminal is connected to a connection portion B of the reference delay circuit 2,
The other input / output terminal is connected to a connection between the input of the inverter 33 and the output of the inverter 34. The connection between the output of the inverter 33 and the input of the inverter 34 is connected to the input of the inverter 36 and the NAND circuit 39.
, And 40, and the output of the inverter 36 is connected to the other input of the NAND circuit 41. Each output of the NAND circuits 39 to 41 forms an output of the delay time determination circuit 4, respectively.

Next, the delay adjustment circuit 5 includes a first delay circuit 5
1, a second delay circuit 52, a third delay circuit 53, and a delay time switching circuit 54. The first delay circuit 51, the second delay circuit 52, and the third delay circuit 53 are set to different delay times. I have. For example, different even-numbered inverters are connected in series so as not to invert the signal level of the input signal, and the first delay circuit 51 has the longest delay time and the third delay circuit 53 has the longest delay time. It is formed so that the delay time of the second delay circuit 52 is an intermediate value between the two delay times. The delay time switching circuit 54 switches the first delay circuit 51, the second delay circuit 52, and the third delay circuit 53 to adjust the delay time, and includes two-input NOR circuits 56 to 58 and 3
The input NOR circuit 59 is formed.

The inputs of the first delay circuit 51, the second delay circuit 52, and the third delay circuit 53 are respectively connected to form an input of the delay adjustment circuit 5, and a signal for performing a delay is input to the input. . The output of the first delay circuit 51 is the NOR circuit 56
, The output of the second delay circuit 52 is connected to one input of a NOR circuit 57, and the output of the third delay circuit 53 is
Each is connected to one input of a circuit 58. The other input of the NOR circuit 56 is connected to the output of the NAND circuit 39, and the other input of the NOR circuit 57 is connected to the NAND circuit 4.
The output of 0 and the other input of the NOR circuit 58 are connected to the output of the NAND circuit 41, respectively. NOR circuit 5
Outputs 6 to 58 are connected to corresponding inputs of a NOR circuit 59, and an output of the NOR circuit 59 forms an output of the delay adjustment circuit 5.

In such a configuration, the reference delay circuit 2
Outputs the respective signals delayed by two types of predetermined delay times to the input signal to the delay time determination circuit 4, and the comparison delay circuit 3 delays the signal input to the reference delay circuit 2 The output signal is output to the delay time determination circuit 4.
The delay time determination circuit 4 compares the signal input from the comparison delay circuit 3 with the two signals input from the reference delay circuit 2 to determine two reference delay times Dref1 of the reference delay circuit 2.
Delay circuit 3 for Dref2 and Dref2 (Dref2> Dref1)
Of the delay time D is determined.

The delay adjusting circuit 5 outputs a signal input using any one of the first delay circuit 51, the second delay circuit 52 and the third delay circuit 53 in accordance with the result determined by the delay time determination circuit 4. Do a delay. For example, the delay adjustment circuit 5
When the delay time D is smaller than the reference delay time Dref1, the first delay circuit 51 having the longest delay time is used. When the delay time D is longer than the reference delay time Dref2, the third delay circuit 53 having the shortest delay time is used. In other cases, the input signal is delayed using the second delay circuit 52.

FIGS. 2 to 4 are timing charts showing waveforms of various parts in the semiconductor device 1 shown in FIG. 1. FIG. 2 shows the case where D <Dref1, and FIG. 3 shows Dref1 ≦ D <D.
FIG. 4 shows the case of ref2, and FIG. 4 shows the case of D ≧ Dref2. The operation of the semiconductor device 1 will be described in more detail with reference to FIGS.

2 to 4, (a) shows the input waveform of the inverter 11, (b) shows the output waveform of the inverter 11, (c) shows the output waveform of the inverter 26,
(D) shows the output waveform of the inverter 27, (e) shows the waveform of the connection A of the reference delay circuit 2, and (f) shows the waveform of the reference delay circuit 2.
(G) shows the output waveform of the inverter 31, and (h) shows the output waveform of the inverter 33.

When the power is turned on, a signal that changes from the “L” level, which is the ground potential, to the “H” level, which is the power supply potential, is input to the input of the inverter 11 after a while. After a reference delay time Dref1 from the rise of the signal from the "L" level to the "H" level, the connection portion A of the reference delay circuit 2 rises from the "L" level to the "H" level. After the input signal of the inverter 11 rises from the “L” level to the “H” level, the reference delay time Dre
After f2, the connection B of the reference delay circuit 2 rises from the "L" level to the "H" level. Further, after a delay time D from the rise of the input signal of the inverter 11 from the "L" level to the "H" level, the signal levels of the respective outputs of the inverters 26 and 27, which are the outputs of the comparison delay circuit 3, change.

Here, referring to FIG. 2, D <Dref1
The case will be described. From the time when the input of the inverter 11 rises from the “L” level to the “H” level until the delay time D, the output of the inverter 26 of the comparison delay circuit 3 is at the “L” level and the output of the inverter 27 is at the “H” level. Therefore, the transfer gates 37 and 38 are turned on and in a conductive state.

Therefore, the "L" level potential at the connection A of the reference delay circuit 2 is input to the inverter 31 via the transfer gate 37, the output of the inverter 31 becomes "H" level, and the output of the inverter 35 becomes It becomes "L" level. At the same time, the "L" level potential at the connection B of the reference delay circuit 2 is input to the inverter 33 via the transfer gate 38, the output of the inverter 33 becomes "H" level, and the output of the inverter 36 becomes "L" level. become. In this state, of the outputs of the NAND circuits 39 to 41, only the output of the NAND circuit 39 is at "L" level,
Since the other outputs are at the “H” level, the outputs of the NOR circuits 57 and 58 in the delay adjustment circuit 5 are “L” regardless of the output levels of the second delay circuit 52 and the third delay circuit 53, respectively. Level.

Next, when the delay time D elapses after the input of the inverter 11 rises from the "L" level to the "H" level, the output of the inverter 26 of the comparison delay circuit 3 changes from the "L" level to the "H" level. , And the output of the inverter 27 falls from the “H” level to the “L” level, so that the transfer gates 37 and 38 are both turned off and cut off. Therefore, each output of the inverters 31 and 33 is latched at the “H” level, respectively.
Of the NAND circuits 39 to 41, only the output of the NAND circuit 39 is at "L" level.

From this, of the outputs of the NAND circuits 39 to 41, only the output of the NAND circuit 39 is at "L" level and the other outputs are at "H" level.
Each output of the NOR circuits 57 and 58 in the delay adjustment circuit 5 becomes "L" level regardless of the output level of the second delay circuit 52 and the third delay circuit 53. on the other hand,
The output of the NOR circuit 56 of the delay adjustment circuit 5 rises from the “L” level to the “H” level when the output of the first delay circuit 51 falls from the “H” level to the “L” level.
The output of OR circuit 59 falls from "H" level to "L" level. Thus, the signals input to the respective inputs of the first to third delay circuits are delayed by using the first delay circuit 51 having the longest delay time.

Next, referring to FIG. 3, Dref1 ≦ D <
The case of Dref2 will be described. The state up to the reference delay time Dref1 after the input of the inverter 11 rises from the “L” level to the “H” level is the same as the state up to the delay time D in the case of D <Dref1.

Next, after the input of the inverter 11 rises from the "L" level to the "H" level, the reference delay time D
When ref1 elapses, the potential of the connection portion A of the reference delay circuit 2 rises from “L” level to “H” level, and the output of the inverter 31 falls from “H” level to “L” level. In this state, of the outputs of the NAND circuits 39 to 41, only the output of the NAND circuit 40 is at "L" level, and the other outputs are at "H" level.

Next, when the input of the inverter 11 rises from the "L" level to the "H" level and the delay time D or later, the output of the inverter 26 of the comparison delay circuit 3 changes from the "L" level to the "H" level. Rises, the output of the inverter 27 falls from the "H" level to the "L" level. As a result, the transfer gates 37 and 38 are both turned off and cut off, and the output of the inverter 31 is latched at the "L" level and the output of the inverter 33 is latched at the "H" level.

Therefore, after the reference delay time Dref1 has elapsed since the input of the inverter 11 rises from the "L" level to the "H" level, the NAND circuits 39 to 4
1, only the output of the NAND circuit 40 is at "L" level and the other outputs are at "H" level. Therefore, each output of the NOR circuits 56 and 58 in the delay adjustment circuit 5 is the first delay. Each of them becomes “L” level regardless of the output levels of the circuit 51 and the third delay circuit 53. On the other hand, the output of the NOR circuit 57 of the delay adjustment circuit 5 rises from the “L” level to the “H” level when the output of the second delay circuit 52 falls from the “H” level to the “L” level, and the NOR circuit 59 Falls from the "H" level to the "L" level. As described above, the signals input to the respective inputs of the first to third delay circuits are delayed using the second delay circuit 52.

Next, the case where D ≧ Dref2 will be described with reference to FIG. The input of the inverter 11 is "L"
The state from the rise to the “H” level to the reference delay time Dref1 is the same as the state up to the delay time D in the case of D <Dref1. In addition, from the time when the input of the inverter 11 rises from the “L” level to the “H” level until the reference delay time Dref2 has elapsed, the above-mentioned Dref1 ≦
This is the same as the state up to the delay time D when D <Dref2.

Next, after the input of the inverter 11 rises from the "L" level to the "H" level, the reference delay time D
When ref2 elapses, the potential of the connection portion B of the reference delay circuit 2 rises from “L” level to “H” level, and the output of the inverter 33 falls from “H” level to “L” level. In this state, of the outputs of the NAND circuits 39 to 41, only the output of the NAND circuit 41 is at "L" level, and the other outputs are at "H" level.

Next, after the input of the inverter 11 rises from the "L" level to the "H" level, the reference delay time D
Thereafter, the output of the inverter 26 of the comparison delay circuit 3 rises from the “L” level to the “H” level, and the output of the inverter 27 falls from the “H” level to the “L” level. As a result, the transfer gates 37 and 38 are both turned off and cut off, and the inverters 31 and 33 are turned off.
Are latched at the “L” level, respectively.

Accordingly, after the reference delay time Dref2 has elapsed since the input of the inverter 11 rises from the "L" level to the "H" level, the NAND circuits 39 to 4
1, only the output of the NAND circuit 41 is at "L" level and the other outputs are at "H" level. Therefore, each output of the NOR circuits 56 and 57 in the delay adjustment circuit 5 is the first delay. Each of them becomes “L” level regardless of the output level of the circuit 51 and the second delay circuit 52. On the other hand, the output of the NOR circuit 58 of the delay adjustment circuit 5 rises from the “L” level to the “H” level when the output of the third delay circuit 53 falls from the “H” level to the “L” level. Falls from the "H" level to the "L" level. Thus, the signals input to the respective inputs of the first to third delay circuits are delayed by using the third delay circuit 53 having the shortest delay time.

As described above, in the semiconductor device according to the first embodiment, the delay time D of the comparison delay circuit 3 varies due to process variations and the like, and the reference delay times Dref1 and Dref2 set in advance in the reference delay circuit 2 are different. Therefore, when the delay time D is D <Dref1, the signal is delayed by using the first delay circuit 51 having the longest delay time, and Dref1
If ≦ D <Dref2, the signal is delayed using the second delay circuit 52 having a shorter delay time than the first delay circuit 51, and D
In the case of ≧ Dref2, the signal is delayed using the third delay circuit 53 having the shortest delay time.

Thus, each resistor and capacitor of the reference delay circuit 2 set to the reference delay time are formed in a process-stable manner that is not affected by the transistor. Even when the delay changes, a constant delay time can be obtained by designing any one of the first to third delay circuits to have a desired delay time. Does not need to be adjusted, and the delay time in the delay circuit can be automatically adjusted when the power is turned on. Further, by forming the resistor and the capacitor forming the reference delay circuit 2 with the same wiring material as that actually used, it is possible to cope with the variation of the delay time with respect to the variation of the wiring material.

Embodiment 2 In the first embodiment, first to first
The operation of selecting the third delay circuit and adjusting the delay time is automatically performed every time the power is turned on.
The adjustment may be performed only once, and such adjustment is referred to as a second embodiment of the present invention. FIG. 5 is a circuit diagram showing an example of a semiconductor device according to the second embodiment of the present invention. In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 5, a semiconductor device 61 includes a reference delay circuit 2, a comparison delay circuit 3, and a delay time determination circuit 4.
A determination output circuit 62 for outputting a determination result of the delay time determination circuit 4 to an external device (not shown) in accordance with a predetermined signal input at power-on, and a determination output from the determination output circuit 62 A delay adjustment circuit 63 for adjusting the delay time from an external device according to the result.

The judgment output circuit 62 is formed by transfer gates 71 to 73 and an inverter 74. The transfer gate 71 includes a P-MOS 71a and an N-MOS
The transfer gate 72 is formed by connecting the input / output terminals 71b in parallel with each other.
The input / output terminals 72b are connected in parallel. Similarly, the transfer gate 73 is connected to the P-MOS 7
3a and the input / output terminals of the N-MOS 73b are connected in parallel.

In the decision output circuit 62, the P-MOS 7
The gates of 1a, 72a and 73a are connected to each other,
The connection is connected to the output of the inverter 74.
The gates of the N-MOSs 71b, 72b, and 73b are connected to each other, and the connection is connected to the input of the inverter 74, and is activated in a predetermined special operation mode to change from "L" level to "H" level. A changing signal is input.

In the transfer gate 71, one input / output terminal is connected to the NAND circuit 39 of the delay time judgment circuit 4.
And the other input / output terminal is connected to a pad 77 for connection to an external device. In the transfer gate 72, one input / output terminal is connected to the output of the NAND circuit 40 of the delay time determination circuit 4, and the other input / output terminal is connected to a pad 78 for connection to an external device. Also, the transfer gate 73
, One input / output terminal is connected to the output of the NAND circuit 41 of the delay time determination circuit 4, and the other input / output terminal is connected to a pad 79 for connection to an external device.

Next, the delay adjusting circuit 63 includes a first delay circuit 51, a second delay circuit 52, a third delay circuit 53, a delay time switching circuit 54, a first setting circuit 81, a second setting circuit 82, and a third The setting circuit 84 is formed. First setting circuit 8
1 is formed by a series circuit of a fuse 81a and a resistor 81b, and a connection portion between the fuse 81a and the resistor 81b is
The input of the NOR circuit 56 is connected via a fuse 81a to a power supply terminal Vdd to which a predetermined power supply voltage is applied from the outside, and is grounded via a resistor 81b. Have been.

The second setting circuit 82 is formed by a series circuit of a fuse 82a and a resistor 82b.
Is connected to one input of a NOR circuit 57. The input of the NOR circuit 57 is connected to a fuse 8b.
2a and a resistor 82
b is grounded. Similarly, the third setting circuit 83
Is formed by a series circuit of a fuse 83a and a resistor 83b, and the connection between the fuse 83a and the resistor 83b is N
The NOR circuit 5 is connected to one input of an OR circuit 58,
The input 8 is connected to a power supply terminal Vdd via a fuse 83a and grounded via a resistor 83b.

In such a configuration, at the time of manufacturing, power is turned on, the input of inverter 11 rises from the "L" level to the "H" level, and the output of each of NAND circuits 39 to 41 in delay time determination circuit 4 is output. Delay adjustment circuit 63 according to the determination result of the delay time output from
One of the fuses 81a to 83a is blown,
The signal is delayed by using any one of the first delay circuit 51, the second delay circuit 52, and the third delay circuit 53.

In the operation mode for performing the operation of adjusting the delay time in the semiconductor device 61, the judgment output circuit 6
2, the signal of the “H” level is input to the input of the inverter 74. The transfer gates 71 to 71
Numerals 73 are turned on to become conductive, the output potential of the NAND circuit 39 is supplied to the pad 77 via the transfer gate 71, the output potential of the NAND circuit 40 is supplied to the pad 78 via the transfer gate 72, and the output potential of the NAND circuit 41 is provided. Is a pad 79 through the transfer gate 73
Respectively.

An external device (not shown) includes pads 77 to 7
9, if the relationship between the delay time D of the comparison delay circuit 3 and the reference delay times Dref1 and Dref2 of the reference delay circuit 2 is D <Dref1, the fuse 8 of the first setting circuit 81
1a is set to the second setting circuit 82 when Dref1 ≦ D <Dref2.
If D ≧ Dref2, the fuse 82a of the third setting circuit 83 is blown.

In the delay adjustment circuit 63, the fuse 81
When a is blown, one input of the NOR circuit 56 is grounded via the resistor 81b, one input of the NOR circuit 57 is connected via the fuse 82a, and one input of the NOR circuit 58 is connected via the fuse 83a. A power supply potential is applied to each. From this, each output of the NOR circuits 57 and 58 is connected to the corresponding second delay circuit 52 and third delay circuit 5.
3 are at "L" level irrespective of the output level. On the other hand, the output of the NOR circuit 56 is
Falls from the "H" level to the "L" level, the output from the "L" level rises to the "H" level, and the output of the NOR circuit 59 falls from the "H" level to the "L" level.

Similarly, when the fuse 82a is blown,
One input of the NOR circuit 57 is grounded via a resistor 82b, one input of the NOR circuit 56 is a fuse 81a, and one input of the NOR circuit 58 is a fuse 83a.
The power supply potential is applied to each of them via the. From this, the output of the NOR circuit 57 rises from the “L” level to the “H” level when the output of the second delay circuit 52 falls from the “H” level to the “L” level, so that the NOR circuit 59 outputs The output falls from "H" level to "L" level.

Similarly, when the fuse 83a is blown,
One input of the NOR circuit 58 is grounded via a resistor 83b, one input of the NOR circuit 56 is a fuse 81a, and one input of the NOR circuit 57 is a fuse 82a.
The power supply potential is applied to each of them via the. From this, the output of the NOR circuit 58 rises from the “L” level to the “H” level when the output of the third delay circuit 53 falls from the “H” level to the “L” level. The output falls from "H" level to "L" level.

As described above, in the semiconductor device according to the second embodiment, the delay time D of the comparison delay circuit 3 varies due to process variations and the like, and the reference delay times Dref1 and Dref2 set in advance in the reference delay circuit 2 are different. Therefore, when the delay time D is D <Dref1, the signal is delayed by using the first delay circuit 51 having the longest delay time by blowing the fuse 81a by an external device, and Dref1 ≦ D <D
In the case of ref2, the fuse 82a is blown by an external device to delay the signal using the second delay circuit 52 having a shorter delay time than the first delay circuit 51. If D ≧ Dref2,
The signal is delayed using the third delay circuit 53 having the shortest delay time when the fuse 83a is blown by an external device.

From this, it is possible to obtain a desired delay time without being affected by process variations and the like, and it is not necessary to adjust the delay time every time the power is turned on. Can eliminate the variation in the circuit operation and obtain a stable delay time. Further, by forming the resistor and the capacitor forming the reference delay circuit 2 with the same wiring material as that actually used, it is possible to cope with the variation of the delay time with respect to the variation of the wiring material.

Embodiment 3 In the second embodiment, the variation in the delay time due to the variation in the process or the like is detected in the semiconductor device. However, the variation in the delay time due to the variation in the process or the like may be detected by an external device. Is the third embodiment of the present invention. FIG. 6 is a circuit diagram showing an example of a semiconductor device according to the third embodiment of the present invention. In FIG. 6, the same components as those in FIG. 5 are denoted by the same reference numerals, and description thereof is omitted here.

In FIG. 6, a semiconductor device 91 includes a delay circuit 92 and a delay adjusting circuit 63, which are delay circuits used to determine a variation in delay time due to a variation in a process. In the comparison delay circuit 92, eight inverters 101 to 108 are sequentially connected in series to form a delay circuit. The input of the inverter 101 serving as the input of the comparison delay circuit 92 is connected to an external device (not shown). The output of the inverter 108, which is the output of the comparison delay circuit 92, is connected to the pad 109 to which connection is made, and is connected to the pad 110, which is connected to an external device.

In such a configuration, the potential level of the pad 109 of the comparison delay circuit 92 is changed by an external device during manufacture, and the external device detects the change in the potential level of the pad 110 of the comparison delay circuit 92 due to this. Thus, the delay time D of the comparison delay circuit 92 is detected.
The external device determines that the relationship between the detected delay time D and the preset reference delay times Dref1 and Dref2 is D <Dre.
In the case of f1, the fuse 81a of the first delay circuit 81 is
If f1 ≦ D <Dref2, the fuse 8 of the second delay circuit 82
If D ≧ Dref2, the fuse 83a of the third delay circuit 83 is blown.

As described above, the semiconductor device according to the third embodiment can obtain the same effect as that of the second embodiment, and further, a circuit for determining a variation in delay time due to a variation in a process is provided in an external device. Therefore, the circuit can be simplified.

In the first and second embodiments, two preset reference delay times Dref1, Dref1,
Although the case where Dref2 is used has been described as an example, the present invention is not limited to this. If at least one reference delay time is used to determine the variation in the delay time due to the variation in the process or the like, Good. In addition, the number of inverters connected in series in the comparison delay circuit 3 in the first and second embodiments and the comparison delay circuit 92 in the third embodiment is an example, and the present invention is not limited to this. Absent.

[0061]

The semiconductor device according to the first aspect of the present invention determines a variation in delay time of the comparison delay circuit portion due to a process variation or the like based on a reference delay time preset in the reference delay circuit portion. One of the delay circuits of the delay adjustment circuit section is selected according to the result of the determination to delay a desired signal. Therefore, even when the delay of the transistor changes due to the variation due to the process or the like, the variation of the process can be improved by designing any one of the delay circuits in the delay adjustment circuit unit to have a desired delay time. Since the desired delay time can be obtained without being affected by the delay time, it is not necessary to externally adjust the delay time, and the delay time in the delay circuit can be automatically adjusted.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a reference delay time preset in a reference delay circuit;
A delay time variation of the comparison delay circuit unit due to a process variation or the like is determined, and one of the delay circuits of the delay adjustment circuit unit is selected by an external device according to the determination result to delay a desired signal. I did it. From this, even when the delay of the transistor changes due to the variation due to the process or the like, a certain delay time can be obtained by designing any one of the delay circuits in the delay adjustment circuit unit to have a desired delay time. Therefore, a desired delay time can be obtained without being affected by process variations and the like.

According to a third aspect of the present invention, in the semiconductor device according to any one of the first and second aspects, specifically, the comparison delay circuit section is constituted by a delay circuit whose delay time varies according to process variations. The delay circuit of the reference delay circuit set to the reference delay time is formed by using a resistor and a capacitor which are not affected by process variations and the like. From this, it is possible to accurately determine the variation in the delay time in the comparison delay circuit unit, and to form the resistor and the capacitor using the same wiring material as the actually used wiring material, so that the delay due to the variation in the wiring material is reduced. It is possible to cope with time variations.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the comparison delay circuit section and the reference delay circuit section each include a predetermined signal input at power-on. , Respectively. From this, it is possible to adjust the delay time in the delay circuit when the power is turned on.

According to a fifth aspect of the present invention, a signal input from an external device is delayed by a comparison delay circuit and output to the external device. Judge the variation of delay time,
One of the delay circuits of the delay adjustment circuit section is selected by an external device according to the result of the determination, and delays a desired signal. From this, even when the delay of the transistor changes due to the variation due to the process or the like, a certain delay time can be obtained by designing any one of the delay circuits in the delay adjustment circuit unit to have a desired delay time. Therefore, a desired delay time can be obtained without being affected by process variations and the like. Furthermore, since a circuit for determining a variation in delay time due to a variation in a process or the like is provided in an external device, the circuit can be simplified.

According to a sixth aspect of the present invention, in the semiconductor device according to any one of the second and fifth aspects, specifically, the fuse of the setting circuit in the delay adjustment circuit section is blown by an external device, and each of the delay circuits is One was fixed and selected. From this, it is necessary to adjust the delay time at the time of manufacture.
It can be performed only once, and variations in circuit operation due to changes in the surrounding state such as temperature changes can be eliminated, and a stable delay time can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing waveforms at various points in the semiconductor device 1 shown in FIG.

FIG. 3 is a timing chart showing waveforms at various points in the semiconductor device 1 shown in FIG.

FIG. 4 is a timing chart showing waveforms at various points in the semiconductor device 1 shown in FIG.

FIG. 5 is a circuit diagram showing an example of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing an example of a conventional delay circuit.

[Explanation of symbols]

1,61,91 semiconductor device, two-reference delay circuit,
3,92 comparison delay circuit, 4 delay time judgment circuit,
5,63 delay adjustment circuit, 51 first delay circuit, 5
2 2nd delay circuit, 53 3rd delay circuit, 54 delay time switching circuit, 62 judgment output circuit, 81 1st setting circuit, 82 2nd setting circuit, 3rd setting circuit.

Claims (6)

[Claims] 1. A semiconductor device provided with a delay circuit, comprising: a comparison delay circuit section including a delay circuit used to determine a variation in delay time; and at least one predetermined reference value serving as a reference value of the delay time. A reference delay circuit unit including a delay circuit set to a reference delay time; and a delay time determination circuit unit for determining a variation in delay time in the comparison delay circuit unit based on the reference delay time of the reference delay circuit unit And a plurality of delay circuits set to different delay times, and one of the delay circuits according to the determination result of the delay time determination circuit unit.
And a delay adjusting circuit unit for selecting one of them to delay a desired signal. 2. A semiconductor device provided with a delay circuit, comprising: a comparison delay circuit unit including a delay circuit used to determine a variation in delay time; and at least one predetermined delay time reference value. A reference delay circuit unit including a delay circuit set to a reference delay time; and a delay time determination circuit unit for determining a variation in delay time in the comparison delay circuit unit based on the reference delay time of the reference delay circuit unit A determination output circuit for outputting the determination result of the delay time determination circuit to an external device; and a plurality of delay circuits set to different delay times, according to the determination result output from the determination output circuit. A delay adjusting circuit for selecting one of the delay circuits by an external device and delaying a desired signal using the selected delay circuit. . 3. The comparison delay circuit section is configured by a delay circuit whose delay time varies according to a process variation.
The reference delay circuit section includes at least one delay circuit formed using a resistor and a capacitor that are not affected by process variations, and the delay circuit is set to the predetermined reference delay time in advance. The semiconductor device according to claim 1, wherein: 4. The comparison delay circuit section and the reference delay circuit section respectively delay a predetermined signal inputted at power-on, and the delay time determination circuit section includes a comparison delay circuit section and a reference delay circuit. 4. The semiconductor device according to claim 1, wherein a variation in delay time is determined from delay signals input from the respective units. 5. A semiconductor device provided with a delay circuit, comprising: a delay circuit used to determine a variation in delay time, wherein a signal input from an external device is delayed and output to the external device. A delay circuit unit, and a plurality of delay circuits set at different delay times, wherein one of the delay circuits is selected from an external device according to a variation in the delay time in the comparison delay circuit unit, and the selected delay circuit is selected. A semiconductor device, comprising: a delay adjustment circuit unit that delays a desired signal using a circuit. 6. The delay adjustment circuit section includes a setting circuit provided with a fuse for selecting one of the plurality of delay circuits, and one of the delay circuits is blown by an external device when the fuse is blown. 6. The semiconductor device according to claim 2, wherein one is fixedly selected.