KR100639201B1 - Titanium Silicide Formation Method of Semiconductor Device - Google Patents
Titanium Silicide Formation Method of Semiconductor Device Download PDFInfo
- Publication number
- KR100639201B1 KR100639201B1 KR1020000037123A KR20000037123A KR100639201B1 KR 100639201 B1 KR100639201 B1 KR 100639201B1 KR 1020000037123 A KR1020000037123 A KR 1020000037123A KR 20000037123 A KR20000037123 A KR 20000037123A KR 100639201 B1 KR100639201 B1 KR 100639201B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- titanium silicide
- semiconductor device
- thin film
- titanium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910021341 titanium silicide Inorganic materials 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 title claims 2
- 239000010409 thin film Substances 0.000 claims abstract description 18
- 239000010936 titanium Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- 238000010926 purge Methods 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 239000012495 reaction gas Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 229910008484 TiSi Inorganic materials 0.000 abstract description 11
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000003877 atomic layer epitaxy Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemical Vapour Deposition (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
반도체소자의 티타늄실리사이드 형성방법은, 실리콘기판과 금속간의 오믹(ohmic) 콘택 및 금속배선을 형성시키기 위한 티타늄실리사이드(TiSi2)의 형성방법에 관한 것이다.The method for forming titanium silicide of a semiconductor device relates to a method of forming titanium silicide (TiSi 2 ) for forming ohmic contacts and metal wiring between a silicon substrate and a metal.
본 형성방법은 기판 상부에 절연층을 형성하는 단계, 이 상부에 티타늄실리사이드박막을 형성하는 단계 및, 티타늄박막을 형성하는 단계를 포함하고 있다.The present method includes forming an insulating layer on the substrate, forming a titanium silicide thin film on the substrate, and forming a titanium thin film.
따라서 본 발명은 ALE 화학기상증착법에 따라 원하는 조성과 두께로 조절함으로써 금속배선을 위한 티타늄실리사이드를 형성하는 효과가 있다.Therefore, the present invention has the effect of forming titanium silicide for metal wiring by controlling to a desired composition and thickness according to the ALE chemical vapor deposition method.
Description
도 1a 내지 도 1c는 본 발명의 일실시예에 따른 반도체소자의 티타늄실리사이드 형성방법을 설명하기 위한 도면.1A to 1C illustrate a method of forming titanium silicide of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10 : 기판 12 : 절연층10
14 : TiSi2박막 16 : Ti박막14 TiSi 2
본 발명은 반도체 제조공정에 관한 것으로, 자세하게는 실리콘기판과 금속간의 오믹(ohmic) 콘택 및 금속배선을 형성시키기 위한, 반도체소자의 티타늄실리사이드 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing process, and more particularly, to a method for forming titanium silicide in a semiconductor device for forming ohmic contacts and metal wiring between a silicon substrate and a metal.
반도체소자의 제작에는 많은 콘택방법이 사용된다. 이러한 콘택은 완성된 반도체소자의 동작 전류 및 안정성 등에 관련된다. 따라서 보다 안정적이고 간단한 방법으로 콘택을 실시하기 위한 연구가 활발히 진행되고 있다. Many contact methods are used to fabricate semiconductor devices. This contact is related to the operating current and stability of the completed semiconductor device. Therefore, researches for conducting contacts in a more stable and simple manner have been actively conducted.
콘택을 실시함에 있어서, 종래에는 먼저 실리콘기판상에 이온주입방법에 의해 원하는 종류의 이온을 도핑한다. 이 후 적당한 두께의 티타늄(Ti)박막을 증착한다. 다음, RTP 방식으로 짧은 시간 동안 열처리를 수행하여 확산시킴으로써 티타늄실리사이드(이하 'TiSi2'라 함)에 의한 콘택을 형성하였다.In carrying out the contact, conventionally, a desired type of ions are first doped by an ion implantation method on a silicon substrate. After that, a titanium (Ti) thin film of a suitable thickness is deposited. Next, a contact by titanium silicide (hereinafter referred to as 'TiSi 2 ') was formed by diffusion by performing heat treatment for a short time in the RTP method.
그러나, 전술한 종래 RTP공정의 확산에 의한 콘택방법은 다음과 같은 문제점이 있다. 즉 RTP공정의 확산에 의해서는 정확한 두께조절이 어렵기 때문에 티타늄실리사이드(TiSi2)를 균일한 두께로 형성시키기 어렵다. 또한 RTP 공정시 티타늄(Ti)원소가 이온주입된 이온들과 반응을 일으키기도 한다. 이 때문에 콘택저항이 불안정하고 누설전류가 증가해 반도체소자의 전반적인 동작특성을 저해하는 문제점이 있다.However, the above-described contact method by the diffusion of the conventional RTP process has the following problems. That is, it is difficult to form a titanium silicide (TiSi 2 ) to a uniform thickness because it is difficult to precisely control the thickness by the diffusion of the RTP process. In addition, during the RTP process, titanium (Ti) elements react with the ions implanted. For this reason, there is a problem that the contact resistance is unstable and the leakage current increases, which hinders the overall operating characteristics of the semiconductor device.
따라서 전술한 문제점을 해결하기 위한 본 발명의 목적은, 티타늄실리사이드(TiSi2)를 ALE(Atomic Layer Epitaxy) 화학기상증착(CVD; Chemical Vapor Deposition) 방법에 따라 원하는 조성과 두께로 조절함으로써 금속배선 형성하기 위한, 반도체소자의 티타늄실리사이드 형성방법을 제공하는 데 있다.Accordingly, an object of the present invention for solving the above-described problems is to form a metal wiring by adjusting titanium silicide (TiSi 2 ) to a desired composition and thickness according to ALE (Atomic Layer Epitaxy) Chemical Vapor Deposition (CVD) method. The present invention provides a method for forming titanium silicide of a semiconductor device.
본 발명에 따른 반도체소자의 티타늄실리사이드 형성방법은, 반도체소자의 제조공정에 있어서, Titanium silicide forming method of a semiconductor device according to the present invention, in the manufacturing process of the semiconductor device,
도전층이 형성된 기판 상부에 절연층을 형성하고 상기 도전층이 노출되도록 패터닝하여 콘택홀을 형성하는 제1단계; 상기 절연층의 상부에 상기 콘택홀을 통해 상기 노출된 도전층과 접촉되게 티타늄실리사이드박막을 ALE CVD방법에 의해 형성하는 제2단계; 및, 상기 형성된 티타늄실리사이드 박막 상부에 티타늄박막을 형성하는 제3단계를 포함한다.Forming a contact hole by forming an insulating layer on the substrate on which the conductive layer is formed and patterning the conductive layer to expose the conductive layer; Forming a titanium silicide thin film by an ALE CVD method on the insulating layer to be in contact with the exposed conductive layer through the contact hole; And a third step of forming a titanium thin film on the formed titanium silicide thin film.
이하 도면들을 참조하여 본 발명의 바람직한 실시예를 자세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명의 일실시예에 따른 반도체소자의 티타늄실리사이드 형성방법을 설명하기 위한 도면이다.1A to 1C are diagrams for describing a method of forming titanium silicide of a semiconductor device according to an embodiment of the present invention.
본 발명은 반도체소자의 금속배선방법 중 종래의 물리기상증착법이나 화학기상증착법이 아닌 ALE CVD를 이용하여, 금속배선의 결함이 적고 두께 조절이 가능한 티타늄실리사이드(TiSi2) 형성방법에 관한 것이다. The present invention relates to a method for forming titanium silicide (TiSi 2 ) with less defects in metal wiring and controlling thickness by using ALE CVD rather than the conventional physical vapor deposition or chemical vapor deposition among the metal wiring methods of semiconductor devices.
도 1a에 도시한 바와 같이, 본 발명에 따른 일실시예는 먼저 금속배선을 형성하고자 하는 기판(10) 상부에 절연층(12)을 증착한다. 그리고 패턴 및 식각공정에 따라 콘택홀을 형성한다. As shown in FIG. 1A, an embodiment according to the present invention first deposits an
이후 도 1b와 같이, 이 상부에 TiSi2박막(14)을 형성하기 위한 공정을 실시한다. 이 공정은 먼저 ALE CVD방법의 순환소스공급방식에 따라 소스로 티타늄클로라이드(이하 'TiCl4'라 함)를 0.1∼1분간 10∼1000sccm의 유량만큼 한정적으로 공급하여 200∼700℃의 기판상에 흡착시킨다. 다음 아르곤(Ar)가스를 10∼1000sccm만큼 흘려 소스퍼지(source purge)를 0.1∼2분간 실시한다. 이 후 이미 흡착된 TiCl4 상부에 반응가스로 SiH4를 약 0.1∼1분 동안 10∼1000 sccm 정도 흘려 흡착시킴으로써 [화학식 1]과 같은 반응을 일으킨다.
Thereafter, as shown in FIG. 1B, a process for forming the TiSi 2
이 때 반응기의 압력은 0.1∼5 Torr 정도로 유지한다. 그 후 반응기체와 부산물 HCl에 아르곤(Ar)가스를 흘려 퍼지(purge) 시킨다. 그리고 위와 같은 과정을 5∼2000회 정도 반복하여, 10∼500Å두께의 TiSi2박막(14)을 형성한다.At this time, the pressure of the reactor is maintained at about 0.1 to 5 Torr. Thereafter, argon (Ar) gas is flowed into the reactor and by-product HCl to purge. Then, the above process is repeated about 5 to 2000 times to form a TiSi 2
이 후 도 1c와 같이, 형성된 TiSi2층(14) 상부에 Ti박막(16)을 형성한다. 이 공정에서는 반응가스로 SiH4대신 H2를 흘려준다. 이 경우에는 이미 형성된 TiSi2박막(14)표면에서 다시 TiCl4가 흡착되어 아래 [화학식 2]와 같은 반응을 일으킨다.Thereafter, as shown in FIG. 1C, the Ti
이러한 과정을 약 5∼2000회 반복하여 10∼600Å정도의 Ti박막(16)을 형성한다. 그리고 반복을 끝낸 후에는 반응기체와 부산물을 퍼지시킴으로써, 본 발명에 따른 반도체소자의 티타늄실리사이드 형성한다.This process is repeated about 5 to 2000 times to form a Ti
전술한 바와 같이, 본 발명은 ALE 화학기상증착법에 따라 원하는 조성과 두께로 조절함으로써 금속배선을 위한 티타늄실리사이드(TiSi2)를 형성하는 효과가 있다.As described above, the present invention has an effect of forming titanium silicide (TiSi 2 ) for metal wiring by controlling to a desired composition and thickness according to the ALE chemical vapor deposition method.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000037123A KR100639201B1 (en) | 2000-06-30 | 2000-06-30 | Titanium Silicide Formation Method of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000037123A KR100639201B1 (en) | 2000-06-30 | 2000-06-30 | Titanium Silicide Formation Method of Semiconductor Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020002812A KR20020002812A (en) | 2002-01-10 |
| KR100639201B1 true KR100639201B1 (en) | 2006-10-31 |
Family
ID=19675377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000037123A Expired - Fee Related KR100639201B1 (en) | 2000-06-30 | 2000-06-30 | Titanium Silicide Formation Method of Semiconductor Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100639201B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10062567B2 (en) | 2015-06-30 | 2018-08-28 | International Business Machines Corporation | Reducing autodoping of III-V semiconductors by atomic layer epitaxy (ALE) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100538806B1 (en) | 2003-02-21 | 2005-12-26 | 주식회사 하이닉스반도체 | SEMICONDUCTOR DEVICE WITH EPITAXIAL C49-TiSi2 LAYER AND METHOD FOR FABRICATING THE SAME |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05243179A (en) * | 1992-02-29 | 1993-09-21 | Sony Corp | Method of forming barrier metal layer of semiconductor device |
| JPH08186173A (en) * | 1994-12-28 | 1996-07-16 | Nec Corp | Manufacture of semiconductor device |
| KR19990015715A (en) * | 1997-08-08 | 1999-03-05 | 윤종용 | Metal wiring layer formation method |
| JP2000133617A (en) * | 1998-10-23 | 2000-05-12 | Oki Electric Ind Co Ltd | TiSi2 LAYER FORMATION AND MANUFACTURE OF SEMICONDUCTOR DEVICE PROVIDED WITH THE LAYER |
-
2000
- 2000-06-30 KR KR1020000037123A patent/KR100639201B1/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05243179A (en) * | 1992-02-29 | 1993-09-21 | Sony Corp | Method of forming barrier metal layer of semiconductor device |
| JPH08186173A (en) * | 1994-12-28 | 1996-07-16 | Nec Corp | Manufacture of semiconductor device |
| KR19990015715A (en) * | 1997-08-08 | 1999-03-05 | 윤종용 | Metal wiring layer formation method |
| JP2000133617A (en) * | 1998-10-23 | 2000-05-12 | Oki Electric Ind Co Ltd | TiSi2 LAYER FORMATION AND MANUFACTURE OF SEMICONDUCTOR DEVICE PROVIDED WITH THE LAYER |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10062567B2 (en) | 2015-06-30 | 2018-08-28 | International Business Machines Corporation | Reducing autodoping of III-V semiconductors by atomic layer epitaxy (ALE) |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020002812A (en) | 2002-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7521379B2 (en) | Deposition and densification process for titanium nitride barrier layers | |
| JP2001303251A (en) | Method of manufacturing barrier metal film using atomic layer deposition method | |
| KR100519376B1 (en) | Method for Forming Barrier Layer of Semiconductor Device | |
| US7358188B2 (en) | Method of forming conductive metal silicides by reaction of metal with silicon | |
| KR100477816B1 (en) | Method for forming titanium silicide contact of semiconductor device | |
| KR20220044601A (en) | Reduced line bending during metal filling process | |
| KR101628843B1 (en) | Method for forming ruthenium containing thin film by atomic layer deposition | |
| KR100447031B1 (en) | Method of forming tungsten silicide film | |
| US7411254B2 (en) | Semiconductor substrate | |
| US6602785B1 (en) | Method of forming a conductive contact on a substrate and method of processing a semiconductor substrate using an ozone treatment | |
| KR100639201B1 (en) | Titanium Silicide Formation Method of Semiconductor Device | |
| KR0161889B1 (en) | Formation method of wiring in semiconductor device | |
| KR100615602B1 (en) | Methods of forming a titanium nitride film having a smooth surface and methods of forming a semiconductor device using the same | |
| KR100609049B1 (en) | Metal wiring formation method of semiconductor device | |
| KR20010007527A (en) | Method of silicide formation in a semiconductor device and processor readable storage medium using the same | |
| JP3801923B2 (en) | Method for forming tungsten silicide | |
| KR100248145B1 (en) | Process for forming metal wire of semiconductor device | |
| KR100513810B1 (en) | FORMING METHOD OF Ti LAYER USING ATOMIC LAYER DEPOSITION BY CATALYST | |
| KR100268791B1 (en) | Metal wiring formation method of semiconductor device | |
| KR20040051700A (en) | Method for forming metal line of semiconductor device | |
| KR20080057086A (en) | Method for manufacturing bit line of semiconductor device | |
| KR100524921B1 (en) | Manufacturing method of barrier layer for semiconductor device | |
| KR100273716B1 (en) | Manufacturing method of semiconductor device | |
| TW202447723A (en) | Formation of silicon-and-metal-containing materials for hardmask applications | |
| TW202503092A (en) | Formation of silicon-and-metal-containing materials for hardmask applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20000630 |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20050308 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 20000630 Comment text: Patent Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20060426 Patent event code: PE09021S01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20060926 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20061020 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20061023 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20090922 Start annual number: 4 End annual number: 4 |
|
| FPAY | Annual fee payment |
Payment date: 20100920 Year of fee payment: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20100920 Start annual number: 5 End annual number: 5 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |