KR100613305B1 - Synchronization code sorting method and device for 1-bit serial communication - Google Patents

Abstract

The present invention provides a method and apparatus capable of detecting valid data after head information by accurately selecting a sync code at any time even when the transmitter transmits data at any point in time. That is, the present invention accurately selects the sync code by effectively using the logical state of the transmitted serial data, the start bit included in the serial data, and the sync code. In other words, according to the synchronization code screening method and apparatus of the present invention, first, the time of change of the serial data logic state is detected. Then, when a change point of the logic state is detected, the logic state of the start bit and the sync code is compared with the preset data value. Finally, if the logical state of the start bit and the sync code is the same as the preset data value, the data transmitted after the head information is recognized and received.

Transceiver, serial data, head information, sync code selection, sampling

Description

Method and apparatus for synchronization code assortment in 1bit serial transmission}

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram illustrating a prior art sync code sorting method capable of sorting sync codes.

2 illustrates a prior art method in which synchronization code selection is not possible.

3 is a view for explaining the concept of the present invention for selecting a synchronization code according to the present invention.

4 illustrates a data receiving device comprising a sync code check device in accordance with the present invention.

5 is a view for explaining a synchronization code screening method of the present invention.

6 is a diagram illustrating a transmission and reception system employing the synchronization code screening method of the present invention.

7 is a waveform diagram provided according to the method and apparatus for synchronizing code selection according to the present invention when the operation clock is 20 MHz.

8 is a waveform diagram provided according to a method and apparatus for synchronizing code selection according to the present invention when an operation clock is 60 MHz;

* Description of the symbols for the main parts of the drawings *

210: Start bit 220: Synchronization code

410: sync code check device 420: multiplexer

430 to 460: flip-flop 470: delay element

According to the present invention, when a transmitter and a receiver that transmit data using only one bit data operate as separate systems or use different clocks, the transmitted serial data may be transmitted even if the phases of the operation clocks used by the transmitter and the receiver are different from each other. The present invention relates to a synchronization code sorting method and apparatus implemented to enable stable transmission of data between a transmitting and receiving unit by accurately sorting sync codes included in head information.

As is known, the serial data transmitted from the transmitter is determined by the receiver according to whether or not the sync code included in the head information of the data is selected. In general, in the prior art sync code screening method, the presence or absence of a sync code is determined by comparing states of logic values of serial data transmitted at a rising edge of a clock using a hardware operating clock used in a receiver. . In other words, in a system in which the transmitter and the receiver are separate, the logic values of the serial data can be determined when the hardware operation clocks have the same phase. However, when the hardware operation clocks are different from each other, the logic values of the data can be determined. Since it is impossible to determine the synchronization code included in the head information of the transmitted serial data, it is impossible to accurately select the data, which causes the problem of not recognizing the data transmitted following the head information.

1 is a view for explaining an example of a conventional method of selecting a sync code. In FIG. 1, serial data is 1-bit serial data transmitted from a transmitter to a receiver, a start bit 110 is a bit indicating the start of a data field, and the sync code 120 is serial. The fixed 3 bits included in the head information of the data, the clock is a hardware operation clock used in the receiver, the A 130 and B 140 is a serial received at a certain point of time based on the hardware operation clock in the receiver The logical value state of the data.

In more detail, FIG. 1 illustrates a logic value of serial data received at a certain point in time using a hardware operation clock used in a receiver using a prior art. In Fig. 1, since the logic values of the serial data transmitted at the rising edges of the clocks at the A and B time points are the same as '1', the synchronization code is selected to determine that the subsequent signal is a meaningful signal, that is, data. Can be.

FIG. 2 illustrates a logic value of serial data received at a certain point in time using a hardware operation clock used in a receiver using the prior art as shown in FIG. 1. In the case of FIG. 2, the viewpoints of A 130 and B 140 for determining a logic value are the same as those of FIG. 1, but the viewpoints of the transmitted 1-bit serial data are different from each other. It is recognized as '1' in different states. Therefore, in this case, the transmitter transmits serial data, but the receiver fails to select a sync code, which causes a problem of not recognizing the data transmitted after the sync code.

Accordingly, in order to solve such a problem of the related art, an improved method or apparatus for accurately selecting a sync code even when an operation clock used in a transmitter and a receiver is changed and different from each other is required.

It is therefore an object of the present invention to provide a method and apparatus capable of effectively selecting a sync code based on transmitted serial data, a start bit included in the serial data, and a logic state of a sync code.

Another object of the present invention is to provide a method for enabling accurate data transmission by effectively selecting a sync code based on the transmitted serial data, a start bit included in the serial data, and a logic state of a sync code.

According to an aspect of the present invention, the synchronization code is selected from serial data transmitted from a transmitter, the serial data including head information comprising a start bit and a synchronization code. A synchronization code selection method for performing the above, (a) detecting a time point at which the logic state of the serial data is changed; (b) if a time point at which the logic state of the serial data is changed is detected at the step (a), Comparing the logic state of the start bit with a first preset data value based on the detected time point, (c) comparing the sync code with a second preset data value, and (d) Recognizing and receiving data transmitted after the head information when the logic state of the sync code is equal to the first and second predetermined data values, the steps (a) to (d ) ) Is provided with a sync code sorting method embedded in a software program in a receiver connected to the transmitter via a line for data transmission and reception.

According to another feature of the present invention, the synchronization code is selected from serial data transmitted from a transmitter, the serial data including head information comprising a start bit and a synchronization code. A sync code sorting apparatus, comprising: flip-flop means for storing and outputting said serial data for a predetermined time, and serial data output from said flip-flop means, and start bits and sync codes included in said serial data; There is provided a synchronization code selection device including a synchronization code check device for comparing a logic state with a preset data value and recognizing data transmitted after the synchronization code if the comparison results are the same.

According to still another aspect of the present invention, in a data receiving device using the sync code screening method, a sync code check device incorporating the sync code screening method, a multiplexer for multiplexing the serial data when the sync code is screened out, A flip-flop means connected between the sync code check device and the multiplexer and storing the serial data for a preset time and then providing the sync code check device to the sync code check device, and a multiple time connected to the multiplexer. Provided is a data receiving device including a delay element for delaying and outputting a delay.

In order to achieve the above object, in the present invention, when the transmitter and the receiver operate as separate systems for transmitting and receiving data using only 1-bit data, the receiver always transmits a synchronization code at any point in time. The present invention provides a method and an apparatus capable of detecting valid data after head information by accurately selecting.

Now, the synchronization code screening method according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a conceptual diagram for explaining a method according to the present invention, in which a receiver always detects valid data after the head information by accurately selecting a sync code even when the transmitter transmits data at any point in time. According to the present invention, as in the prior art, the logic code of the serial data is first selected without using the state of the logic value of the serial data received at a certain time with respect to the rising edge of the clock. A time point 310 for changing from '0' to '1' is detected. This detected time point is used as a time point to select a sync code. That is, in the sync code detecting method of the present invention, when the value of the serial data is changed from '0' to '1', the start bit is selected in the Temp01 320 section based on the selection time detected after a predetermined time. Whether the value of the data corresponding to the first code is the first preset data value, for example, “0” and the data corresponding to the sync code in the intervals Temp02 (330), Temp03 (340), and Temp04 (350). Check if the set data value is “010”, for example. If all of the above conditions are true, the data transmitted after the head information ("0010") of the serial data are interpreted as data transmitted by the transmitter.

Hereinafter, the synchronization code screening method according to the present invention will be described in detail with reference to FIGS. 4 to 6 based on the concept of the present invention described above with reference to FIG.

4 illustrates a data receiving device including a sync code check device of the present invention. As shown, a data receiving device having a sync code check device of the present invention is a sync code check (sync_code_check) device 410, a multiplexer 420, each of which can accommodate 24 bits of data. Three groups of flip-flops 430-460, and a delay element 470. Referring to FIG. 6 before describing the present invention in detail with reference to FIG. 4, a transmission / reception system employing the method and apparatus for synchronizing code according to the present invention and a data receiving device is exemplarily illustrated. As shown, such a transmission and reception system includes a servo motor having a transmitter and a servo driver having a controller and a power unit. For example, the data receiving device of the present invention shown in FIG. 4 may be embedded in a control unit of a control unit of a servo drive included in the transmission / reception system of FIG. 6. In a preferred embodiment of the present invention, the transmitter shown in Fig. 6 is an encoder having information on the operation of the servo motor, and the transmission speed of the serial data provided from the transmitter to the receiver is 2.5 Mbps.

Referring back to FIG. 4, the sync code check device 410 of the present invention has four flip-flops 430, 440, 450, and 460 configured as 24 bits when the hardware operation clock of the receiver shown in FIG. 6 is 60 MHz. The synchronization code can be selected by comparing the output data state of FIG. 4 (the data state provided through the solid line between the four flip-flops 430-460 and the sync code check device 410 of FIG. 4). When the operating clock is 20 MHz, a point between the output data states of the two flip-flops 430 and 440 composed of four 8-bit groups (two flip-flops 430-440 in FIG. 4) and the sync code check device 410 is shown. The synchronization code can be selected by comparing the data state provided through the broken line. Specifically, all four groups (430-460) of 24-bit flip-flops are used for 60 MHz operation, and the first 24-bit flip out of four of the 24-bit flip flops configured for 60 MHz at 20 MHz. Only the lower 8 bits of the flop 430 and the second 24-bit flip-flop 440 are used. Therefore, since the group of flip-flops at 60 MHz and the group of flip-flops at 20 MHz need not be configured differently, the configuration of the hardware and the implementation of the control algorithm are simple and efficient. In a preferred embodiment of the present invention, the hardware operation clock used in the receiver is divided by an external 'clk_select' port. For example, when 'clk_select' is '0', the hardware operation clock used at the receiver selects a synchronization code of serial data transmitted from the transmitter based on 20 MHz. In addition, when 'clk_select' is '1', the hardware operation clock used in the receiver may select a synchronization code of serial data transmitted from the transmitter based on 60 MHz. According to a preferred embodiment of the present invention, the default value of "clk_select" is set to "1", that is, the operation clock is 60 MHz for convenience, and this value is previously provided by the upper processor in the receiver shown in FIG. Details of the sync code screening apparatus and data receiving device of the present invention illustrated in FIG. 4 will be described later with reference to FIGS. 7 and 8.

Although the concept of the present invention has been schematically described with reference to FIG. 3, the sync code check device 410 of the present invention shown in FIG. 4 will be described in more detail below with reference to FIG. 5. The synchronization code check device 410 of the present invention has a software algorithm as shown in FIG. 5 and is implemented to operate under the control of the control unit shown in FIG. 6 prior to the reception of the first serial data. In detail, first, a point in time at which the logic state of the serial data received in step 410a is changed, that is, a point in time at which the logic state of the serial data is changed from “0” to “1” is detected. If a change in the logic state of the serial data is detected in step 410a, then in step 410b, the start bit (temp01 320 section of FIG. 3) included in the head information of the serial data is detected based on the detected time point. Value] and the first preset data value, that is, "0". After checking the start bit, in step 410c, a three-bit sync code (data values in the intervals of Temp02 330, Temp03 340, and Temp04 (350) in FIG. 3) and the second predetermined data value, i.e. Compare "010". In the final step 410d, if the result is satisfied through all the comparisons as described above, that is, the first bit having the start bit and the sync code included in the head information of the transmitted serial data is present in the sync code check device 410 itself. And the second predetermined data value, ie, "0010", the process of the present invention recognizes the data transmitted after the head information and transfers it to the next device. This process is performed upon receipt of the original data, and once the data is received, such sync code selection process is no longer performed.

When a sync code is selected according to the present invention, the sync code check device 410 provides corresponding information to the multiplexer 420. In response to this information, the multiplexer 420 provides the received serial data to the delay element 470, which is then sampled through the delay element 470 to an intermediate portion of the data excluding the noise component. The internal serial data (internal_serial_data) is transmitted to the next processor, for example, the control unit shown in FIG.

7 and 8 are waveform diagrams provided according to the sync code selection method and apparatus of the present invention for the case where the hardware operation clocks of the receiver are 20 MHz and 60 MHz, respectively. In detail, in FIG. 7 and FIG. 8, clk represents an operation clock of a receiver and rstb represents a reset signal. In the preferred embodiment of the present invention, the sync code sorting apparatus and the data transmitting / receiving device of the present invention shown in Fig. 4 are implemented to be operated when the reset signal is "1". In FIG. 7 and FIG. 8, serial_data represents serial data. As shown in FIG. 7, when clk_choice is “0”, the operation clock is 20 MHz, and when “1” is 60 MHz as in FIG. 8. . 7 and 8, the pulse portions 500, 503 of sync_high_edge indicate the time points at which the logic state of the serial data is changed from "0" to "1", respectively. In addition, in FIGS. 7 and 8, Temp01-Temp04 represents a data state output from flip-flops 430-460 of FIG. 4.

In detail, in FIG. 7, when the operation clock is 20 MHz, as described above, two flip-flops 430-440 are used, so that the data state values of Temp01 and Temp02 are “010 (00FF00)” in Temp01, In Temp02, it becomes “0 (only output 00 because 03FF00 uses only the lower 8 bits)”. Therefore, a data state value of "0010" can be obtained from Tem01-Temp02. In FIG. 8, when the operation clock is 60 MHz, as described above, all four flip-flops (430-460) are used, so that the data state values of Temp01-Temp04 are “0 (000000)” in Temp01 and “02”. 1 (FFFFFF) ”,“ 0 (000000) ”in Temp03, and“ 0 (000000) ”in Temp04. Therefore, a data state value of "0010" can be obtained from Temp01-Temp04.

In Figs. 7 and 8, internal_serial_data is data output from the delay element 470 as described above with reference to Fig. 4, and a synchronization code is obtained from the data state values of Temp01-Temp04 provided from flip-flops 430-460. It can be seen that the screen is output after a predetermined time, that is, after the cursor portions 501 and 504.

According to the present invention, since the synchronization code for serial data communication can be accurately selected, the transmission / reception unit enables stable data communication using only 1 bit data. In the prior art method, the hardware operation clock used in the receiver is used to compare the state of the serial data logic values transmitted at the rising edge of the clock to determine whether the synchronization code is selected. In the prior art, when the hardware operating clocks have the same phase as separate systems of the transmitter and the receiver, the serial data logic values can be determined. However, when the hardware operating clocks have different phases, the logic values can be determined. And the synchronization code contained in the head information of the serial data to be transmitted cannot be accurately selected, which causes a problem of not recognizing the transmitted data. However, in the method and apparatus of the present invention, when the transmitter and the receiver operate as separate systems, the hardware operation is performed by utilizing the logical state of the start bit and the sync code included in the transmitted serial data and the head information of the serial data. Even if the clock phases are different from each other, the synchronization code can be accurately selected, so that the transceiver can be used for stable data communication using only one bit of data. In addition, the 'clk_select' port can accurately select the sync code included in the head of the serial data transmitted from the transmitter even if the hardware operation clock of the receiver is changed by the user.

While the present invention has been described and illustrated by way of preferred embodiments, those skilled in the art will recognize that various modifications and changes can be made without departing from the spirit and scope of the appended claims.

Claims (12)

In the synchronization code screening method for screening the sync code from the serial data transmitted from the transmitter, the serial data includes head information consisting of a start bit and a synchronization code , (a) detecting a time point at which a logic state of the serial data is changed; (b) comparing the logic state of the start bit with a first preset data value based on the detected time point, if a change time of the logic state of the serial data is detected in step (a); (c) comparing the sync code with a second predetermined data value, and (d) if the logical state of the start bit and the sync code is equal to the first and second preset data values, recognizing and receiving data transmitted after the head information; And the steps (a) to (d) are implemented as a software program in a receiver connected to the transmitter via a line for data transmission and reception. The method of claim 1, wherein the step (a) detects a time point at which the logic state of the serial data is changed from "0" to "1". 2. The method of claim 1, wherein the first and second predetermined data values are "0" and "010", respectively. The method of claim 1, wherein step (a) is performed based on an operation clock used in the receiver, and the operation clock is 20 MHz or 60 MHz. In the sync code sorting apparatus for sorting the sync code from the serial data transmitted from the transmitter, the serial data includes head information consisting of a start bit and a synchronization code , Flip-flop means for storing and outputting the serial data for a preset time; and The serial data output from the flip-flop means and the logical state of the start bit and the sync code included in the serial data are compared with a preset data value. If the comparison result is the same, the data transmitted after the sync code is recognized. A sync code sorting apparatus comprising a sync code checking device. The device of claim 5, wherein the sync code check device comprises: Detecting a time point at which the logic state of the serial data is changed, When a time point of change of the logic state of the serial data is detected, the logic state of the start bit is compared with the first preset data value based on the detected time point, Comparing the sync code with a second preset data value, And recognizing data transmitted after the head information if the logical state of the start bit and the sync code is equal to the first and second predetermined data values. 7. The sync code sorting apparatus according to claim 6, wherein the sync code check device detects a time point at which the logic state of the serial data is changed from "0" to "1". 7. The sync code sorting apparatus according to claim 6, wherein the first and second preset data values are "0" and "010", respectively. The apparatus of claim 5, wherein the sync code check device is performed based on an operation clock of 20 MHz or 60 MHz. A data receiving device using the synchronization code sorting method according to claim 1, A sync code check device incorporating the sync code sorting method; Multiplexer means for multiplexing the serial data when the sync code is selected; Flip-flop means connected between the sync code check device and the multiplexer and storing the serial data for a predetermined time and then providing the sync data to the sync code check device; A delay element connected to the multiplexer and outputting the serial data by delaying the serial data for a predetermined time. Data receiving device comprising a. 11. A data receiving device according to claim 10, wherein said flip-flop means consists of a plurality of flip-flops, each flip-flop capable of storing 24-bit data. 12. The apparatus of claim 11, wherein the sync code check device is performed based on a 20MHz or 60MHz operating clock used in the receiving unit, and when the operating clock is 60MHz, all of the plurality of flip-flops are used. The data receiving device uses only a part of the plurality of flip-flops when the clock is 20MHz.

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