KR100531537B1 - Method for fabricating of semiconductor device - Google Patents

Abstract

The present invention is to provide a method of manufacturing a semiconductor device that can improve the current driving capability of the device, reduce the amount of leakage current, improve the short channel effect and punch-through characteristics, according to one aspect of the invention, the substrate Stacking a gate insulating film and a gate electrode on the substrate; Forming first and second sidewall insulating layers on both sides of the gate electrode; Forming a buffer insulating film and a photoresist film on the substrate to expose the upper surface of the gate electrode; Doping by implanting impurity ions into the gate electrode; Removing the photosensitive film; And forming a source / drain region in the gate electrode and the substrate on both sides of the first and second sidewall insulating layers.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a transistor manufacturing process in a semiconductor device manufacturing process, and more particularly, to improve current driving capability, reduce leakage current amount, and improve short channel effect and punchthrough characteristics. The present invention relates to a method of manufacturing a transistor.

Referring to the accompanying drawings, a method of manufacturing a semiconductor device according to the prior art will be described.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

In the conventional method of manufacturing a semiconductor device, as shown in FIG. 1A, the first insulating film and the polysilicon layer are sequentially deposited on the semiconductor substrate 100, and then the polysilicon layer and the first insulating film are formed using a gate forming mask. Is etched to form a gate insulating film 101 and a gate electrode 102 in one region.

Thereafter, low concentration source / drain regions 103a and 103b are formed in the semiconductor substrate 100 using the gate electrode 102 as a mask.

Next, a second insulating film and a third insulating film are sequentially deposited on the entire surface of the semiconductor substrate 100 including the gate electrode 102, and then etched back to form first and second sidewall insulating films 104 and 105 on both sides of the gate electrode 102. ).

In this case, the first sidewall insulating film 104 is formed at an angle between the gate electrode 102 and the second sidewall insulating film 105 and under the second sidewall insulating film 105.

As shown in FIG. 1B, a buffer insulating film 106 is deposited to have a thickness of about 100 μs on the entire surface including the gate electrode 102 and the first and second sidewall insulating films 104 and 105.

Thereafter, high concentration impurity ions are implanted into the semiconductor substrate 100 on both sides of the gate electrode 102 and the first and second sidewall insulating films 104 and 105. At this time, not only the semiconductor substrate 100 but also the gate electrode 102 is simultaneously implanted with ions.

As shown in FIG. 1C, a subsequent rapid thermal process (RTP) process is performed to form a high concentration source / drain in the semiconductor substrate 100 on both sides of the gate electrode 102 and the first and second sidewall insulating films 104 and 105. The regions 107a / 107b are formed.

As described above, when the high concentration impurity ions are implanted to form the high concentration source / drain regions 107a and 107b, ions are simultaneously implanted into the gate electrode 102. As in the above process, the ion implantation of the gate electrode 102 is entirely determined by the ion implantation conditions of the high concentration source / drain regions 107a / 107b.

However, when the gate electrode is implanted under the same conditions as the ion implantation conditions of the source / drain regions, the gate electrode may not function as a material that is sufficiently electrically conductive due to the thickness of the gate electrode and the poly grain structure. Can cause problems.

As described above, if the gate electrode is not sufficiently doped, the depletion layer region is generated by the voltage applied to the gate electrode, thereby increasing the thickness of the electrical gate-oxide film, thereby lowering the current driving capability of the MOS transistor, and in the off state. A problem arises in that the leakage current increases.

In other words, in the situation where the source / drain regions of the MOS transistors gradually become shallower as a device for miniaturization and preventing short channel effects, the gate electrode is no longer the same as the source / drain regions. At the same time, the ion implantation method has reached its limit.

The present invention has been proposed to solve the problems of the prior art as described above, the method of manufacturing a semiconductor device that can improve the current driving capability of the device, reduce the amount of leakage current, improve the short channel effect and punch-through characteristics The purpose is to provide.

According to an aspect of the present invention for achieving the above technical problem, forming a gate insulating film and a gate electrode stacked on a substrate; Forming first and second sidewall insulating layers on both sides of the gate electrode; Forming a buffer insulating film and a photoresist film on the substrate to expose the upper surface of the gate electrode; Doping by implanting impurity ions into the gate electrode; Removing the photosensitive film; And forming a source / drain region in the gate electrode and the substrate on both sides of the first and second sidewall insulating layers.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, as shown in FIG. 2A, a first insulating film and a polysilicon layer are sequentially deposited on the semiconductor substrate 200, and then a polysilicon layer is formed using a gate formation mask. The insulating film is etched and the gate insulating film 201 and the gate electrode 202 are stacked in one region.

Thereafter, low concentration source / drain regions 203a / 203b are formed in the semiconductor substrate 200 using the gate electrode 202 as a mask.

Next, a second insulating film and a third insulating film are sequentially deposited on the entire surface of the semiconductor substrate 200 including the gate electrode 202. Then, the third insulating film is etched back so that the second insulating film is exposed, and then the gate electrode ( The second insulating film is etched back so that the surface of the metal plate 202 is exposed to form first and second sidewall insulating films 204 and 205 on both sides of the gate electrode 202.

In this case, the first sidewall insulating layer 204 is formed at an angle between the gate electrode 202 and the second sidewall insulating layer 205 and under the second sidewall insulating layer 205.

Next, a buffer insulating film 206 is deposited on the entire surface including the gate electrode 202 and the first and second sidewall insulating films 204 and 205 to have a thickness of about 100 μs.

As shown in FIG. 2B, a photosensitive film 207 is applied onto the buffer insulating film 206, and the photosensitive film 207 is patterned by an exposure and development process so that the buffer insulating film 206 on the gate electrode 202 is exposed. .

Subsequently, the surface of the gate electrode 202 is exposed by etching back the buffer insulating film 206 using the patterned photoresist 207 as a mask.

Next, ions are implanted into the gate electrode 202 using the photoresist 207 as a mask to dope only the gate electrode 202.

As shown in FIG. 2C, the photosensitive film 207 is removed and high concentration impurity ions are implanted into the semiconductor substrate 200 on both sides of the gate electrode 202 and the first and second sidewall insulating films 204 and 205. At this time, ions are simultaneously implanted into the gate electrode 202 as well as the semiconductor substrate 200.

Subsequently, as shown in FIG. 2D, a subsequent rapid thermal process (RTP) is performed to obtain a high concentration source / concentration in the semiconductor substrate 200 on both sides of the gate electrode 202 and the first and second sidewall insulating films 204 and 205. Drain regions 208a / 208b are formed.

When the gate electrode 202 is doped in the same manner as described above, ion implantation energy and concentration may be independently set without affecting the source / drain regions. Therefore, it is possible to prevent deterioration of device characteristics, in particular, occurrence of a short channel phenomenon.

In other words, as the device is integrated, the ion implantation conditions of the gate electrode 202 and the source / drain regions need to be set differently (especially, the doping of the gate electrode needs to be high) for smooth operation of the device. When the photoresist 207 is patterned to expose only the top surface of the electrode 202 and the gate insulating film 206 is etched after the buffer insulating film 206 is etched back, the source / drain regions directly affecting device characteristics are not affected. The gate electrode 202 can be sufficiently doped independently.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The method of manufacturing the semiconductor device of the present invention described above has the following effects.

First, since the gate electrode can be sufficiently doped, the current driving capability of the semiconductor device can be improved and leakage current can be prevented at the same time.

Second, since the gate electrode can be independently doped without affecting the source / drain regions at all, the deterioration of device characteristics, in particular, the short channel effect and punchthrough characteristics can be improved.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

200: semiconductor substrate 201: gate insulating film

202: gate electrode 203a / 203b: low concentration source / drain region

204: first sidewall insulating film 205: second sidewall insulating film

206: buffer insulating film 207: photosensitive film

208a / 208b: high concentration source / drain area

Claims (4)

Stacking a gate insulating film and a gate electrode on the substrate; Forming first and second sidewall insulating layers on both sides of the gate electrode; Forming a buffer insulating film and a photoresist film on the substrate to expose the upper surface of the gate electrode; Doping by implanting impurity ions into the exposed gate electrode; Removing the photosensitive film; And Forming a source / drain region in the substrate on both sides of the gate electrode and the first and second sidewall insulating layers Method of manufacturing a semiconductor device comprising a. The method of claim 1, The formation of the first and second sidewall insulating films may include sequentially depositing first and second insulating films on the entire surface of the substrate including the gate electrode; Etching back the second insulating film to expose the first insulating film; And etching back the first insulating film to expose the surface of the gate electrode. The method of claim 1, And forming a low concentration source / drain region in the surface of the substrate after the gate electrode is formed. The method of claim 1, Forming the buffer insulating film and the photosensitive film so that the upper surface of the gate electrode is exposed, Exposing and developing the photosensitive film so as to expose the buffer insulating film over the gate electrode; And etching back the buffer insulating layer using the patterned photoresist as a mask to expose the upper surface of the gate electrode.