KR100523625B1 - Method for formating imd in semiconductor - Google Patents
Method for formating imd in semiconductor Download PDFInfo
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- KR100523625B1 KR100523625B1 KR10-2003-0048736A KR20030048736A KR100523625B1 KR 100523625 B1 KR100523625 B1 KR 100523625B1 KR 20030048736 A KR20030048736 A KR 20030048736A KR 100523625 B1 KR100523625 B1 KR 100523625B1
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- 238000000034 method Methods 0.000 title claims description 20
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 14
- 239000011800 void material Substances 0.000 claims abstract description 7
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 239000010949 copper Substances 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 HDP로 메탈과 메탈 사이를 좁게 만든 후, PECVD을 이용하여 보이드를 형성하여 알루미늄 디바이스에서 RC 딜레이를 최소화하기 위한 것으로, 이를 위한 작용은 메탈이 증착된 웨이퍼 상에 PR를 도포하고, 감광하여 마스크 패턴을 형성하는 단계와, 메탈 마스크 패턴을 형성한 후, HDP를 이용하여 라이너 산화막을 형성하는 단계와, 형성된 라이너 산화막에 대하여 건식 식각을 수행하여 메탈 상부의 HDP 산화막을 제거하고, 메탈 측벽의 상부를 라운딩하여 하부 HDP 산화막이 일부 제거되어 갭 필을 어렵게 하는 단계와, 메탈 상부의 HDP 산화막이 제거된 상태에서, PECVD를 이용하여 캡 산화막을 증착하여 보이드를 형성시킨 후, 캡 산화막을 CMP하여 평탄화하는 단계를 포함한다. 따라서, 로우 k 재료에 의해 전기적 특성이 열악하고, 후속 구리 CMP 시 기계적으로 잘 견디지 못하게 되는 결점을 해결할 수 있는 효과가 있다. The present invention is to minimize the RC delay in the aluminum device by forming a void by using PECVD, and then to narrow the metal and the metal by HDP, the action for this is to apply a PR on the metal-deposited wafer, the photosensitive Forming a mask pattern; forming a metal mask pattern; forming a liner oxide film using HDP; and performing dry etching on the formed liner oxide film to remove the HDP oxide film on the metal and removing the metal sidewalls. Rounding the upper portion of the lower HDP oxide to remove gaps to make the gap fill difficult, and in the state where the upper HDP oxide is removed from the metal, the cap oxide is deposited by PECVD to form voids, and then the cap oxide is CMP. To planarize. Therefore, there is an effect that can solve the drawback that the low k material is poor in electrical characteristics, and mechanically poor at subsequent copper CMP.
Description
본 발명은 반도체의 아이엠디(inter metal dielectric, IMD) 형성방법에 관한 것으로, 특히, HDP로 메탈과 메탈 사이를 좁게 만든 후, 플라즈마 화학 기상 증착(Plasma Enhanced Chemical Vapor Deposition, PECVD)을 이용하여 보이드(void)를 형성하여 알루미늄(Al) 디바이스에서 RC 딜레이(delay)를 최소화하도록 하는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an intermetal dielectric (IMD) of a semiconductor, and in particular, after narrowing a metal to a metal by HDP, voids using plasma enhanced chemical vapor deposition (PECVD) A method of forming a void to minimize RC delay in an aluminum (Al) device.
통상적으로, IMD는 도 1a에 도시된 바와 같이, 메탈(10)이 증착(deposition)된 웨이퍼 상에 포토 레지스트(Photo Resist, PR)(20)를 도포하고, 감광하여 RIE(Reactive Ion Etch, RIE)를 위한 PR(20) 패턴을 형성한다.Typically, the IMD is coated with a photoresist (PR) 20 on a wafer on which the metal 10 is deposited, as shown in FIG. 1A, and then exposed to photoresist (RIE). To form a PR 20 pattern.
이후, 도 1b를 참조하면, RIE 공정을 통해 메탈 라인을 형성한 후, HDP를 이용하여 IMD 갭 필(gap fill)(30)을 실시한 다음에, 도 1c와 같이, PECVD(40)를 이용하여 캡 산화막(cap oxide)을 형성하고 이를 CMP하여 평탄화한다. Subsequently, referring to FIG. 1B, after the metal line is formed through the RIE process, the IMD gap fill 30 is performed using HDP, and then the PECVD 40 is performed as shown in FIG. 1C. A cap oxide is formed and CMP is planarized.
이와 같이, IMD는 갭 필(gap fill)을 가장 중요하게 다루는 부분이다. 즉, 디바이스(device) 전체 신호의 딜레이가 백 엔드, 다시 말해서, 메탈과 IMD에 의한 RC 딜레이에 의존하는 실정이다. As such, IMD is the most important part of dealing with gap fill. That is, the delay of the entire device signal depends on the back end, that is, the RC delay caused by the metal and the IMD.
이에, 메탈은 알루미늄(Al)에서 구리(Cu)로 변화해 가는 실정이고, IMD는 SiO2에서 FSG(Fluorine doped Silicon Glass)로 변화해 가는 실정이며, 현재에는 이보다 더 낮은 k 값을 갖는 로우(low) k로 변화해 간다. Accordingly, metal is changing from aluminum (Al) to copper (Cu), and IMD is changing from SiO2 to Fluorine doped Silicon Glass (FSG), and now has a lower k value than this. ) changes to k.
그러나, 로우(low) k 재료는 전기적 특성이 열악하고, 후속 구리(Cu) CMP 시 기계적으로 잘 견디지 못하게 되는 문제점을 갖고 있다. However, low k materials have the problem of poor electrical properties and poor mechanical resistance to subsequent copper (Cu) CMP.
따라서, 본 발명은 상술한 문제점을 해결하기 위해 안출된 것으로, 그 목적은 HDP로 메탈과 메탈 사이를 좁게 만든 후, PECVD을 이용하여 보이드(void)를 형성하여 알루미늄(Al) 디바이스에서 RC 딜레이(delay)를 최소화하도록 하는 반도체의 IMD 형성방법을 제공함에 있다. Accordingly, the present invention has been made to solve the above-described problems, the object of which is to narrow the gap between the metal and the metal by HDP, and then form a void by using PECVD to form an RC delay in the aluminum (Al) device ( A method of forming an IMD of a semiconductor to minimize delay) is provided.
이러한 목적을 달성하기 위한 본 발명에서 반도체의 IMD 형성방법은 메탈이 증착된 웨이퍼 상에 PR를 도포하고, 감광하여 마스크 패턴을 형성하는 단계와, 메탈 마스크 패턴을 형성한 후, HDP를 이용하여 라이너 산화막을 형성하는 단계와, 형성된 라이너 산화막에 대하여 건식 식각을 수행하여 메탈 상부의 HDP 산화막을 제거하고, 메탈 측벽의 상부를 라운딩하여 하부 HDP 산화막이 일부 제거되어 갭 필(gap fill)을 어렵게 하는 단계와, 메탈 상부의 HDP 산화막이 제거된 상태에서, PECVD를 이용하여 캡 산화막(cap oxide)을 증착하여 보이드를 형성시킨 후, 캡 산화막을 CMP하여 평탄화하는 단계를 포함하는 것을 특징으로 한다. In the present invention for achieving this purpose, the method for forming an IMD of a semiconductor is applied to a PR on a metal-deposited wafer, photosensitive to form a mask pattern, and after forming a metal mask pattern, a liner using HDP Forming an oxide layer and performing dry etching on the formed liner oxide layer to remove the HDP oxide layer on the metal, and rounding the upper portion of the metal sidewall to partially remove the lower HDP oxide layer to make a gap fill difficult. And forming a void by depositing a cap oxide film using PECVD in a state where the HDP oxide film on the metal is removed, and then capping the cap oxide film by CMP to planarize the cap oxide film.
이하, 첨부된 도면을 참조하여 본 발명의 구성 및 동작에 대하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the present invention.
도 2는 본 발명에 따른 반도체의 IMD 형성방법에 대하여 도시한 도면이다.2 is a view showing a method for forming an IMD of a semiconductor according to the present invention.
즉, 도 2a를 참조하면, 메탈(10)이 증착(deposition)된 웨이퍼 상에 PR(20)를 도포하고, 감광하여 마스크 패턴을 형성한다. 이때, 메탈은 베리어 메탈(barrier metal)/알루미늄(Al)/베리어 메탈의 시퀀스(sequence)로 수행한다.That is, referring to FIG. 2A, the PR 20 is coated on the wafer on which the metal 10 is deposited, and is exposed to light to form a mask pattern. In this case, the metal is performed in a sequence of barrier metal / aluminum (Al) / barrier metal.
이후, 도 2b를 참조하면, RIE 공정을 통해 메탈(10) 패턴을 형성한 후, 도 2c에 도시된 바와 같이, HDP를 이용하여 라이너 산화막(liner oxide)(50)을 형성한다. 이때, 형성되는 라이너 산화막은 USG(Undoped Silicon Glass)나 FSG(Fluorine doped Silicon Glass)이다.Subsequently, referring to FIG. 2B, after forming the metal 10 pattern through the RIE process, as shown in FIG. 2C, a liner oxide 50 is formed using HDP. At this time, the liner oxide film formed is USG (Undoped Silicon Glass) or FSG (Fluorine doped Silicon Glass).
다음으로, 도 2d를 참조하면, 형성된 라이너 산화막(50)에 대하여 건식 식각을 수행하여 메탈(10) 상부의 HDP 산화막을 제거하고, 측벽의 상부를 라운딩(rounding)한다. 이때, 하부 HDP 산화막도 일부 제거됨에 따라 갭 필(gap fill)이 어렵게 되는 것이다.Next, referring to FIG. 2D, dry etching is performed on the formed liner oxide layer 50 to remove the HDP oxide layer on the metal 10 and round the upper sidewall. At this time, as the lower HDP oxide is partially removed, gap fill becomes difficult.
이후, 도 2e에 도시된 바와 같이, 메탈(10) 상부의 HDP 산화막이 제거된 상태에서, PECVD(60)를 이용하여 캡 산화막(cap oxide)을 증착한다. 이때, PECVD(60)는 SiH4를 기본 가스(gas)로 한 USG 또는 FSG로 한다. 이로 인하여, PE-SiH4 CVD의 특성상 좁아진 메탈과 메탈 갭 사이에 보이드(void)(70)가 형성되는 것이다.Thereafter, as shown in FIG. 2E, a cap oxide layer is deposited using PECVD 60 while the HDP oxide layer on the metal 10 is removed. At this time, the PECVD 60 is made of USG or FSG using SiH 4 as a base gas. As a result, a void 70 is formed between the metal and the metal gap, which are narrowed due to the characteristics of PE-SiH4 CVD.
최종적으로, 도 2f와 같이, 보이드가 형성된 캡 산화막을 CMP(80)하여 평탄화한다. Finally, as shown in FIG. 2F, the cap oxide film having the voids formed thereon is planarized by CMP 80.
따라서, HDP로 메탈과 메탈 사이를 좁게 만든 다음에, PECVD를 이용하여 인위적으로 보이드를 형성하는 과정으로 RC 딜레이에서 가장 중요한 메탈간의 k 값이 낮아지도록 한다. Therefore, HDP narrows the gap between metals and then artificially forms voids using PECVD to lower the k value between the most important metals in the RC delay.
상기와 같이 설명한 본 발명은 HDP로 메탈과 메탈 사이를 좁게 만든 후, PECVD을 이용하여 보이드(void)를 형성하여 알루미늄(Al) 디바이스에서 RC 딜레이(delay)를 최소화함으로써, 로우(low) k 재료에 의해 전기적 특성이 열악하고, 후속 구리(Cu) CMP 시 기계적으로 잘 견디지 못하게 되는 결점을 해결할 수 있는 효과가 있다. As described above, the present invention provides a low k material by narrowing the metal to the metal by HDP, and then forming a void using PECVD to minimize the RC delay in the aluminum (Al) device. Due to the poor electrical properties, there is an effect that can solve the defects that are not mechanically well with the subsequent copper (Cu) CMP.
도 1은 기존 반도체의 아이엠디 형성방법에 대하여 도시한 도면이고,1 is a view showing a method for forming an IMD of a conventional semiconductor,
도 2는 본 발명에 따른 반도체의 아이엠디 형성방법에 대하여 도시한 도면이다.2 is a diagram illustrating a method for forming an IMD of a semiconductor according to the present invention.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2003-0048736A KR100523625B1 (en) | 2003-07-16 | 2003-07-16 | Method for formating imd in semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2003-0048736A KR100523625B1 (en) | 2003-07-16 | 2003-07-16 | Method for formating imd in semiconductor |
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| KR20050009426A KR20050009426A (en) | 2005-01-25 |
| KR100523625B1 true KR100523625B1 (en) | 2005-10-24 |
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| KR100669851B1 (en) | 2005-07-12 | 2007-01-16 | 삼성전자주식회사 | Manufacturing Method of Phase Change Memory Device |
| KR100782487B1 (en) | 2006-08-21 | 2007-12-05 | 삼성전자주식회사 | Void confinement structures, semiconductor devices having the void confinement structures and methods of forming them |
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