JP2005005697A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of forming copper wiring excellent in pattern shape and ashing a resist film without damaging a low-k film. <P>SOLUTION: A stopper film 3 is formed on a semiconductor substrate 2 on which a copper wiring layer 1 is formed, and then an interlayer insulating film 6 formed of a low dielectric material is formed on the stopper film 3. Further, a cap film 7 is formed on the interlayer insulating film 6 and then a resist film 8 having a predetermined pattern is formed on the cap film 7. The cap film 7 and the interlayer insulating film 6 are etched taking the resist film 8 as a mask to form an opening 9 reaching the stopper film 3. Successively, a stopper film 3a exposed to the opening 9 with the resist film 8 left behind is etched to form a via hole 10 and then the resist film 8 is ashed for its removal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device by a damascene method using a low dielectric constant insulating film.

  In recent years, the speed of semiconductor devices has been remarkably increased, and a transmission delay due to a decrease in signal propagation speed due to a wiring resistance in a multilayer wiring portion and a parasitic capacitance between wirings or wiring layers has become a problem. Such a problem tends to become more prominent because the wiring resistance increases and the parasitic capacitance increases as the wiring width and the wiring interval become finer due to higher integration of semiconductor devices.

  In order to prevent signal delay due to an increase in wiring resistance and parasitic capacitance, copper wiring has been introduced instead of aluminum wiring, and an insulating film having a low dielectric constant (hereinafter referred to as a low-k film) is used as an interlayer insulating film. Has been attempted.

  As a method for forming a copper wiring using a low-k film, there is a damascene method. This is known as a technique for forming a wiring without etching copper, considering that it is difficult to control the etching rate of copper compared to aluminum.

  A conventional copper wiring forming process using the damascene method will be described with reference to FIGS. In these drawings, the parts denoted by the same reference numerals are the same.

  First, as shown in FIG. 6A, a stopper film 22 is formed on a silicon substrate 21 on which a copper wiring layer 20 is formed. Here, the copper wiring layer 20 has a barrier metal film 20a and a copper layer 20b. Next, after the Low-k film 23 is formed on the stopper film 22, the cap film 24 is formed on the Low-k film 23 to obtain the structure shown in FIG. Subsequently, the cap film 24, the low-k film 23, and the stopper film 22 are etched to form the via hole 25 and the wiring groove 26 shown in FIG. 6C. Thereafter, a barrier metal film 27 is formed on the inner surfaces of the via hole 25 and the wiring groove 26, and a copper layer 28 is embedded in the via hole 25 and the wiring groove 26 to form a via plug 29 and a copper wiring layer 30. Through the above steps, a copper wiring in which the copper wiring layer 20 formed on the silicon substrate 21 and the upper copper wiring layer 30 are electrically connected via the via plug 29 can be formed (FIG. 6D). ).

  In the above process, the formation of the via hole 25 is specifically performed as follows. First, as shown in FIG. 7A, a resist film 31 having a predetermined pattern is formed on the cap film 24. Then, the cap film 24 and the low-k film 23 are etched by a photolithography method to form an opening 32 that reaches the stopper film 22 (FIG. 7B). Thereafter, the resist film 31 that is no longer needed is removed by ashing, and then the stopper film 22a exposed from the opening 32 is etched to form a via hole 33 (FIG. 7C).

  However, in the conventional step of etching the stopper film 22a, the cap film 24 is also etched together with the stopper film 22a. Further, in the portion where the cap film 24 disappeared by etching, the exposed underlying Low-k film 23 was also etched. As a result, there is a problem that the cross-sectional shape of the via hole 33 has a tapered shape as shown in FIG. When the low-k film 23 is processed into a tapered shape, a copper wiring structure having a desired opening size cannot be formed, and the electrical characteristics of the semiconductor device are degraded.

  Further, ashing of the resist film 31 is performed by oxygen plasma or the like, but there is also a problem that the Low-k film 23 is deteriorated due to plasma damage. Such damage is particularly noticeable in a porous low-k film having a relative dielectric constant lower than 2.5.

  The present invention has been made in view of the above problems. That is, an object of the present invention is to provide a semiconductor device manufacturing method capable of forming a copper wiring having a good pattern shape.

  Another object of the present invention is to provide a semiconductor device manufacturing method capable of ashing a resist film without damaging the Low-k film.

  Other objects and advantages of the present invention will become apparent from the following description.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a stopper film on a semiconductor substrate on which a conductive layer is formed, a step of forming an interlayer insulating film made of a low dielectric constant material on the stopper film, A step of forming a cap film on the interlayer insulating film; a step of forming a resist film having a predetermined pattern on the cap film; and etching the cap film and the interlayer insulating film using the resist film as a mask; A step of forming an opening reaching the stopper film, a step of etching the stopper film exposed in the opening while leaving the resist film to form a via hole, and an ashing of the resist film after forming the via hole And removing it.

  The method for manufacturing a semiconductor device of the present invention can further include a step of forming a barrier metal film on the inner surface of the via hole and a step of embedding a copper layer in the via hole via the barrier metal film.

  In the method for manufacturing a semiconductor device of the present invention, ashing is preferably performed at a temperature of 200 ° C. to 400 ° C. using a mixed gas of hydrogen and an inert gas. At this time, it is preferable to mix 1% by volume to 40% by volume of hydrogen with respect to the inert gas. In this case, the inert gas is an argon gas, and 10% to 40% by volume of hydrogen can be mixed with the argon gas. Moreover, 1 volume%-30 volume% of hydrogen can also be mixed with helium gas as inert gas.

In the semiconductor device manufacturing method of the present invention, the conductive layer is preferably a copper wiring layer. In addition, as the interlayer insulating film, any one film selected from the group consisting of a porous SiO ₂ film, a SiOC film, and an SOG film can be used. In addition, as the stopper film, any one film selected from the group consisting of a SiC film, a Si _x N _y film, a SiCN film, and a SiOC film can be used. Furthermore, as the cap film, a SiO ₂ film or a Si _x N _y film can be used.

  According to the present invention, since the stopper film is etched with the resist film remaining, the cap film and the interlayer insulating film are prevented from being etched, and a semiconductor device having a good pattern shape can be manufactured. .

  Further, according to the present invention, the ashing for removing the resist film is performed at a temperature higher than normal temperature using a mixed gas of hydrogen and an inert gas, so that the semiconductor having good characteristics by preventing damage to the interlayer insulating film The device can be manufactured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  1A to 1F are cross-sectional views illustrating a method for manufacturing a semiconductor device in the present embodiment. As shown in FIG. 1A, a stopper film 3 is formed on a semiconductor substrate 2 on which a copper wiring layer 1 as a conductive layer is formed. Here, the copper wiring layer 1 has a barrier metal film 4 and a copper layer 5. In the present embodiment, a conductive layer other than the copper wiring layer may be formed. For example, a wiring layer of metal other than copper or an impurity doping region may be formed on the semiconductor substrate.

As the semiconductor substrate 2, for example, a silicon substrate can be used. The stopper layer 3 is preferably made of a material having a high etching selectivity with respect to the interlayer insulating film formed thereon. Specifically, it is determined as appropriate depending on the type of the interlayer insulating film. For example, the film is a SiC film, a Si _x N _y (eg, Si ₃ N ₄ , Si ₂ N ₃ , SiN, etc.) film, a SiCN film, or the like. An SiOC film or the like can be used. These films can be formed by a CVD (Chemical Vapor Deposition, hereinafter referred to as CVD) method, a sputtering method, or the like.

  Next, as shown in FIG. 1B, an interlayer insulating film 6 and a cap film 7 are formed in order on the stopper film 3.

The interlayer insulating film 6 is preferably an insulating film (Low-k film) made of a low dielectric constant material. For example, a porous SiO ₂ film, a SiOC film, a SOG (Spin on Glass) film, or the like can be used. Examples of the material for the SOG film include hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ). These films can be formed by CVD, SOD (Spin on Dielectric Coating), or the like.

The cap film 7 has a role of preventing the interlayer insulating film 6 from being etched during the formation of a resist film described later. Further, it also has a role of protecting the interlayer insulating film 6 in the polishing process performed when forming the copper wiring layer. As the cap film 7, for example, a SiO ₂ film or a Si _x N _y (eg, Si ₃ N ₄ , Si ₂ N ₃ , SiN, etc.) film formed by CVD or sputtering is used. Can do.

  After the cap film 7 is formed, a resist film 8 having a predetermined pattern is formed thereon to obtain the structure shown in FIG. Specifically, the resist film 8 can be formed by applying a photoresist on the cap film 7 and then exposing and developing the photoresist.

  Next, using the resist film 8 as a mask, the cap film 7 and the interlayer insulating film 6 are anisotropically etched to form the opening 9. This etching is automatically stopped when the stopper film 3 is reached. Then, as shown in FIG. 1 (d), a part 3 a of the stopper film 3 is exposed to the opening 9.

As an etching apparatus, for example, a dual frequency excitation parallel plate type reactive ion etcher that can apply high frequencies of 60 MHz and 2 MHz to the upper electrode and the lower electrode, respectively, can be used. Specifically, a mixed gas composed of octafluorobutene (C ₄ F ₈ ), nitrogen (N ₂ ), and argon (Ar) is introduced into the apparatus as an etching gas, and the pressure is maintained at 75 mT. Plasma is generated by applying power of 2,400 W and 3,300 W to the lower electrode. At this time, the flow rate ratio of the etching gas can be, for example, 15 sccm for octafluorobutene, 225 sccm for nitrogen, and 1,400 sccm for argon. In addition, the surface temperature of the stage on which the semiconductor substrate is placed can be maintained at 40 ° C.

For etching the cap film 7 and the interlayer insulating film 6, a gas other than the above mixed gas can be used. For example, a mixed gas composed of tetrafluoromethane (CF ₄ ), difluoromethane (CH ₂ F ₂ ), neon (Ne), and argon (Ar) may be used.

  After the etching of the cap film 7 and the interlayer insulating film 6 is completed, the stopper film 3a exposed in the opening 9 is etched to form a via hole. The present embodiment is characterized in that the stopper film 3a is etched with the resist film 8 remaining.

  The etching of the stopper film 3 a is preferably performed following the etching of the cap film 7 and the interlayer insulating film 6. Specifically, it is preferable to carry out in a continuous process using the same etching apparatus. By doing so, it is possible to improve the throughput in the manufacturing process of the semiconductor device, and to improve the yield by preventing the adhesion of foreign matters.

For example, a mixed gas of tetrafluoromethane (CF ₄ ) and nitrogen (N ₂ ) is introduced into the above-mentioned two-frequency excitation parallel plate type reactive ion etcher, and the pressure is maintained at 150 mT, and 1 is applied to the upper electrode. Plasma is generated by applying electric power of 1,000 W and 200 W to the lower electrode. At this time, the flow rate ratio of the etching gas can be set to, for example, 50 sccm for tetrafluoromethane and 300 sccm for nitrogen. In addition, the surface temperature of the stage on which the semiconductor substrate is placed can be maintained at 40 ° C.

  Thus, according to the present embodiment, the etching is performed with the resist film 8 on the cap film 7, so that the cap film 7 can be prevented from being etched. This can also prevent the interlayer insulating film 6 that is the base of the cap film 7 from being etched. Therefore, it is possible to prevent the cap film 7 and the interlayer insulating film 6 from being processed into a tapered shape, and to form a via hole having good patternability.

  After etching the stopper film 3a, the resist film 8 that is no longer needed is removed by ashing to form a via hole 10 shown in FIG. Here, on the bottom surface of the via hole 10, the surface of the lower copper wiring layer 1 is exposed.

By the way, in the conventional method of performing ashing of the resist film before etching the stopper film, for example, oxygen (O ₂ ) gas, ammonia (NH ₃ ) gas, or a mixture of nitrogen (N ₂ ) and hydrogen (H ₂ ). Ashing was performed using a gas or the like at a temperature of room temperature or lower and a pressure of 0.1 Torr or lower. On the other hand, the interlayer dielectric film is more susceptible to damage such as cracking due to ashing because the film density decreases as the relative dielectric constant decreases. Under the above-described conventional conditions, the interlayer insulating film is greatly damaged. In particular, the porous film having a relative dielectric constant of less than 2.5 is markedly damaged.

As a result of diligent research, the present inventor has found that damage to the interlayer insulating film can be prevented by performing ashing at a temperature higher than room temperature using a mixed gas of hydrogen and an inert gas. As the inert gas, a gas that does not easily react with hydrogen, such as helium (He) or argon (Ar), can be used. Nitrogen (N ₂ ) gas is not preferable because damage to the interlayer insulating film is increased.

  FIG. 2A is an example of a cross-sectional TEM (Transmission Electron Microscopy) image after ashing using a mixed gas of hydrogen and helium. For comparison, a cross-sectional TEM photograph after ashing using ammonia gas is also shown (FIG. 2B).

  In FIG. 2B, a stopper film 51, a low-k film 52 and a cap film 53 are stacked on the silicon substrate 50, and a copper wiring layer 55 is embedded in the via hole 54. It can be seen that the low-k film 52 is damaged by the ashing, whereby a void 56 is generated in the low-k film 52 and the side wall of the via hole 54 has a bowing shape.

  FIG. 2A also has the same configuration as FIG. 2B, and a stopper film 41, a low-k film 42 and a cap film 43 are laminated on the silicon substrate 40, and a copper wiring is formed in the via hole 44. Layer 45 is embedded. However, in FIG. 2A, the Low-k film 42 has no voids, and the via hole 44 also has a good cross-sectional shape. Therefore, ashing is performed without damaging the Low-k film 42. I understand that.

  Ashing is preferably performed by mixing hydrogen in an amount of 1 to 40% by volume with respect to the inert gas. If the amount of hydrogen is less than 1% by volume, the ashing rate is generally slow, which is not preferable from the viewpoint of throughput. On the other hand, if the amount of hydrogen exceeds 40% by volume, it is not preferable from the viewpoint of safety.

  FIG. 3 shows the change of the ashing rate with respect to the hydrogen concentration when a mixed gas of hydrogen and argon is used. From the figure, it can be seen that the ashing rate increases as the hydrogen concentration increases. When throughput and safety are comparatively weighed, it is preferable that the amount of hydrogen with respect to the argon gas is in the range of 10 volume% to 40 volume%.

  FIG. 4 shows changes in the ashing rate with respect to the hydrogen concentration when a mixed gas of hydrogen and helium is used. It can be seen that a good ashing rate can be obtained regardless of the hydrogen concentration when helium is used. Therefore, in this case, the amount of hydrogen to be mixed can be freely changed within a range of 1% by volume to 40% by volume. However, when importance is attached to safety, the amount of hydrogen is preferably in the range of 1% by volume to 30% by volume.

  The temperature at the time of ashing is preferably higher than room temperature, and particularly preferably within a range of 200 ° C to 400 ° C. At a temperature lower than 200 ° C., the ashing rate becomes slow and the throughput decreases. On the other hand, at temperatures higher than 400 ° C., copper oxidation and diffusion become severe. The pressure during ashing is preferably set as appropriate according to the temperature, but is preferably within the range of 0.1 Torr to 10 Torr within the above temperature range from the viewpoint of throughput.

  FIG. 5 is a diagram showing a change in ashing rate with respect to temperature when ashing is performed using a mixed gas of hydrogen and helium that has flowed down. For comparison, the case of using oxygen gas and the case of using ammonia gas are also shown. Ashing was performed using a remote plasma apparatus at a pressure of 133 Pa and a plasma power of 2,000 W. The amount of hydrogen relative to helium gas was 5% by volume. FIG. 5 shows that the ashing rate increases exponentially with increasing temperature.

  After the via hole 10 is formed in the interlayer insulating film 6 by the above process, the wiring trench 11 is formed on the via hole 10 by photolithography. Subsequently, a barrier metal film 12 is formed on the inner surfaces of the via hole 10 and the wiring groove 11, and a copper layer 13 is embedded in these via the barrier metal film 12, thereby forming a via plug 14 and a copper wiring layer 15. (FIG. 1 (f)). Specifically, this step can be performed as follows.

  First, after a barrier metal film such as a titanium nitride film or a tantalum nitride film is formed by a CVD method or a sputtering method, a copper layer is further formed thereon. Subsequently, the copper layer and the barrier metal film are polished by a chemical mechanical polishing (CMP) method. Thus, the copper layer and the barrier metal film can be left only in the via hole and the wiring groove.

The formation of the barrier metal film and the filling of the copper layer may be performed by other methods. For example, after the barrier metal is formed only inside the wiring groove by the CVD method and the CMP method, copper may be embedded in the wiring groove by a plating method using an electrolytic solution based on copper sulfate (CuSO ₄ ).

  Through the above steps, the via plug 14 and the copper wiring layer 15 can be formed on the semiconductor substrate 2 having the copper wiring layer 1 (FIG. 1F). Here, the copper wiring layer 15 is electrically connected to the copper wiring layer 1 via the via plug 14.

(A)-(f) is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is the cross-sectional TEM photograph after ashing, (a) is the case where the mixed gas of hydrogen and helium is used, (b) is the case where ammonia gas is used. It is a figure which shows the change of the ashing rate with respect to hydrogen concentration when using the mixed gas of hydrogen and argon. It is a figure which shows the change of the ashing rate with respect to hydrogen concentration when the mixed gas of hydrogen and helium is used. It is a figure which shows the change of the ashing rate with respect to temperature at the time of ashing using the mixed gas of hydrogen and helium. (A)-(d) is sectional drawing which shows the manufacturing process of the conventional semiconductor device. (A)-(c) is sectional drawing which shows the manufacturing process of the conventional semiconductor device.

Explanation of symbols

1, 15, 20, 30 Copper wiring layer 2 Semiconductor substrate 3, 22 Stopper film 4, 12, 27 Barrier metal film 5, 13, 28 Copper layer 6, 23 Interlayer insulating film 7, 24 Cap film 8, 31 Resist film 9 32 Open hole 10, 25, 33 Via hole 11, 26 Wiring groove 14, 29 Via plug 21 Silicon substrate

Claims (10)

Forming a stopper film on the semiconductor substrate on which the conductive layer is formed;
Forming an interlayer insulating film made of a low dielectric constant material on the stopper film;
Forming a cap film on the interlayer insulating film;
Forming a resist film having a predetermined pattern on the cap film;
Etching the cap film and the interlayer insulating film using the resist film as a mask to form an opening reaching the stopper film;
Etching the stopper film exposed in the opening with the resist film left, and forming a via hole;
And a step of ashing and removing the resist film after forming the via hole. Forming a barrier metal film on the inner surface of the via hole;
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of burying a copper layer inside the via hole via the barrier metal film.   The method of manufacturing a semiconductor device according to claim 1, wherein the ashing is performed at a temperature of 200 ° C. to 400 ° C. using a mixed gas of hydrogen and an inert gas.   The method for manufacturing a semiconductor device according to claim 3, wherein the hydrogen is mixed in an amount of 1% by volume to 40% by volume with respect to the inert gas.   The method for manufacturing a semiconductor device according to claim 4, wherein the inert gas is an argon gas, and the hydrogen gas is mixed in an amount of 10 to 40% by volume with respect to the argon gas.   The method of manufacturing a semiconductor device according to claim 4, wherein the inert gas is helium gas, and the hydrogen is mixed in an amount of 1% by volume to 30% by volume with the helium gas.   The method for manufacturing a semiconductor device according to claim 1, wherein the conductive layer is a copper wiring layer. The method for manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is one film selected from the group consisting of a porous SiO ₂ film, a SiOC film, and an SOG film. The method for manufacturing a semiconductor device according to claim 1, wherein the stopper film is one film selected from the group consisting of a SiC film, a Si _x N _y film, a SiCN film, and a SiOC film. The method for manufacturing a semiconductor device according to claim 1, wherein the cap film is a SiO ₂ film or a Si _x N _y film.

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