KR100472270B1 - Active matrix type display device - Google Patents

Abstract

The present invention provides a display device having a holding circuit comprising: a plurality of pixel electrodes arranged in a matrix shape, a plurality of holding circuits disposed corresponding to these pixel electrodes, for the purpose of further increasing the accuracy or further improving the aperture ratio; In an active matrix display device including a power supply line for supplying predetermined voltages to these sustain circuits, and a voltage corresponding to data held by the sustain circuit is supplied to the pixel electrode to perform display, the power supply line is any one of a matrix. An active matrix display device is provided which is shared in a holding circuit corresponding to pixel electrodes arranged in one direction and extending in the direction of, and shared in a pixel electrode adjacent to another direction in a matrix.

Description

Active matrix display device {ACTIVE MATRIX TYPE DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device, and more particularly, to an active matrix display device provided with a plurality of holding circuits corresponding to pixels.

In recent years, portable display devices such as portable televisions, mobile phones, and the like have been demanded by market needs. In response to these demands, research and development have been actively conducted to cope with the miniaturization, light weight, and low power consumption of display devices.

6 shows a circuit configuration diagram of one pixel electrode in a liquid crystal display (LCD) according to the prior art. The gate signal line 51 and the drain signal line 61 intersect and are formed on an insulating substrate (not shown), and the pixel selection TFT 65 connected to these signal lines 51 and 61 is provided near the intersection. It is. The source 65s of the pixel selection TFT 65 is connected to the pixel electrode 17 of the liquid crystal 21.

In addition, a storage capacitor 85 for maintaining the voltage of the pixel electrode 17 for one field period is provided, and one terminal 86 of the storage capacitor 85 is provided with a source (for example) of the pixel selection TFT 65. 65 s), and a potential common to each pixel electrode is applied to the other electrode 87.

Here, when a gate signal is applied to the gate signal line 51, the pixel select TFT 65 is turned on so that an analog image signal is transmitted from the drain signal line 61 to the pixel electrode 17, and the storage capacitor 85 is provided. Is maintained. An image signal voltage applied to the pixel electrode 17 is applied to the liquid crystal 21, and the liquid crystal 21 is aligned according to the voltage. LCDs may be implemented by arranging such pixel electrodes in a matrix.

Conventional LCDs can obtain displays regardless of moving or still images. In the case of displaying a still image on such LCD, for example, an image of a battery is displayed as a display of the remaining amount of the battery for driving the mobile telephone on a part of the liquid crystal display of the mobile telephone.

However, in the liquid crystal display device having the above-described configuration, similarly to the case of displaying a moving image even when displaying a still image, the video signal can be rewritten to each pixel electrode with the pixel selection TFT 65 turned on with the gate signal. A need arose.

Therefore, a driver circuit for generating drive signals such as a gate signal and a video signal and an external LSI for generating various signals for controlling the operation timing of the driver circuit always operate, and therefore have consumed large power. For this reason, in the mobile telephone etc. which have only a limited power supply, the usable time becomes short.

In contrast, a liquid crystal display device having a static memory in each pixel electrode is disclosed in Japanese Patent Laid-Open No. Hei 8-194205. In this specification, a part of this publication is quoted and demonstrated. 7 is a planar circuit diagram of an active matrix display device having a holding circuit disclosed in Japanese Patent Laid-Open No. Hei 8-194205. A plurality of gate signal lines 51 and reference lines 52 are arranged in a row direction, and a plurality of drain signal lines 61 are arranged in a column direction. The TFT 53 is provided between the holding circuit 54 and the pixel electrode 17. By displaying based on the data held in the holding circuit 54, the gate driver 50 and the drain driver 60 are stopped to reduce power consumption.

8 is a circuit diagram illustrating one pixel of the liquid crystal display. The pixel electrodes are arranged in a matrix on the substrate, and the gate signal lines 51 are arranged in the horizontal direction of the paper between the pixel electrodes 17, and the drain signal lines 61 are arranged in the vertical direction of the paper. The reference line 52 is disposed in parallel with the gate signal line 51, and the sustain circuit 54 is provided at the intersection of the gate signal line 51 and the drain signal line 61, and the sustain circuit 54 and the pixel electrode are provided. The switch elements 53 are provided between the 17 elements. The holding circuit 54 uses a memory having a form of positive feedback of the two-stage inverters 55 and 56, that is, a static random access memory (SRAM), as the holding circuit of the digital video signal. In particular, SRAM, unlike DRAM, is suitable because it does not require refreshing to hold data.

Here, in response to the binary digital signal held in the static memory, the switch element 53 controls the resistance value between the reference line Vref and the pixel electrode 17 in accordance with the output of the holding circuit 54, whereby the liquid crystal 21 The bias state of is being adjusted. On the other hand, the AC signal Vcom is input to the common electrode. Ideally, the apparatus is not required to refresh the memory unless there is a change in the display image such as a still image.

However, when the static RAM is used for the holding circuit 54, the number of transistors constituting the holding circuit increases to four or six, resulting in a large circuit area. When such a static RAM is disposed between the pixel electrodes 17, the area of the pixel electrodes 17 becomes small, and the aperture ratio of the liquid crystal display device is lowered, or one pixel size must be increased, so that high precision is difficult. There was.

Therefore, an object of the present invention is to increase the accuracy or to increase the aperture ratio in a display device having a holding circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and includes a plurality of pixel electrodes arranged in a matrix shape, a plurality of holding circuits arranged corresponding to the pixel electrodes, and a power supply line for supplying a predetermined voltage to the holding circuits. In an active matrix display device in which a voltage corresponding to data held by a holding circuit is supplied to a pixel electrode to perform display, the power supply line extends in any one direction of the matrix and corresponds to the pixel electrode arranged in one direction. An active matrix display device which is shared by a holding circuit and shared by a holding circuit corresponding to pixel electrodes adjacent to other directions in a matrix.

According to this configuration, in the active matrix display device having the holding circuit, the number of power supply lines can be reduced by half and the pixel size can be reduced, compared to the arrangement of the power supply lines for each row. It can be implemented as a display device.

And a pixel electrode arranged in a matrix, a plurality of gate signal lines arranged in a row direction, and a plurality of drain signal lines arranged in a column direction, wherein the pixel electrode is selected by a scan signal from the gate signal line and drained. An active matrix display device in which an image signal is supplied from a signal line, comprising: a first display circuit for supplying a signal corresponding to an image signal from a drain signal line to a pixel electrode selected by a scan signal input from a gate signal line, and a predetermined voltage; A second display circuit which is supplied with a holding circuit for holding a video signal from the drain signal line in accordance with a signal input from the gate signal line, and supplies a signal corresponding to the signal from the holding circuit to the display electrode; Selectively selecting the first and second display circuits based on the circuit selection signal. A circuit selection circuit for connecting to the drain signal line, wherein the power supply line for supplying a predetermined voltage to the holding circuit extends in one direction of the matrix and is shared by the holding circuit corresponding to the pixel electrodes arranged in this direction; The active matrix display device is shared by a plurality of pixels adjacent to different directions of the matrix.

According to this configuration, in the active matrix display device which can select any one of the first and second display circuits, the number of power lines can be reduced by half compared to the arrangement of power lines for each row, thereby reducing the pixel size. As a result, a more precise active matrix display device can be implemented.

Preferred embodiments thereof are as follows. That is, at least two driving power lines extending in one direction of the matrix and supplying different driving voltages are connected to each of the holding circuits, and at least one of the driving power lines is arranged in a plurality of pixels adjacent to the other direction of the matrix. Shared

In addition, at least two reference power lines extending in one direction of the matrix to supply different reference voltages are connected to each of the sustain circuits, and the sustain circuit selects and supplies the reference voltages to the pixel electrodes based on the retained data. At least one of the reference power supply lines is shared by a plurality of pixels adjacent to the other direction of the matrix.

In addition, the shared power supply line supplies the same voltage to all the holding circuits. In addition, the shared power supply line is disposed near pixels adjacent to different directions of the matrix, and the arrangement of the holding circuits in pixels adjacent to different directions of the matrix has an axis or a center between pixels adjacent to different directions of the matrix. They are arranged symmetrically with a shared power line in between.

Next, a display device according to an exemplary embodiment of the present invention will be described. 1 shows a circuit configuration diagram when the display device of the present invention is applied to a liquid crystal display device.

In the liquid crystal display panel 100, a plurality of pixel electrodes 17 are arranged in a matrix on the insulating substrate 10. The plurality of gate signal lines 51 connected to the gate driver 50 for supplying the gate signal are arranged in one direction, and the plurality of drain signal lines 61 are arranged in the direction crossing the gate signal lines 51. It is.

The drain signal line 61 is provided with sampling transistors SP1, SP2,... Based on the timing of the sampling pulses output from the drain driver 60. SPn is turned on, and the data signal (analog video signal or digital video signal) of the data signal line 62 is supplied.

The gate driver 50 selects an arbitrary gate signal line 51 and supplies a gate signal thereto. The data signal is supplied from the drain signal line 61 to the pixel electrodes 17 of the selected row.

Hereinafter, the detailed structure of each pixel is demonstrated. In the vicinity of the intersection of the gate signal line 51 and the drain signal line 61, a circuit selection circuit 40 composed of a P-channel circuit selection TFT 41 and an N-channel circuit selection TFT 42 is provided. Each drain of these circuit selection TFTs 41 and 42 is connected to a drain signal line 61, and each of these gates is connected to a circuit selection signal line 88. One of the circuit selection TFTs 41 and 42 is turned on based on the selection signal from the selection signal line 88. In addition, as will be described later, a circuit selection circuit 43 is provided in pair with the circuit selection circuit 40. These circuit selection circuits 40 and 43 may have their respective transistors operate complementarily, and of course, the P-channel and N-channel may be reversed. In addition, only one of the circuit selection circuits 40 and 43 may be omitted.

As a result, it becomes possible to select and switch the analog video signal display (full color moving picture correspondence) which is a normal operation mode described later and the digital video display (low power consumption, still image correspondence) which are the memory operation mode. In addition, adjacent to the circuit selection circuit 40, a pixel selection circuit 70 composed of an N-channel pixel selection TFT 71 and an N-channel TFT 72 is disposed. These pixel selection TFTs 71 and 72 are connected to the circuit selection TFTs 41 and 42 of the circuit selection circuit 40 by a cascade, respectively, and the gate signal line 51 is connected to these gates. Both the pixel selection TFTs 71 and 72 are configured to be turned on at the same time in response to a gate signal from the gate signal line 51.

In addition, a storage capacitor 85 for holding an analog video signal is provided. One electrode of the storage capacitor 85 is connected to the source of the pixel selection TFT 71. The other electrode is connected to the common storage capacitor line 87, and the bias voltage Vsc is supplied. In addition, the source of the pixel selection TFT 71 is connected to the pixel electrode 17 through the circuit selection TFT 44 and the contact 16. When the gate of the pixel selection TFT 70 is opened by the gate signal, the analog video signal supplied from the drain signal line 61 is input to the pixel electrode 17 through the contact 16 to drive the liquid crystal as the pixel voltage. . The pixel voltage should be maintained for one field period until the pixel selection TFT 71 is deselected and next selected again, but only the liquid crystal capacity of the pixel voltage gradually decreases with time, so that one field period is sufficiently maintained. It doesn't work. Therefore, the fall of the pixel voltage appears as display unevenness, and favorable display is not obtained. Therefore, the storage capacitor 85 is provided to maintain the pixel voltage for one field period.

A P-channel TFT 44 of the circuit selection circuit 43 is provided between the storage capacitor 85 and the pixel electrode 17, and is on-off at the same time as the circuit selection TFT 41 of the circuit selection circuit 40. It is comprised so that it may become. The operation mode in which the circuit selection TFT 41 is turned on and supplies an analog signal at any time to drive the liquid crystal is called a normal operation mode or an analog operation mode.

In addition, a holding circuit 110 is provided between the TFT 72 and the pixel electrode 17 of the pixel selection circuit 70. The holding circuit 110 is composed of two positive feedback inverter circuits and a signal selection circuit 120, and constitutes a static memory for holding a digital binary value.

The signal selection circuit 120 is a circuit for selecting signals based on signals from two inverters, and is composed of two N-channel TFTs 121 and 122. Since complementary output signals from two inverters are applied to the gates of the TFTs 121 and 122, respectively, the TFTs 121 and 122 are complementarily turned on and off.

Here, when the TFT 122 is turned on, an AC drive signal (signal B) is selected, and when the TFT 121 is turned on, an AC drive signal (signal A) equivalent to the counter electrode signal VCOM is selected and selected. It is supplied to the pixel electrode 17 of the liquid crystal 21 through the TFT 45 of the circuit 43. The operation mode in which the circuit selection TFT 42 is turned on and displays based on the data held in the holding circuit 110 is called a memory mode or a digital operation mode.

In summary, the above-described configuration includes a circuit (analog display circuit) consisting of a pixel selection TFT 71 as a pixel selection element and a storage capacitor 85 for holding an analog video signal, a TFT 72 as a pixel selection element, and a binary value. A circuit (digital display circuit) consisting of a holding circuit 110 for holding a digital video signal is provided in one pixel electrode, and circuit selection circuits 40 and 43 for selecting these two circuits are provided. .

Next, the peripheral circuit of the liquid crystal panel 100 will be described. A panel driving LSI 91 is provided on an external circuit board 90 which is a substrate separate from the insulating substrate 10 of the liquid crystal panel 100. The vertical start signal STV is input to the gate driver 50 from the panel driving LSI 91 of the external circuit board 90, and the horizontal start signal STH is input to the drain driver 60. In addition, an image signal is input to the data line 62.

Next, a driving method of the display device having the above-described configuration will be described.

(1) In the case of normal operation mode (analog operation mode)

When the analog display mode is selected based on the mode signal, the LSI 91 is set to a state in which an analog signal is supplied to the data signal line 62, and the potential of the circuit selection signal line 88 becomes "L" so that the circuit The circuit selection TFTs 41 and 44 of the selection circuits 40 and 43 are turned on, and the circuit selection TFTs 42 and 45 are turned off.

In addition, the sampling transistor SP is sequentially turned on in accordance with the sampling signal based on the horizontal start signal STH, and the analog video signal of the data signal line 62 is supplied to the drain signal line 61.

Further, the gate signal is supplied to the gate signal line 51 based on the vertical start signal STV. In response to the gate signal, when the pixel selection TFT 71 is turned on, the analog image signal An.Sig is transmitted from the drain signal line 61 to the pixel electrode 17 and held in the storage capacitor 85. An image signal voltage applied to the pixel electrode 17 is applied to the liquid crystal 21, and the liquid crystal 21 is oriented according to the voltage to implement liquid crystal display.

In this analog display mode, since the liquid crystal is driven at any time based on the analog signal input at any time, it is suitable for displaying a full color moving image. However, power is continually consumed in order to drive them to the LSI 91 and the respective drivers 50 and 60 of the external circuit board 90.

(2) In the memory operation mode (digital display mode)

When the digital display mode is selected based on the mode signal, the LSI 91 digitally converts the video signal, sets the digital data obtained by extracting the upper 1 bit to the data signal line 62, and sets the circuit selection signal line ( 88) becomes "H". Accordingly, the circuit selection TFTs 41 and 44 of the circuit selection circuits 40 and 43 are turned off while the circuit selection TFTs 42 and 45 are turned on, so that the holding circuit 110 is in an effective state. It becomes

The start signal STH is input to the gate driver 50 and the drain driver 60 from the LSI 91 for panel driving of the external circuit board 90. As a result, sampling signals are sequentially generated, and the sampling transistors SP1, SP2,... , SPn is turned on in order, and the digital video signal D. Sig is sampled and supplied to each drain signal line 61.

Here, the gate signal line 51 to which the first row, that is, the gate signal G1 is applied, will be described. First, each pixel select TFT 72 of each pixel electrode connected to the gate signal line 51 by the gate signal G1 is turned on for one horizontal scanning period. When attention is paid to the pixel electrodes in the first row and the first column, the digital video signal S11 sampled by the sampling signal SP1 is input to the drain signal line 61. When the pixel selection TFT 72 is turned on by the gate signal, the digital signal D. Sig is input to the holding circuit 110 and held by two inverters.

The signal held in this inverter is input to the signal selection circuit 120, and the signal selection circuit 120 selects the signal A or the signal B, the selected signal is applied to the pixel electrode 17, and the voltage thereof is the liquid crystal. Is applied to (21).

In this way, scanning is performed from the gate signal line of the first row to the gate signal line of the last row, so that scanning for one screen (one field period), that is, all dot scans, is completed, and one screen is displayed.

When one screen is displayed, the voltage supply to the gate driver 50 and the drain driver 60 and the external panel driving LSI 91 is stopped to stop their driving. The sustain circuit 110 is always supplied with the driving voltages V _DD and V _SS for driving, and the counter electrode voltage is supplied to the counter electrode 32, and the signals A and B are supplied to the selection circuit 120.

That is, in the case where the holding circuit 110 supplies driving voltages V _DD and V _SS for driving thereof, the counter electrode voltage V _COM is applied to the counter electrode, and the liquid crystal display panel 100 is normal white (NW). The signal A is only applied with an AC drive voltage having the same potential as the counter electrode voltage, and with the signal B an AC voltage for driving the liquid crystal (for example, 60 mA). In this way, one screen can be maintained and displayed as a still image. In addition, no voltage is applied to the other gate driver 50, the drain driver 60, and the external panel driving LSI 91.

At this time, when the H-level digital video signal is input to the holding circuit 110 in the drain signal line 61, since the "L" is input to the first TFT 121 in the signal selection circuit 120, the first signal is inputted. The TFT 121 is turned off, and since "H" is input to the other second TFT 122, the second TFT 122 is turned on. Accordingly, the signal B is selected and the voltage of the signal B is applied to the liquid crystal. That is, since the AC voltage of the signal B is applied and the liquid crystal rises by the electric field, it can be observed as a black display as a display in the display panel of NW.

When the L-level digital video signal is input to the holding circuit 110 in the drain signal line 61, since the "H" is input to the first TFT 121 in the signal selection circuit 120, the first TFT 121 is used. ) Is turned on, and since "L" is input to the other second TFT 122, the second TFT 122 is turned off. Accordingly, the signal A is selected and the voltage of the signal A is applied to the liquid crystal. That is, since a voltage equivalent to that of the counter electrode 32 is applied, the electric field does not occur and the liquid crystal does not rise. Therefore, the display panel of the NW can be observed as a white display as a display.

In this way, it is possible to display as a still image by writing and retaining one screen, but in this case, the driving of each of the drivers 50, 60 and the LSI 91 is stopped, so that lower power consumption can be achieved.

In the above embodiment, the holding circuit 110 holds only one bit, but of course, if the holding circuit 110 is multiplexed, gray scale display can be performed in the memory operation mode, and the holding circuit 110 stores the analog value. When the memory is used, full color display in the memory operation mode can be performed.

As described above, according to the exemplary embodiment of the present invention, one liquid crystal display panel 100 includes a full color moving picture display (in the analog display mode) and a low power consumption digital gradation display (in the digital display mode). Kinds of indications can be implemented.

Next, the layout of this embodiment will be described with reference to FIG. 2 is a conceptual diagram showing the layout of this embodiment. The P-channel circuit selection TFT 41 of the circuit selection circuit, the N-channel pixel selection TFT 71 of the pixel selection circuit, and the P-channel TFT 44 of the circuit selection circuit are connected in series, and a contact is made to the pixel electrode 17. It is connected via 16) and is connected to the auxiliary capacitance 85. Further, the N-channel circuit selection TFT 42, the N-channel pixel selection TFT 72, the holding circuit 110, and the N-channel TFT 45 of the circuit selection circuit are connected to the pixel electrode 17 via the contact 16. It is. All of the above structures are arranged to overlap the pixel electrode 17.

Although the circuit structure arranged in each pixel is almost the same in each pixel, the circuit arrangement of pixels adjacent to a column direction has a line symmetry structure which made the axis | shaft between the pixels of each other substantially. That is, in the pixel of the first column of FIG. 2, the gate signal line 51 is disposed at the upper end of the pixel, and the sustain circuit 110 is disposed at the lower half of the pixel. In the second pixel of FIG. 2, the gate signal line 51 is disposed at the lower end of the pixel, and the sustain circuit 110 is disposed in the upper half of the pixel. Similarly, in the pixel of the 3rd column which is not shown in figure, it becomes the same arrangement as the pixel of the 1st column which arrange | positioned the gate signal line 51 on the upper end, and the holding circuit 110 in the lower half.

The holding circuit 110 is an SRAM as described above. The holding circuit 110 is connected to a total of four power supply lines using two high and low drive power supply lines LV _DD and LV _SS and two high and low reference power supply lines (signal A and signal B). . These power supply lines extend in the row direction and are shared by each pixel of the row like the gate signal line 51, the storage capacitor line 87, and the like. The above is the point common in the circuit arrangement of each pixel. In this embodiment, the circuit layout of each pixel is different. The circuit layout of each pixel is laid out in line symmetry between pixels adjacent to the column direction. The holding circuits 110 of the pixels adjacent to the column direction are arranged close to each other with these four power supply lines interposed therebetween, and the four power supply lines are common to both holding circuits 110. That is, each power supply line is arrange | positioned at one ratio to two rows of pixels, and is connected to all the holding circuits corresponding to the two rows of pixels. Therefore, the power supply line extending in the row direction can be cut in half as compared with the arrangement in each row. Since the active matrix display device having the holding circuit 110 has many circuits provided for each pixel, reducing the components of the circuit is directly connected to the reduction of the pixel area. Therefore, the display device having the holding circuit can be made highly accurate.

For example, since the gate signal lines 51 need to be turned on at different timings in each row, they cannot be shared across different rows. In contrast, the four power supply lines shared in this embodiment are lines for supplying the driving voltage and the reference voltage of the holding circuit 110, and the selection or non-selection of the pixels and the display contents (white and black) of the pixels are performed. Regardless, the voltage applied in common to the sustain circuits 110 of all the pixels is continuously supplied. Therefore, it can be shared across multiple rows. In addition, for the same reason, even when the active matrix display device performs color display, the power lines can be shared between adjacent pixels. In other words, the present invention can be implemented not only in a stripe arrangement in which the same colors are arranged in the column direction, but also in a delta arrangement in which RGBs are alternately arranged.

Next, the relationship on the layout of the four power supply lines and the pixel electrode 17 will be described. FIG. 3 is a layout conceptual diagram illustrating a boundary portion of pixels GS1 and GS2 adjacent to a column direction in FIG. 2. As shown in Fig. 3, the power supply line 19 shared by the two pixels GS1 and GS2 (the power supply line LV _DD supplied to the SRAM of the holding circuit 110 in Fig. 2) is one pixel, for example. Each source 110S, 110S of the thin film transistor TFT that overlaps and extends the pixel GS2 and branches in the middle thereof in the direction of the pixels GS1, GS2, and constitutes each SRAM through the contacts 18, 18, respectively. )

In this layout, parasitic capacitance is formed between the pixel electrode 17 and the power supply line 19 of the pixel GS2 through an insulating film. Since the parasitic capacitance becomes very large compared with the parasitic capacitance formed between the pixel electrode 17 and the power supply line 19 of the pixel GS1, the influence on the pixel electrodes 17 and 17 of the parasitic capacitance becomes non-uniform. For this reason, the influence of the parasitic capacitance is generated every other pixel, and the display quality is deteriorated as horizontal lines or vertical lines on the screen.

Thus, in the pixel GS1 on the side where the power supply line 19 does not overlap with the pixel electrode 17, the branched power supply line 19 forms an overlapping region 20 formed by expanding on the pixel electrode 17. The parasitic capacitance between the pixel electrode 17 and the power supply line 19 is increased to balance the parasitic capacitance of the adjacent pixel GS2 to eliminate the influence of the parasitic capacitance. Here, by forming the overlapped region 20 in which the power supply line 19 is extended, the parasitic capacitance value formed between the pixel electrode 17 and the power supply line 19 is the same for the adjacent pixels GS1 and GS2. desirable.

The power supply line 19 is not limited to the driving power supply line LV _DD on the high voltage side of the holding circuit 110, and is driven by the reference power supply lines (signals A and B) and the low voltage side of the holding circuit 110. Either the power line LV _{SS or} the reference power line carrying the signal B may be used.

In addition, in the above-described layout, the power supply line 19 is directly capacitively coupled by being superimposed on the pixel electrode 17, but it is not necessarily superimposed on the pixel electrode 17. For example, as in the case where the source of the TFT and the pixel electrode 17 are connected via the intermediate electrode layer, the power supply line 19 may be indirectly coupled to the pixel electrode 17 via the intermediate electrode layer. It's okay. Therefore, the overlapping region 20 formed by extending the above-mentioned power supply line 19 on the pixel electrode 17 does not necessarily need to overlap on the pixel electrode 17, but is formed on the intermediate electrode layer as described above. If nested in the same effect.

On the other hand, the LCD of this embodiment is a reflective LCD. 4 is a cross-sectional view taken along the line AA ′ of FIG. 2 as the reflective LCD of the present embodiment. A semiconductor layer 11 made of polycrystalline silicon and isolated like an island is disposed on one insulating substrate 10, and a gate insulating film 12 is coated thereon. A gate electrode 13 is disposed on the gate insulating film 12 above the semiconductor layer 11, and a source and a drain are formed in the semiconductor layer 11, which is a lower layer located on both sides of the gate electrode 13. On the gate electrode 13 and the gate insulating film 12, an interlayer insulating film 14 covering them is formed. A contact is formed at a position corresponding to the drain and the source, and the drain is in contact with the pixel selection TFT 71 through the contact, and the source is connected to the pixel electrode 17 via the contact 16. Each pixel electrode 17 formed on the planarization insulating film 15 is made of a reflective material such as aluminum (Al). On each pixel electrode 17 and planarization insulating film 15, an alignment film 20 made of polyimide or the like for orienting the liquid crystal 21 is formed.

On the other insulating substrate 30, a counter electrode made of a transparent conductive film such as a color filter 31 representing each color of red (R), green (G), and blue (B), indium tin oxide (ITO), or the like ( The alignment film 33 which orientates 32 and the liquid crystal 21 is formed in order. Of course, the color filter 31 is unnecessary when not using color display.

The periphery of the pair of insulating board | substrates 10 and 30 formed in this way is adhere | attached with an adhesive sealing material, and the liquid crystal 21 is filled in the space | gap formed thereby.

In the reflective LCD, as indicated by the dotted arrow in FIG. 4, external light incident from the insulating substrate 30 side is reflected by the pixel electrode 17 and emitted to the observer 1 side, whereby the display can be observed. have.

In the reflective LCD, light does not transmit through the pixel electrode 17, so that any element disposed under the pixel electrode 17 does not affect the aperture ratio. By arranging the holding circuit 110 which requires a large area under the pixel electrode 17, the intervals between the pixels can be made equal to that of a normal LCD. Note that it is not necessary to arrange all the structures under the pixel electrodes as in the present embodiment, and some of the components may be arranged between the pixel electrodes.

Next, a second embodiment of the present invention will be described with reference to the drawings. 5 is a conceptual diagram showing a planar layout of this embodiment. This embodiment is a stripe arrangement in which pixels of each color of RGB are arranged in alignment, and any one of the color filters of RGB is correspondingly arranged on each pixel electrode 17, and these are denoted by reference numerals 17R, 17G, and 17B. . Each pixel of RGB has a circuit similar to that of FIG. 2, and the data of the pixel can be held in the holding circuit 110 in each pixel.

The characteristic feature of the present embodiment is that the layout of the pixel electrode 17 and the circuit layout of the sustain circuit, the selection circuit, and the storage capacitor do not coincide. This point will be described in detail below. First, attention is paid to the pixel electrode 17R. The pixel electrode 17R is disposed at the left end in FIG. 5 and has a rectangular structure that is long in the vertical direction. The contact connecting the pixel electrode 17R and its circuit is indicated by reference numeral 16R. The circuit selection TFTs 41R and 44R and the pixel selection TFT 71R are connected in series, and part of them extends to the pixel electrode 17G which is an adjacent pixel. Similarly, the storage capacitor 85R and the holding circuit 110R also extend to the pixel electrode 17G. The pixel electrode 17G is connected to the corresponding circuit via the contact 16G, and the circuit selection TFT 41G, the pixel selection TFT 71G, the storage capacitor 85G, and the holding circuit 110G are adjacent pixels. It overlaps with the phosphor pixel electrode 17R.

The circuits corresponding to the pixel electrodes 17R and 17G share the gate signal line 51 and are arranged in point symmetry with respect to one point on the gate signal line. Hereinafter, similarly, the circuit corresponding to the pixel electrode 17B also extends to its adjacent pixel electrode (not shown). If this pixel is referred to as pixel electrode 17R ', the circuit corresponding to pixel electrode 17R' is superimposed on pixel electrode 17B.

The advantage obtained by arrange | positioning in this way is demonstrated below. For example, if one RGB pixel is used as one pixel, and the pixel is almost square, each RGB pixel is 3: 1, which is a vertical rectangle. In general, individual RGB pixels in a stripe array become long rectangles in one direction. If the holding circuit 110 or the like is to be arranged under the thin long rectangular pixel electrode 17 in accordance with the layout, the design of the circuit becomes difficult. In contrast, according to the present invention, since the layout of the pixel electrodes 17 and the layout of the circuits are different, troublesome wiring bypasses and the like are unnecessary, resulting in high space efficiency, which can reduce the area required by the holding circuit. In the case of an LCD having a holding circuit, since the minimum area of one pixel mainly occupies the area occupied by the holding circuit, it can be said that reducing the holding circuit is directly connected to high precision of the LCD.

Next, the advantages obtained by symmetrically arranging the circuits with the gate signal lines in between will be described below. In the case where the adjacent pixels share the area with each other, it is necessary to adjust the layout in the circuit for each pixel. However, if the adjacent pixels are arranged in point symmetry, a circuit of one pixel can be designed and the circuit can be designed to be symmetrical to the circuit. The efficiency of the design is good. However, it is necessary to adjust the wiring to the four power supply lines shown in the upper and lower ends of the pixel in FIG. Further, if the circuit layout is moved in parallel without making point symmetry, it is necessary to arrange the gate signal lines of adjacent pixels at mutual distances, and it is necessary to arrange two gate signal lines in each row. On the other hand, in this embodiment, since the circuits are arranged symmetrically, only one gate signal line is required in each row, so there is no need to increase it.

Also in this embodiment, similarly to the first embodiment, the holding circuit 110 is disposed at the upper and lower ends of the pixels, and the holding circuit 110 of the pixels adjacent to the column direction is connected to the power supply lines V _DD and V _SS. , Signals A and B are disposed in close proximity to each other and share these four power lines. Therefore, as in the first embodiment, the power supply line can be cut in half as compared with the arrangement of the power supply lines in each row.

In the first and second embodiments, four power lines are shared by adjacent pixels, but not all power lines are necessarily shared. When four power supply lines are arranged adjacent to each other, parasitic capacitance occurs because all of the wirings branched from each power supply line in the column direction for connection to the holding circuit 110 intersect with the other three power supply lines. In addition, the case where one power supply line is arrange | positioned, for example between the holding circuit 110 of the layout of this embodiment, the auxiliary capacitance 85, etc. is assumed as a case where layout efficiency is favorable as a whole. In such a case, an arbitrary power supply line may be shared among four power supply lines.

As a result of sharing the power lines in the first and second embodiments, the circuit arrangement is not completely line-symmetrical or point-symmetrical, so that parasitic capacitances formed at each power line and pixel electrode 17 may be different from one another. . Therefore, the signal delays between the pixels are different from each other, and there is a fear that the display quality is lowered. Therefore, in order to make this parasitic capacitance constant, if 2n power supply lines to be shared (n is a natural number), n pixels are superimposed on each pixel, and if there are 2n + 1 power supply lines to be shared, each pixel It is sufficient to arrange n by each of them and arrange one power supply line between pixels.

In the first and second embodiments, the four power supply lines V _DD , V _SS , signal A, and signal B extend in the row direction and have been described such that the pixels adjacent to the column direction are shared. As shown in the drawing, it may be arranged to extend in the column direction. In this case, the power lines are shared with the circuit arrangement of each pixel as the line symmetry with respect to the columns, and the same effects as in the first and second embodiments can be obtained. However, especially in the case of stripe arrangements as in the second embodiment, there is little layout margin for extending the wiring in the column direction. Therefore, it is preferable that the power supply lines are laid out so as to extend in the row direction.

Although the embodiment has been described using a reflective LCD, it is of course possible to apply the transparent LCD to a transparent pixel electrode and a holding circuit. However, in the transmissive LCD, since the portion where the metal wiring is arranged is shielded from light, a decrease in the aperture ratio cannot be avoided. Further, in the transmissive LCD, if the holding circuit is disposed under the pixel electrode, the transistors of the holding circuit and the selection circuit may malfunction due to the transmitted light. Therefore, it is necessary to form a light shielding film on the gates of all the transistors. Therefore, it is difficult to make aperture ratio high in a transmissive LCD.

On the other hand, the reflective LCD does not affect the aperture ratio even if any circuit is arranged under the pixel electrode. In addition, as in the transmissive liquid crystal display device, since there is no need to use a so-called backlight on the opposite side to the observer side, power for turning on the backlight is not required. Since the main purpose of the LCD having the holding circuit is to reduce the power consumption, it is preferable that the display device of the present invention is a reflective LCD suitable for low power consumption since no backlight is required.

In addition, although the said Example was demonstrated using the liquid crystal display device, this invention is not limited to this, It is applicable to various display devices, such as an organic electroluminescence display and an LED display device.

As described above, the active matrix display device of the present invention is an active matrix display device having a sustain circuit corresponding to a pixel electrode, wherein a power supply line connected to the sustain circuit extends in the row direction, for example, Since it is shared by the holding circuits corresponding to the pixel electrodes arranged in the direction and shared by the holding circuits corresponding to the pixel electrodes adjacent to the column direction, the number of power supply lines is halved as compared with the arrangement of the power supply lines for each row. Since the size can be reduced and the pixel size can be reduced, it can be said to be an active matrix display device having a holding circuit with higher precision.

In particular, since the shared power supply line supplies equal voltages to all the holding circuits, it can be shared across the row direction and the column direction.

In particular, the shared power supply line is disposed near pixels adjacent to the row or column direction, and the arrangement of the holding circuit in pixels adjacent to the row or column direction is axially or centered between pixels adjacent to the row or column direction. Since the wirings are arranged symmetrically with a shared power supply line interposed therebetween, the efficiency of layout can be improved, for example, the wiring connected to the holding circuit can be shortened from the shared power supply line.

1 is a circuit diagram showing a first embodiment of the present invention.

2 is a conceptual diagram showing a planar layout of a first embodiment of the present invention.

3 is a conceptual diagram showing a planar layout of a first embodiment of the present invention;

4 is a cross-sectional view of an embodiment of the present invention.

5 is a conceptual diagram showing a planar layout of a second embodiment of the present invention.

6 is a circuit diagram showing one pixel of a liquid crystal display device.

7 is a circuit diagram showing a display device having a conventional holding circuit.

8 is a circuit diagram showing one pixel of a liquid crystal display device having a conventional holding circuit.

<Explanation of symbols for the main parts of the drawings>

17: pixel electrode

40, 43: circuit selection circuit

70: pixel selection circuit

85: auxiliary capacity

110: holding circuit

Claims (10)

A plurality of pixel electrodes arranged in a matrix shape, a plurality of holding circuits disposed corresponding to the pixel electrodes, and a power supply line for supplying a predetermined voltage to the holding circuits, the voltages corresponding to data held by the holding circuits; In an active matrix display device which is supplied to the pixel electrode and performs display, The power supply line is shared by a holding circuit for pixel electrodes arranged in a predetermined direction and forming one line of the matrix, and is connected to a pixel electrode arranged in the predetermined direction and forming another one line of the matrix. An active matrix display device, which is commonly used in the sustain circuit. A pixel electrode arranged in a matrix shape, a plurality of gate signal lines arranged in a row direction, and a plurality of drain signal lines arranged in a column direction, wherein the pixel electrode is selected by a scan signal from the gate signal line; In an active matrix display device in which a video signal is supplied from a drain signal line, A first display circuit for supplying a signal corresponding to the video signal from the drain signal line to the pixel electrode selected by the scan signal input from the gate signal line; A holding circuit which is supplied with a predetermined voltage and holds a video signal from the drain signal line in response to a scanning signal input from the gate signal line, and supplies a signal corresponding to the signal from the holding circuit to the display electrode. With the second display circuit A circuit selection circuit for selectively connecting said first and second display circuits to said drain signal line in response to a circuit selection signal, A plurality of power supply lines for supplying a predetermined voltage to the sustain circuit extend in one direction of the matrix and are shared by the sustain circuit corresponding to the pixel electrodes arranged in the one direction and adjacent to the other direction in the matrix. An active matrix display device, which is shared by pixels. The method according to claim 1 or 2, At least two driving power lines extending in either direction of the matrix and supplying different driving voltages are connected to each of the holding circuits, And at least one of the driving power lines is shared by a plurality of pixels adjacent to different directions of the matrix. The method of claim 3, Capacitively coupling the driving power line shared by the pixels adjacent to each other to the pixel electrode of one pixel, and extending the region so that the driving power line is capacitively coupled to the pixel electrode of the other pixel. Active matrix display device. The method of claim 3, And overlapping the driving power supply line shared by the pixels adjacent to each other on the pixel electrode of one pixel, and forming an overlapping region formed by extending the driving power supply line on the pixel electrode of the other pixel. Active matrix display device. The method according to claim 1 or 2, At least two reference power lines extending in either direction of the matrix and supplying different reference voltages to each of the holding circuits, The holding circuit selects and supplies the reference voltage to the pixel electrode based on the held data; At least one of the reference power lines is shared by a plurality of pixels adjacent to different directions in a matrix. The method of claim 6, Capacitively coupling the reference power line shared by the pixels adjacent to each other to the pixel electrode of one pixel, and forming an extended region such that the reference power line is capacitively coupled to the pixel electrode of the other pixel. Active matrix display device. The method of claim 6, The reference power supply line shared by the pixels adjacent to each other is overlapped on the pixel electrode of one pixel, and the overlapping area formed by extending the reference power supply line on the pixel electrode of the other pixel is formed. Active matrix display device. The method according to claim 1 or 2, And said shared power supply line supplies the same voltage to all the holding circuits. The method according to claim 1 or 2, The shared power supply line is disposed near pixels adjacent to different directions in the matrix, The arrangement of the holding circuits in the pixels adjacent to the other direction in the matrix is symmetrically arranged with the shared power lines interposed between the pixels adjacent to the other direction in the matrix as the axis or the center. An active matrix display device.