KR100386253B1 - Write data conviction circuit for fpga register in using parity bit - Google Patents

Abstract

The present invention relates to a write data confirmation circuit of an FPI register using parity bits, and enables the FPI to detect errors in data written in the FPI register. To this end, the present invention comprises a parity generating unit for generating a parity by receiving data and a predetermined operation; A data and parity interface unit receiving the parity and the data of the parity generating unit and interfacing the data to an internal predetermined register; A data and parity writing unit in which a predetermined internal register is selected by a selection signal of a control unit, and data and parity written in the internal register by a write enable signal are written through the data and parity interface unit; A clock generator which receives a selection signal, a write enable signal, and a system clock signal output from the controller and processes the predetermined signal to generate a clock signal for detecting a data error; And a data error detection unit which is enabled by a clock signal of the clock generation unit, receives data and parity output from the data and parity writing unit, and processes the data and parity to detect a data error.

Description

WRITE DATA CONVICTION CIRCUIT FOR FPGA REGISTER IN USING PARITY BIT}

The present invention relates to a write data verification circuit of an FPI register using parity bits, and more particularly, to an FPI register that uses parity bits to detect an error of data written in the FPI register itself. And a write data confirmation circuit.

In general, data buses cannot be used at other addresses when occupied by one address. Therefore, data is written to the FPGA (FIELD PROGRAMMABLE ARRAY) register and read again to check for data errors. While no other address can be accessed, this prior art will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a conventional write data verification circuit of an FPI register. As shown in FIG. )Wow; A predetermined register is selected from the control unit 11 by the selection signal BYTE0_SEL generated by the combination of the address buses, and the data DT0 input through the data interface unit 10 by the write enable signal WREN. A data writing unit (12) for writing? DT7) to the selected register; The selection signal BYTE0_SEL and the read enable signal RDEN generated by the combination of the address buses generated from the control unit 11 and the data DATA0 to DATA7 written to the predetermined register of the data writing unit 12 are inputted. A data checking unit 13 which receives a predetermined operation and outputs the read data RDT0 to RDT7 according to the data interface unit 10; The control unit 11 controls the respective units as well as receives the read data RDT0 to RDT7 of the data checking unit 13 through a bus and detects an error. The operation of the conventional apparatus will be described. .

First, when the data DT0 to DT7 are written, the control unit 11 applies a selection signal BYTE0_SEL to the data writing unit 12 for selecting an arbitrary FP register, and then the data writing unit 12. Selects an internal FGF register by the selection signal BYTE0_SEL.

In this case, the controller applies the write enable signal WREN to the selected register of the data writing unit 12 to write the data DT0 to DT7, thereby inputting the data through the data interface unit 10. The data DT0 to DT7 to be written are written to the register of the data writing unit 12.

On the other hand, in order to detect an error of the data DATA0 to DATA7 written in a predetermined register of the data writing unit 12, the data checking unit 13 outputs a read enable signal RDEN output from the control unit 11; The NAND operation of the selection signal BYTE0_SEL and the data stored in the predetermined register of the data writing unit 12 outputs the read data RDT0 to RDT7 through the data interface unit 10.

In other words, after writing the data DT0 to DT7 in any of the FP registers selected by the controller 11, the FP A to detect whether there is an error in the written data DATA0 to DATA7. The register is accessed by the control unit 11 to detect a data error.

That is, in the prior art operating as described above, the data bus has a characteristic that it cannot be used at another address when occupied by one address. There is a problem that the data processing speed is reduced because the operation cannot be accessed by accessing the.

Accordingly, the present invention devised in view of the above-described problems uses a write data confirmation circuit of an FpgiA register using a parity bit that enables Fpgi itself to detect an error of data written to the Fpgi register. The purpose is to provide.

1 is a circuit diagram showing a configuration of a write data confirmation circuit of a conventional FP register.

Fig. 2 is a circuit diagram showing the configuration of the write data circuit of the FP register using the parity bits of the present invention.

FIG. 3 is a timing diagram for each part of the clock generation section in FIG.

***** Description of the symbols for the main parts of the drawings *****

100: data and parity interface unit 200: control unit

300: data and parity writing unit 400: clock generating unit

500: data error detection unit 600: parity generation unit

The present invention for achieving the above object is a parity generating unit for generating a parity by a predetermined operation on the input data; A data and parity interface unit for interfacing the parity of the parity generating unit and the data to an internal predetermined register; A data and parity writing unit in which a predetermined internal register is selected by a selection signal of a controller, and data and parity written in the internal register by the write enable signal are written through the data and parity interface units; A clock generator which processes a selection signal, a write enable signal, and a system clock signal output from the controller to generate a clock signal for data error detection; And a data error detection unit which is enabled by a clock signal of the clock generation unit, receives data and parity output from the data and parity writing unit, and processes the data and parity to detect a data error.

Hereinafter, operations and effects of the write data confirmation circuit of the FP register using the parity bit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram illustrating a write data confirmation circuit of an FPI register using the parity bits of the present invention. As shown in FIG. A parity generating unit 600 generated; A data and parity interface unit 100 which receives the parity bits of the parity generating unit 600 and the data EX1 and EX2 and interfaces them to internal registers; The predetermined internal register is selected by the selection signal BYTE0_SEL of the control unit 200, and the data DT0 to DT7 and parity inputted through the data and parity interface unit 100 by the write enable signal WREN. A data and parity writing unit 300 to which bits PARITY are written; The clock generator 400 receives the selection signal BYTE0_SEL, the write enable signal WREN, and the system clock signal SYSCLK from the controller 200 and processes the predetermined signal to generate a clock signal for data error detection. )Wow; Enabled by the clock signal of the clock generator 400, and receives data DATA0 to DATA7 and parity bits PARITY output from the data and parity writing unit 300 to detect and process data errors. A data error detection unit 500; The controller 200 is configured to collectively control each unit.

The parity generating unit 600 receives data DT0 to DT3 and DT4 to DT7 by four bits, respectively, to calculate first and second exclusive oval gates EX1 and (2). EX2); The first and second exotic oar gates EX1 and EX2 receive the output signals and are composed of a third exclusive oar gate EX3 that calculates the result.

The clock generator 400 may include a first AND gate AN1 that receives and selects a write enable signal WREN inverted from the selection signal BYTE0_SEL; A first deflip-flop DF10 that receives and maintains an output signal of the first AND gate AN1 and outputs the same in synchronization with a system clock signal SYDCLK; A second deflip-flop DF11 that receives and maintains an output signal of the first flip-flop DF10 and outputs it in synchronization with the system clock signal SYSCLK; A third deflip-flop DF12 that receives and maintains an output signal of the second flip-flop DF11 and outputs it in synchronization with the system clock signal SYSCLK; An AND gate (AN2) for receiving and outputting the output signal of the third deflip-flop (DF12) inverted from the output signal of the second deflip-flop (DF11); A fourth deflip-flop DF13 that receives and maintains the output signal of the AND gate AN2 and outputs in synchronization with the system clock signal SYSCLK.

The data error detection unit 500 receives the first and second five ora gates EX4 that receive the overall data DATA0 to DATA3 stored in a predetermined register of the data and parity writing unit 300 and perform an exclusive oracle operation. And a second exclusive oagate EX5 that receives the late data DATA4 to DATA7 and the parity bits PARITY stored in a predetermined register of the data and parity writing unit 300 and performs an exclusive oval operation. A third express oA gate EX6 that receives the output signals of the first and second express oV gates EX4 and EX5 and calculates the exclusive oval gate EX6; It consists of a deflip-flop (DF14) that receives and maintains the output signal of the school clock ore gate EX6 and outputs the error detection signal CHK_CLK according to the clock signal of the clock generator 400. The operation of the present invention configured as described above will be described.

First, before data is written to the FP register, the parity generator 600 receives 8-bit data DT0 to DT7 and performs a predetermined operation to output the parity bit.

That is, the first and second exotic oar gates EX1 and EX2 receive four data bits DT0 to DT3 and DT4 to DT7, respectively, and calculate and output an exclusive oval. The third exotic oar gate EX3 calculates the output signals of the first and second exotic oar gates EX1 and EX2 again by performing an exotic oval, and thus a parity bit. Create

In this case, the data and parity interface unit 100 receives the parity bits of the parity generating unit 600, the data EX1, and EX2, and interfaces them with internal registers, and the data and parity writing unit 100. In operation 300, a predetermined internal register is selected by the selection signal BYTE0 _SEL of the control unit 200, and data DT0 input through the data and parity interface unit 100 by the write enable signal WREN. DT7) and the parity bit (PARITY) are written.

Here, the data and parity writing unit 300 includes a plurality of registers. For the convenience of description, FIG. 2 shows only one register.

Meanwhile, in order to detect an error of data stored in the data and parity writing unit 300, the clock generator 400 may include a selection signal BYTE0_SEL and a write enable signal WREN output from the control unit 200. The system clock signal SYSCLK is received and processed in advance to generate a clock signal for data error detection.

That is, the AND gate AN1 receives and receives the selection signal BYTE0_SEL of FIG. 3A and the inverted write enable signal WREN of FIG. 3B of the controller 200. The flip-flop DF10 receives and maintains the output signal of the AND gate AN1 as shown in FIG. 3C, and outputs it in synchronization with the system clock signal SYDCLK. The output signal of the flip-flop DF10 is received and maintained, and is output as a signal as shown in FIG. 3D in synchronization with the system clock signal SYSCLK, and the flip-flop DF12 is a deflip-flop DF11. ) Is outputted as a signal such as (e) of FIG. 3 in synchronization with the system clock signal SYSCLK.

The AND gate AN2 receives and outputs the output signal of the flip-flop DF11 and the inverted output signal of the flip-flop DF12 to output a signal as shown in FIG. The flip-flop DF13 receives and maintains the output signal of the AND gate AN2, and outputs a clock signal in synchronization with the system clock signal SYSCLK.

Then, the data error detection unit 500 is enabled by the clock signal of the clock generator 400, and the data DATA 0 to DATA7 and the parity bit output from the data and parity writing unit 300. Receives a predetermined process and detects a data error.

That is, after the data and the data DT0 to DT7 stored in the predetermined register of the parity writing unit 300 are sequentially passed through the EXCLUV OA gates EX4 to EX6, the EXCLUV XV ora operation is performed. The operation signal is latched by the clock signal of the clock generator 400 in the flip-flop DF14 to finally output the error detection signal CHK_CLK.

If the data DT0 to DT7 are normally written in the corresponding registers of the data and the parity writing unit 300, the error detection signal CHK_CLK is always kept low, and one or more data ( If an error occurs in DT0 to DT7), the error detection signal CHK_CLK is in a 'high' state. That is, if the error detection signal is checked by the controller 200 and is 'low', the normal write operation is performed. In this case, it is determined that an error occurs in the write operation.

As described in detail above, the present invention has the effect of efficiently using the data bus by detecting the error of data written in the FPI register on its own without occupying the data bus.

Claims (5)

A parity generating unit generating parity by a predetermined operation of input data; A data and parity interface unit for interfacing the parity of the parity generating unit and the data to an internal predetermined register; A data and parity writing unit in which a predetermined internal register is selected by a selection signal of a controller, and data and parity written in the internal register by the write enable signal are written through the data and parity interface units; A clock generator which processes a selection signal, a write enable signal, and a system clock signal output from the controller to generate a clock signal for data error detection; And a data error detection unit enabled by a clock signal of the clock generation unit and configured to process data and parity output from the data and parity writing unit to detect a data error. Write data confirmation circuit of the register. The apparatus of claim 1, wherein the parity generating unit comprises: first and second exclusive oval gates that receive data by a predetermined bit and perform an exclusive oval operation respectively; And a third express oragate configured to receive an output signal of the first and second exotic oar gates and perform an operation on the output signal of the first and second exotic oar gates. The display device of claim 1, wherein the clock generator comprises: a first AND gate configured to receive and perform an operation of receiving a write enable signal inverted from the selection signal; A first deflip-flop that receives and maintains an output signal of the first AND gate, and outputs in synchronization with a system clock signal; A second flip-flop that receives and maintains an output signal of the first flip-flop and outputs it in synchronization with the system clock signal; A third flip-flop that receives and maintains an output signal of the second flip-flop and outputs it in synchronization with the system clock signal; An AND gate for receiving and outputting the output signal of the third deflip-flop, which is inverted from the output signal of the second deflip-flop; And a fourth deflip-flop which receives and maintains the output signal of the AND gate, and outputs in synchronization with the system clock signal. 2. The apparatus of claim 1, wherein the data error detection unit comprises: a first exploit oragate configured to receive the entire data stored in a predetermined register of the data and the parity writing unit and perform an exotic or oval operation; A second express oragate for receiving late half data and parity stored in a predetermined register of the data and parity writing unit and performing an exclusive orphan operation; A third exotic oar gate configured to receive an output signal of the first and second exotic oar gates and perform an exclusive oval operation; A F-PAI using parity bits, characterized in that it is configured to receive and maintain the output signal of the third exotic oar gate and output an error detection signal according to the clock signal of the clock generator. Write data confirmation circuit of the register. The data error detection unit of claim 1 or 4, wherein the data error detection unit outputs an error detection signal of 'low' when data is normally written to a corresponding register of the data and the parity writing unit, and, if an error occurs in one or more data. The error detection signal is output in a 'high' state, the write data verification circuit of the FP A register using a parity bit.