KR100386159B1 - 레이저 간섭계를 이용한 반도체 다층 배선 구조 형성 방법 - Google Patents
레이저 간섭계를 이용한 반도체 다층 배선 구조 형성 방법 Download PDFInfo
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- KR100386159B1 KR100386159B1 KR10-2001-0007752A KR20010007752A KR100386159B1 KR 100386159 B1 KR100386159 B1 KR 100386159B1 KR 20010007752 A KR20010007752 A KR 20010007752A KR 100386159 B1 KR100386159 B1 KR 100386159B1
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- South Korea
- Prior art keywords
- etching
- depositing
- laser interferometer
- dielectric material
- low dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000010410 layer Substances 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 45
- 239000003989 dielectric material Substances 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 8
- 238000001636 atomic emission spectroscopy Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (5)
- 반도체 기판상에 확산 방지층을 증착하는 단계와;상기 확산 방지층상에 층간 절연막인 제 1 저유전 물질을 증착하는 단계와;상기 제 1 저유전 물질상에 식각 저지층을 증착하는 단계와;상기 식각 저지층상에 층간 절연막인 제 2 저유전 물질을 증착하는 단계와;상기 제 2 저유전 물질상에 트렌치용 마스크를 증착하여 포토레지스트 패턴을 형성하는 단계와;레이저 간섭계(LASER interferometer)를 이용하여 상기 식각 저지층까지 트렌치를 식각하는 제 1 식각 단계와;상기 트렌치용 마스크를 제거하고 비아용 마스크를 증착하여 포토레지스트 패턴을 형성하는 단계와;상기 레이저 간섭계를 이용하여 상기 확산 방지층까지 비아 홀을 식각하는 제 2 식각 단계와;상기 확산 방지층을 식각하는 제 3 식각 단계를 포함하는 것을 특징으로 하는 레이저 간섭계를 이용한 반도체 다층 배선 구조 형성 방법.
- 제 1 항에 있어서,상기 제 1 식각 단계는,레이저 광원의 입사파와 반사파의 경로차에 따라 상기 제 2 저유전 물질의식각율을 계산하고, 상기 식각율에 따른 식각 종말점을 검출하여 상기 트렌치 식각 공정을 정지시키는 단계인 것을 특징으로 하는 레이저 간섭계를 이용한 반도체 다층 배선 구조 형성 방법
- 제 1 항 또는 제 2 항에 있어서,상기 제 1 식각 단계는,상기 트렌치 식각 공정 수행시에는 저선택비의 식각율을 적용한 식각 공정을 수행하고, 상기 레이저 간섭계를 이용하여 상기 식각 종말점을 검출한 후에는 고선택비 식각율을 적용한 식각 공정을 수행하는 것을 특징으로 하는 레이저 간섭계를 이용한 반도체 다층 배선 구조 형성 방법.
- 제 3 항에 있어서,상기 식각 종말점은, 상기 식각 저지층이 노출되기 직전의 시점인 것을 특징으로 하는 레이저 간섭계를 이용한 반도체 다층 배선 구조 형성 방법.
- 제 1 항에 있어서,상기 식각 저지층은 SiN, WN, TaN, Si3N4중 하나인 것을 특징으로 하는 레이저 간섭계를 이용한 반도체 다층 배선 구조 형성 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0007752A KR100386159B1 (ko) | 2001-02-16 | 2001-02-16 | 레이저 간섭계를 이용한 반도체 다층 배선 구조 형성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0007752A KR100386159B1 (ko) | 2001-02-16 | 2001-02-16 | 레이저 간섭계를 이용한 반도체 다층 배선 구조 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020067259A KR20020067259A (ko) | 2002-08-22 |
KR100386159B1 true KR100386159B1 (ko) | 2003-06-02 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR10-2001-0007752A Expired - Fee Related KR100386159B1 (ko) | 2001-02-16 | 2001-02-16 | 레이저 간섭계를 이용한 반도체 다층 배선 구조 형성 방법 |
Country Status (1)
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KR (1) | KR100386159B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101307247B1 (ko) * | 2012-09-26 | 2013-09-11 | 가톨릭대학교 산학협력단 | 보상구조물을 이용한 실리콘웨이퍼 에칭 방법 및 이를 이용한 에너지 하베스터 제조 방법 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0239536A (ja) * | 1988-07-29 | 1990-02-08 | Hitachi Ltd | 配線構造体及びその製造方法 |
JPH06267911A (ja) * | 1993-03-12 | 1994-09-22 | Oki Electric Ind Co Ltd | 配線パターン形成方法 |
US5612254A (en) * | 1992-06-29 | 1997-03-18 | Intel Corporation | Methods of forming an interconnect on a semiconductor substrate |
US6071813A (en) * | 1997-10-20 | 2000-06-06 | Advanced Micro Devices, Inc. | Method and system for electrical coupling to copper interconnects |
KR20000033546A (ko) * | 1998-11-24 | 2000-06-15 | 윤종용 | 다마신 공정으로 형성된 도전성 배선을 구비하는 반도체장치 및그 제조방법 |
-
2001
- 2001-02-16 KR KR10-2001-0007752A patent/KR100386159B1/ko not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0239536A (ja) * | 1988-07-29 | 1990-02-08 | Hitachi Ltd | 配線構造体及びその製造方法 |
US5612254A (en) * | 1992-06-29 | 1997-03-18 | Intel Corporation | Methods of forming an interconnect on a semiconductor substrate |
JPH06267911A (ja) * | 1993-03-12 | 1994-09-22 | Oki Electric Ind Co Ltd | 配線パターン形成方法 |
US6071813A (en) * | 1997-10-20 | 2000-06-06 | Advanced Micro Devices, Inc. | Method and system for electrical coupling to copper interconnects |
KR20000033546A (ko) * | 1998-11-24 | 2000-06-15 | 윤종용 | 다마신 공정으로 형성된 도전성 배선을 구비하는 반도체장치 및그 제조방법 |
Also Published As
Publication number | Publication date |
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KR20020067259A (ko) | 2002-08-22 |
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