KR100386159B1 - Method for providing a multi layer in a semiconductor device by using laser interferometer - Google Patents

Abstract

The present invention relates to a method for forming a semiconductor multilayer wiring structure using a laser interferometer.

The present invention comprises the steps of depositing a diffusion barrier layer on a semiconductor substrate; Depositing a first low dielectric material, which is an interlayer insulating film, on the diffusion barrier layer; Depositing an etch stop layer on the first low dielectric material; Depositing a second low dielectric material, an interlayer insulating film, on the etch stop layer; Depositing a trench mask on the second low dielectric material to form a photoresist pattern; Etching the trench to the etch stop layer using a laser interferometer; Removing the trench mask and depositing a via mask to form a photoresist pattern; A second etching step of etching the via hole to the diffusion barrier layer using a laser interferometer; And a third etching step of etching the diffusion barrier layer. Therefore, the present invention can accurately determine the etch stop time by the laser interferometer, it is possible to implement the thickness of the etch stop layer as thin as possible, it is possible to prevent the rise of the overall dielectric constant and solve the signal delay problem to improve product reliability It has an effect.

Description

METHOD FOR PROVIDING A MULTI LAYER IN A SEMICONDUCTOR DEVICE BY USING LASER INTERFEROMETER}

The present invention relates to a method for forming a semiconductor multilayer wiring structure, and more particularly, to a method for forming a semiconductor multilayer wiring structure using a laser interferometer.

Due to the rapid development of electronic technology, a multilayer wiring structure has been introduced into the semiconductor manufacturing field, and a more precise and complicated multilayer wiring structure forming technology is applied to the semiconductor manufacturing field to accommodate device miniaturization, large capacity, and high integration.

However, such a multilayer wiring structure has raised a problem that the capacitance between wirings of the same layer is increased due to the reduction of the distance between wirings, thereby causing signal delay between wirings. This signal delay problem is a very sharp problem that influences the operation characteristics of the device, which reduces wiring thickness and increases the thickness of the interlayer insulating film to reduce the capacitance between the interlayer wirings, that is, the wiring material having low resistivity, for example, copper. And various interlayer insulating films having low relative dielectric constants are required.

However, in the case of copper, there is a problem that a lot of difficulties in dry etching because the vapor pressure of the etching by-products is low.

The damascene process is a process for efficiently patterning copper interconnects while solving these dry etching difficulties, including a series of processes for forming and filling holes for semiconductor multilayer interconnection structures. In such a damascene process, an etch stop layer is essentially used, and a material having a low dielectric constant of a thin film, for example, silicon nitride, is used as a typical etch stop layer (the reason for using a thin film low dielectric material is because If the dielectric constant of the layer increases, the dielectric constant of the interlayer insulating film also increases).

In this case, an end point detector (EPD) technique using optical emission spectroscopy (OES) is used as a method of etching the etch stop layer. That is, the conventional etching method of the etch stop layer employs a method of detecting the reactant in the plasma and determining the etch endpoint by changing the reactant.

However, when the conventional method is employed, a problem arises in that the etch stop layer, which is a thin film low dielectric material, may be excessively etched.

In other words, the general EPD technique stops the etching process only after detecting the exposure of the nitride film, which raises a problem that the etch stop layer may be lost due to inaccurate etching endpoint determination. This problem has resulted in the fact that the thickness of the etch stop layer that determines the overall dielectric constant of the semiconductor manufacturing process has to be set thick, and thus the overall dielectric constant increases, resulting in a problem that the product yield is reduced.

Accordingly, the present invention has been made to solve the above-described problem, and during the etching process of the semiconductor multilayer wiring structure forming process, the etch stop layer is exposed by determining the etch end point according to the path difference between the incident wave and the reflected wave of the laser light source. The purpose of the present invention is to provide a method for forming a semiconductor multilayer interconnection structure using a laser interferometer that stops the etching process beforehand and performs a more accurate etching stop process to form a semiconductor multilayer interconnection structure that can solve a low dielectric constant and a signal delay problem. have.

In order to achieve this object, the present invention comprises the steps of depositing a diffusion barrier layer on a semiconductor substrate; Depositing a first low dielectric material, which is an interlayer insulating film, on the diffusion barrier layer; Depositing an etch stop layer on the first low dielectric material; Depositing a second low dielectric material, an interlayer insulating film, on the etch stop layer; Depositing a trench mask on the second low dielectric material to form a photoresist pattern; Etching the trench to the etch stop layer using a laser interferometer; Removing the trench mask and depositing a via mask to form a photoresist pattern; A second etching step of etching the via hole to the diffusion barrier layer using a laser interferometer; It provides a method for forming a semiconductor multilayer wiring structure using a laser interferometer comprising a third etching step of etching the diffusion barrier layer.

1A to 1J illustrate a process of forming a semiconductor multilayer wiring structure using a laser interferometer according to a preferred embodiment of the present invention;

2 is a view for explaining a laser interferometer according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100: substrate

102: diffusion barrier layer

104, 108: low dielectric material

106: etching stop layer

110: mask

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1A to 1J are diagrams for describing a process of forming a semiconductor multilayer wiring structure using a laser interferometer according to a preferred embodiment of the present invention.

First, a diffusion barrier layer 102 is deposited on the semiconductor substrate 100 (FIG. 1A). Silicon nitride may be used for the diffusion barrier layer 102.

Next, a first low dielectric material 104 as an interlayer insulating film is deposited on the diffusion barrier layer 102 formed through the process of FIG. 1A (FIG. 1B). The low dielectric material 104 is an organic material or an inorganic material. Preferably, SiOF, HSQ, MSQ, HOSP, polymer, or the like may be used. In addition, depending on the deposition method, it can be divided into CVD technique and "Spin on deposition" technique.

In FIG. 1C, an etch stop layer 106, eg, silicon nitride, is deposited on the first low dielectric material 104 formed in FIG. 1B. In this case, the etch stop layer 106 may be SiN, WN, TaN, etc., preferably Si ₃ N ₄ may be used.

In FIG. 1D, a second low dielectric material 108, which is an interlayer insulating film similar to the process of FIG. 1B, is deposited on the etch stop layer 106 formed (FIG. 1D).

A trench mask 110 is deposited on the second low dielectric material 108 to form a photoresist pattern (FIGS. 1E and 1F).

Then, in FIG. 1G, the trench is etched to the etch stop layer 106 by dry etching using, for example, plasma. In this case, such an etching process may be implemented using a laser interferometer according to the present invention.

The laser interferometer refers to a technology in which a reception method of determining an angle of arrival of an optical signal by measuring a path difference between an incident wave and a reflected wave by entering a laser light source and comparing a phase difference of a received laser signal.

2 is a diagram for explaining such a laser interferometer.

The etching thickness is determined by 2dsin θ = nX. Where X is the wavelength, θ is the incident angle, and n is the refractive index. Since the etching thickness can be known by the above equation, the thickness can be accurately predicted and the etching thickness can be known in real time.

As shown in FIG. 2, the process of FIG. 1G determines the etch rate of the second low dielectric material 108 according to the path difference 2dsinθ between the incident wave and the reflected wave of the laser light source incident on the second low dielectric material 108. The method may include calculating and stopping the trench etching process by detecting an etching end point according to the etching rate, that is, a time point just before the etching stop layer 106 is exposed.

In the etching step of FIG. 1G, the etching process using the low selectivity etching rate is performed when the trench etching process is performed, and the etching step using the high selectivity etching rate is detected after detecting the etching end point using a laser interferometer. It is characterized by performing a process.

Meanwhile, in FIG. 1H, the trench mask 110 formed in FIG. 1E is removed and the via mask 110 is deposited to form a photoresist pattern.

Subsequently, in FIG. 1I, the via hole is etched up to the diffusion barrier layer 102 using the above-described laser interferometer, and in FIG. 1J, the diffusion barrier layer 102 is etched to form a multilayer wiring structure according to the present invention.

As described above, the present invention is implemented to determine the etch stop time when forming a semiconductor multilayer wiring structure using a laser interferometer rather than the conventional optical emission spectroscopy (OES).

Therefore, the present invention can accurately determine the etch stop time, it is possible to implement the thickness of the etch stop layer as thin as possible, there is an effect that can improve the product reliability by preventing the increase in the overall dielectric constant and solve the signal delay problem. .

Claims (5)

Depositing a diffusion barrier layer on the semiconductor substrate; Depositing a first low dielectric material that is an interlayer insulating film on the diffusion barrier layer; Depositing an etch stop layer on the first low dielectric material; Depositing a second low dielectric material, an interlayer insulating film, on the etch stop layer; Depositing a trench mask on the second low dielectric material to form a photoresist pattern; Etching the trench up to the etch stop layer using a laser interferometer; Removing the trench mask and depositing a via mask to form a photoresist pattern; A second etching step of etching the via hole to the diffusion barrier layer using the laser interferometer; And a third etching step of etching the diffusion barrier layer. The method of claim 1, The first etching step, Calculating an etch rate of the second low dielectric material according to a path difference between an incident wave and a reflected wave of a laser light source, detecting an etch endpoint according to the etch rate, and stopping the trench etching process; Method of forming semiconductor multilayer wiring structure using The method according to claim 1 or 2, The first etching step, When the trench etching process is performed, an etch process using a low selectivity etch rate is performed, and after detecting the etch endpoint using the laser interferometer, an etch process using a high selectivity etch rate is performed. A method for forming a semiconductor multilayer wiring structure using a laser interferometer. The method of claim 3, wherein The etching end point is a time point immediately before the etching stop layer is exposed, characterized in that the method for forming a semiconductor multilayer wiring structure using a laser interferometer. The method of claim 1, The etch stop layer is a method for forming a semiconductor multilayer wiring structure using a laser interferometer, characterized in that one of SiN, WN, TaN, Si ₃ N ₄ .