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KR100384314B1 - Method and device for mounting electronic component on circuit board - Google Patents

Method and device for mounting electronic component on circuit board Download PDF

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Publication number
KR100384314B1
KR100384314B1 KR10-1999-7005885A KR19997005885A KR100384314B1 KR 100384314 B1 KR100384314 B1 KR 100384314B1 KR 19997005885 A KR19997005885 A KR 19997005885A KR 100384314 B1 KR100384314 B1 KR 100384314B1
Authority
KR
South Korea
Prior art keywords
circuit board
electronic component
thermosetting resin
electrode
resin sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-1999-7005885A
Other languages
Korean (ko)
Other versions
KR20000062375A (en
Inventor
니시다가즈토
Original Assignee
마츠시타 덴끼 산교 가부시키가이샤
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Publication date
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Publication of KR20000062375A publication Critical patent/KR20000062375A/en
Application granted granted Critical
Publication of KR100384314B1 publication Critical patent/KR100384314B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

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  • Engineering & Computer Science (AREA)
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Abstract

IC칩(1)을 회로기판(4)에 구성요소를 배치하고 접속하는 경우에, IC칩상의 전극(2)에 범프(3)를 형성하고, 절연성의 도전입자가 없는 열경화성 수지(6)를 회로기판의 전극과 범프 사이에 개재시키면서 범프와 회로기판이 전극의 위치를 맞추어, 가열된 헤드(8)에 의하여 IC칩을 회로기판에 1 범프당 20gf 이상의 가압력으로 가압하여, IC칩 및 기판의 휨을 교정하면서, IC칩과 회로기판 사이에 개재하는 수지를 경화하여, IC칩과 회로기판을 접합한다.In the case where the IC chip 1 is disposed and connected to the circuit board 4, the bumps 3 are formed on the electrodes 2 on the IC chip, and the thermosetting resin 6 without insulating conductive particles is formed. The bumps and the circuit boards are positioned between the electrodes and the bumps of the circuit board while the electrodes are positioned so as to press the IC chip to a circuit board with a pressing force of 20 gf or more per bump by the heated head 8, thereby While correcting the warpage, the resin interposed between the IC chip and the circuit board is cured to join the IC chip and the circuit board.

Description

회로기판에의 전자부품 실장방법 및 장치{METHOD AND DEVICE FOR MOUNTING ELECTRONIC COMPONENT ON CIRCUIT BOARD}METHOD AND DEVICE FOR MOUNTING ELECTRONIC COMPONENT ON CIRCUIT BOARD}

오늘날, 전자회로기판은, 모든 제품에 사용되게 되며, 날이갈수록 그 성능이 향상하여, 회로기판상에서 사용되는 주파수도 높아지고 있으며, 임피이던스가 낮아지는 플립칩(flip chip) 실장은 고주파를 사용하는 전자기기에 적합한 실장방법으로 되어 있다. 또 휴대기기가 증가하므로, 회로기판에 IC칩을 패키지가 아닌 나(裸)형 상태 그대로 탑재하는 플립칩 실장이 추구되고 있다. 이를 위하여 IC칩 그대로의 상태에서 단체로 회로기판에 탑재하였을 때의 IC칩이나, 전자기기 및 플랫패널 디스플레이(flat panel display)에 실장한 IC칩에는, 일정수의 불량품이 섞여있다. 또, 상기 플립칩 이외에도 CSP(Chip Size Package), BGA(Ball Grid Array) 등을 사용할 수 있도록 되어 있다.Today, electronic circuit boards are used in all products, and their performance improves day by day, the frequency used on circuit boards increases, and the impedance of flip chip mounting with low impedance is high-frequency electronics. The mounting method is suitable for the equipment. In addition, as the number of portable devices increases, flip chip mounting in which an IC chip is mounted on a circuit board as it is, rather than a package, is being pursued. For this purpose, a certain number of defective products are mixed in the IC chip when the IC chip is mounted on a circuit board in the same state as the IC chip, or the IC chip mounted on an electronic device and a flat panel display. In addition to the flip chip, a chip size package (CSP), a ball grid array (BGA), and the like can be used.

종래의 전자기기의 회로기판에 IC칩을 접합하는 방법(종래예 1)으로서는 일본국 특공평 06-66355호 공보등에 의하여 게재된 것이 있다. 이것을 도 13에 나타내었다. 도 13에 도시한 바와 같이, 범프(73)를 형성한 IC칩(71)에 Ag페이스트(paste)(74)를 전사하여 회로기판(76)의 전극(75)에 접속한 다음 Ag페이스트(74)를 경화한 후, 밀봉재(78)를 IC칩(71)과 회로기판(36) 사이에 흘러 들어가게 하는 방법이 일반적으로 알려져 있다.As a method (conventional example 1) for joining an IC chip to a circuit board of a conventional electronic device, there is one published by Japanese Patent Application Laid-Open No. 06-66355. This is shown in FIG. 13. As shown in FIG. 13, the Ag paste 74 is transferred to the IC chip 71 having the bumps 73 formed thereon, connected to the electrode 75 of the circuit board 76, and then the Ag paste 74 formed thereon. ) Is generally known to allow the sealing material 78 to flow between the IC chip 71 and the circuit board 36 after curing.

또, 액정 디스플레이에 IC칩을 접합하는 방법(종래예 2)으로서, 도 14에 도시한 일본국 특공소 62-6652호 공보와 같이, 이방성 도전필름(80)을 사용하는 것으로서, 절연성 수지(83)속에 도전성 알갱이(82)를 첨가하여 구성하는 이방성 도전접착제층(81)을 분리기(85)로부터 박리하여 기판이나 액정 디스플레이(84)의 유리에 도포하고, IC칩(28)을 열압착함으로써, Au범프(87)의 아래 이외의 IC칩(86)의 하면과 기판(84) 사이에 상기 이방성 도전접착제층(81)이 개재되어 있는 반도체 칩의 접속구조가, 일반적으로 알려져 있다.In addition, as a method (conventional example 2) of bonding an IC chip to a liquid crystal display, an anisotropic conductive film 80 is used as in Japanese Patent Application Laid-Open No. 62-6652 shown in FIG. ) By peeling the anisotropic conductive adhesive layer 81 formed by adding the conductive grains 82 into the separator 85 from the separator 85 and applying it to the glass of the substrate or the liquid crystal display 84, and thermally compressing the IC chip 28. The connection structure of the semiconductor chip in which the said anisotropic conductive adhesive layer 81 is interposed between the lower surface of IC chip 86 other than the bottom of Au bump 87 and the board | substrate 84 is generally known.

제3종래예로서는, UV경화수지를 기판에 도포하고, 그 위에 IC칩을 장착하여 가압하면서, UV조사함으로써 양자 사이의 수지를 경화하고, 그 수축력에 의하여 양자 사이의 접촉을 유지하는 방법이 공지되어 있다.As a third conventional example, a method is known in which a UV curable resin is applied to a substrate, an IC chip is mounted thereon, and pressurized, thereby curing the resin between them by UV irradiation, and maintaining the contact between them by the shrinkage force. have.

이와 같이, IC칩을 접합하려면 플랫패키지와 같은 IC칩을 리이드프레임(lead frame)상에 다이본딩(die bonding)하고, IC칩의 전극과 리이드프레임을 와이어본딩(wire bonding)하여 연결하고, 수지성형하여 패키지를 형성한 다음, 크리임(cream) 땜납을 회로기판에 인쇄하고, 그 위에 플랫패키지 IC를 탑재하여 리플로우(reflow)하는 공정을 실시함으로써 상기 접합을 하여 왔다. 이들 SMT(Surface Mount Technology)라고 하는 공법에서는, 공정이 길고, 생산에 장시간을 필요로 하여, 회로기판을 소형화하는 것이 곤란하였다. 예컨대, IC칩은 플랫팩에 밀봉된 상태에서는, IC칩의 약 4배 정도의 면적을 필요로 하므로, 소형화를 방해하는 요인으로 되고 있다.As described above, in order to bond an IC chip, an IC chip such as a flat package is die bonded on a lead frame, and an electrode and a lead frame of the IC chip are wire-bonded to each other, and a resin The bonding has been performed by forming a package by forming a package, then printing a cream solder on a circuit board, and carrying a reflow process by mounting a flat package IC thereon. In these construction methods called SMT (Surface Mount Technology), the process is long, requires a long time for production, and it is difficult to miniaturize the circuit board. For example, the IC chip requires about four times the area of the IC chip in a sealed state with the flat pack, which is a factor that hinders miniaturization.

이에 대하여, 공정의 단축과 소형 경량화를 위하여, IC칩을 나형의 상태에서 직접으로 기판에 탑재하는 플립칩공법을 최근에 와서 사용할 수 있도록 되었다. 이 플립칩공법은, IC칩에의 범프형성, 범프레벨링(bump levelling), AgㆍPd 페이스트전사, 실장, 검사, 밀봉수지에 의한 밀봉, 검사 등을 하는 스터드ㆍ범프ㆍ본딩(studㆍbumpㆍbonding)(SBB)이나, IC칩에의 범프형성과 기판으로의 UV경화수지 도포를 병행하여 실행한 후, 실장, 수지의 UV경화, 검사를 하는 UV수지 접합과 같은 많은 공법이 개발되고 있다.On the other hand, in order to shorten the process and reduce the size and weight, the flip chip method for mounting an IC chip directly on a substrate in a spiral form has recently come to be used. The flip chip method includes stud bump bump bonding for bump formation, bump leveling, Ag / Pd paste transfer, mounting, inspection, sealing by sealing resin, inspection, etc. to an IC chip. Many processes have been developed, such as bonding (SBB), bump formation to IC chips, and application of UV curable resin to a substrate, followed by UV resin bonding, mounting, UV curing, and inspection.

그런데, 어느 공법에 있어서도 IC칩의 범프와 기판의 전극을 접합하는 페이스트의 경화나 밀봉수지의 도포경화에 시간이 걸려서 생산성이 나쁘다고 하는 결점을 갖고 있었다. 또한, 회로기판에 세라믹이나 유리를 사용할 필요가 있어 고가인 결점을 갖고 있었다. 종래예 1과 같은 도전성 페이스트를 접합재로 사용하는 공법에 있어서는, 그 전사량을 안정화하기 위하여, IC칩의 범프는 레벨링하여, 평탄화하고 나서 사용할 필요가 있었다.By the way, in either method, there was a drawback that the productivity was poor due to the hardening of the paste bonding the bump of the IC chip and the electrode of the substrate and the application of the sealing resin. In addition, it is necessary to use ceramic or glass for the circuit board, which has an expensive drawback. In the method using the same conductive paste as that of the conventional example 1, in order to stabilize the transfer amount, the bumps of the IC chip are leveled and planarized. It was necessary to use.

또, 종래예 2와 같은 이방성 도전접착제에 의한 접합구조에 있어서는 회로기판의 기재(基材)로서 유리를 사용하는 것이 개발되고 있으나. 도전성 접착제 중의 도전입자를 균일하게 분산하는 것이 곤란하고, 입자의 분산 이상에 의하여 단락의 원인으로 된다거나, 도전성 접착제가 고가로 되거나 하였다.Moreover, in the joining structure by the anisotropic conductive adhesive like the conventional example 2, using glass as a base material of a circuit board is developed. It is difficult to uniformly disperse the conductive particles in the conductive adhesive, which causes short circuits or the conductive adhesive becomes expensive due to abnormal dispersion of the particles.

또, 종래예 3과 같이 UV경화수지를 사용하여 접합하는 방법에 있어서는, 범프의 높이의 불규칙한 분포를 ±1(㎛) 이하로 해야 하며, 또, 수지기판(유리에폭시기판) 등의 평면도가 나쁜 기판에는 접합할 수 없다고 하는 문제가 있었다. 또, 땜납을 사용하는 방법에 있어서도, 접합 후에 기판과 IC칩의 열팽창 수축차를 완화하기 위하여 밀봉수지를 유입경화할 필요가 있었다. 이 수지밀봉을 위해서는, 2∼4 시간을 필요로 하여, 생산성이 극히 나쁘다고 하는 문제가 있었다.In addition, in the method of joining using UV-curable resin as in the conventional example 3, the irregular distribution of the height of the bumps should be ± 1 (µm) or less, and the flatness of the resin substrate (glass epoxy substrate) or the like is poor. There was a problem that the substrate could not be bonded. Also in the method of using solder, it was necessary to harden the sealing resin in order to alleviate the thermal expansion shrinkage difference between the substrate and the IC chip after bonding. This resin sealing required 2 to 4 hours and had the problem that productivity was extremely bad.

본 발명은, 상기한 종래의 문제점에 비추어서, 회로기판과 IC칩을 접합한 다음에, IC칩과 기판 사이에 유입하는 밀봉수지공정이나 범프의 높이를 일정하게 가지런하게 하는 범프레벨링공정을 필요로 하지 않고, IC칩을 기판에 생산성이 좋게, 또한 높은 신뢰성으로 접합하는 회로기판에의 IC칩의 실장방법 및 장치를 제공하는 것을 목적으로 한다.In view of the above conventional problems, the present invention requires a step of bonding a circuit board and an IC chip, followed by a sealing resin step flowing in between the IC chip and the board, or a bump leveling step for uniformly raising the height of the bumps. It is an object of the present invention to provide a method and apparatus for mounting an IC chip on a circuit board for bonding the IC chip to the substrate with high productivity and with high reliability.

또, 본 발명은, 상기한 종래의 문제점을 감안하여, 회로기판과 전자부품을 생산성 좋게 직접 접합하는 회로기판에의 전자부품의 실장방법 및 장치를 제공하는 것을 목적으로 한다.Another object of the present invention is to provide a method and apparatus for mounting an electronic component on a circuit board for directly and efficiently joining a circuit board and an electronic component in view of the above-described conventional problems.

본 발명은 전자회로용 프린트기판에 전자부품, 예컨대, IC칩이나 표면탄성파(SAW)장치 등을 단체(單體)[IC칩의 경우에는 베어(bare)IC]상태에서 실장(배치접속)하는 회로기판에의 전자부품의 실장방법 및 그 장치에 관한 것이다.According to the present invention, an electronic component such as an IC chip, a surface acoustic wave (SAW) device, or the like is mounted on a printed circuit board for electronic circuits in a single state (bare IC in the case of an IC chip). A method for mounting an electronic component on a circuit board and an apparatus therefor.

본 발명의 이들, 그 밖의 목적과 특징은, 첨부된 도면에 대한 바람직한 실시형태에 관련한 다음의 기술로부터 명백해 질 것이다. 이 도면에 있어서는,도 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J는 각기 본 발명의 제1실시형태에 관한 회로기판에의 전자부품 예컨대 IC칩의 실장방법을 나타낸 설명도이며,These and other objects and features of the present invention will become apparent from the following description in connection with the preferred embodiments of the accompanying drawings. In the drawings, FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, and 1J each show a method of mounting an electronic component such as an IC chip on a circuit board according to the first embodiment of the present invention. Illustrative

도 2A, 2B, 2C, 2D, 2E, 2F, 2G는 각기 본 발명의 제1실시형태의 실장방법에 있어서, IC칩의 와이어본더(wire bonder)를 사용한 범프(돌기전극)형성공정을 나타낸 설명도이며,2A, 2B, 2C, 2D, 2E, 2F, and 2G respectively illustrate a bump (protrusion electrode) forming process using a wire bonder of an IC chip in the mounting method of the first embodiment of the present invention. Degrees,

도 3A, 3B, 3C는 각기 본 발명의 제1실시형태에 관한 실장방법에 있어서, 회로기판과 IC칩의 접합공정을 나타낸 설명도이며,3A, 3B, and 3C are explanatory views each showing a bonding process between a circuit board and an IC chip in the mounting method according to the first embodiment of the present invention.

도 4A, 4B, 4C는 각기 본 발명의 제1실시형태의 실장방법에 있어서 회로기판과 IC칩의 접합공정을 나타낸 설명도이며,4A, 4B, and 4C are explanatory views each showing a joining process of a circuit board and an IC chip in the mounting method of the first embodiment of the present invention.

도 5A, 5B, 5C, 5D, 5E, 5F는 각기 본 발명의 제1실시형태의 실장방법에 있어서 열경화성 수지 시이트를 대신하여 이방성 도전막을 사용하는 경우에 있어서, 회로기판과 IC칩의 접합공정을 도시한 설명도이며,5A, 5B, 5C, 5D, 5E, and 5F each show a bonding process between a circuit board and an IC chip in the case of using an anisotropic conductive film instead of the thermosetting resin sheet in the mounting method of the first embodiment of the present invention. Illustrated for illustration,

도 6은 본 발명의 제1실시형태에 있어서 도 5의 실시형태에서의 회로기판과 IC칩의 접합공정을 도시한 설명도이며,FIG. 6 is an explanatory diagram showing a bonding process between a circuit board and an IC chip in the embodiment of FIG. 5 in the first embodiment of the present invention; FIG.

도 7A, 7B, 7C는 각기 본 발명의 제2실시형태에 관한 실장방법에 있어서, 회로기판과 IC칩의 접합공정을 도시한 설명도이며,7A, 7B, and 7C are explanatory views showing the bonding process of a circuit board and an IC chip in the mounting method which concerns on 2nd Embodiment of this invention, respectively,

도 8A, 8B, 8C는 각기 본 발명의 제2실시형태에 관한 실장방법에 있어서, 회로기판과 IC칩의 접합공정을 도시한 설명도이며,8A, 8B, and 8C are explanatory views showing the bonding process of a circuit board and an IC chip in the mounting method which concerns on 2nd Embodiment of this invention, respectively,

도 9A, 9B, 9C, 9D, 9E는 각기 본 발명의 제3실시형태의 실장방법에 있어서, 회로기판과 IC칩의 접합공정을 도시한 설명도이며,9A, 9B, 9C, 9D, and 9E are explanatory views showing a bonding process between a circuit board and an IC chip in the mounting method of the third embodiment of the present invention, respectively.

도 10A, 10B, 10C, 10D, 10E, 10F는 각기 본 발명의 제4실시형태의 실장방법에 있어서, 회로기판과 IC칩의 접합공정을 도시한 설명도이며,10A, 10B, 10C, 10D, 10E, and 10F are explanatory views each showing a bonding process of a circuit board and an IC chip in the mounting method of the fourth embodiment of the present invention.

도 11A, 11B, 11C, 11D, 11E, 11F, 11G는 각기 본 발명의 제5실시형태의 실장방법에 있어서, 회로기판과 IC칩의 접합공정을 도시한 설명도이며,11A, 11B, 11C, 11D, 11E, 11F, and 11G are explanatory views showing a bonding process of a circuit board and an IC chip in the mounting method of the fifth embodiment of the present invention, respectively.

도 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H는 각기 본 발명의 제6실시형태의 실장방법에 있어서, 회로기판과 IC칩의 접합공정을 도시한 설명도이며,12A, 12B, 12C, 12D, 12E, 12F, 12G, and 12H are explanatory views showing a bonding process between a circuit board and an IC chip in the mounting method of the sixth embodiment of the present invention, respectively.

도 13은 종래의 회로기판과의 IC칩의 접합방법을 도시한 단면도이며,13 is a cross-sectional view showing a conventional method of bonding an IC chip to a circuit board.

도 14A, 14B는 각기 종래의 회로기판과의 IC칩의 접합방법을 도시한 설명도이며,14A and 14B are explanatory views showing a bonding method of an IC chip with a conventional circuit board, respectively.

도 15A, 15B, 15C, 15D, 15E, 15F, 15G는 각기 본 발명의 제7실시형태의 실장방법에 있어서, 회로기판과 IC칩의 접합공정을 도시한 설명도이다.15A, 15B, 15C, 15D, 15E, 15F, and 15G are explanatory views showing a bonding process between a circuit board and an IC chip in the mounting method of the seventh embodiment of the present invention, respectively.

본 발명은 상기 과제를 해결하기 위하여, 다음과 같이 구성하였다.In order to solve the said subject, this invention was comprised as follows.

본 발명의 제1특징에 의하면, 절연성으로 도전입자를 포함하지 않는 열경화성 수지를 개재시키면서, 회로기판의 전극과 전자부품의 전극에 와이어본딩에 의하여 형성된 범프와 위치맞춤을 행하고,According to the first aspect of the present invention, the bumps formed by wire bonding to the electrodes of the circuit board and the electrodes of the electronic component are interposed with the thermosetting resin which is insulating and does not contain the conductive particles.

가열하면서, 상기 전자부품을 상기한 회로기판에 1범프당 20gf 이상의 가압력으로 가압하고, 상기 범프의 레벨링과 상기 기판의 휨 교정을 동시에 행하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지를 상기 열로 경화하여, 상기 전자부품과 상기 회로기판을 접합하여 양 전극을 전기적으로 접속하도록 한 전자부품의 실장방법을 제공한다.The thermosetting material interposed between the electronic component and the circuit board while pressing the electronic component with a pressing force of 20 gf or more per bump to the circuit board while heating, and simultaneously performing leveling of the bump and bending correction of the substrate. A method of mounting an electronic component, wherein the resin is cured with the heat to bond the electronic component and the circuit board to electrically connect both electrodes.

본 발명의 제2특징에 의하면, 상기 위치맞춤은, 레벨링하지 않고 행하며, 상기 접합은, 가열하면서, 상기 범프의 레벨링과 상기 기판의 휨의 교정을 동시에 실행하는, 제1특징에서 기재한 전자부품의 실장방법을 제공한다.According to the second aspect of the present invention, the above-described alignment is performed without leveling, and the joining is performed by heating, while simultaneously performing leveling of the bumps and correction of warping of the substrate. It provides a method of mounting.

본 발명의 제3특징에 의하면, 상기 열경화성 수지는, 이방성 도전막을 구비한 열경화성 수지 시이트인, 제1특징에 기재한 전자부품의 실장방법을 제공한다.According to a third aspect of the present invention, the thermosetting resin is a thermosetting resin sheet having an anisotropic conductive film, which provides a method for mounting the electronic component according to the first aspect.

본 발명의 제4특징에 의하면, 상기 위치맞춤 전에, 상기 회로기판에, 상기 열경화성 수지로서, 상기 전자부품의 전극을 연결한 외형치수보다 작은 형상치수의 고정형의 열경화성 수지 시이트를 첩부(貼付)한 다음 상기 위치맞춤을 행하고,According to the fourth aspect of the present invention, a fixing type thermosetting resin sheet having a shape dimension smaller than the external dimension connecting the electrode of the electronic component to the circuit board is attached to the circuit board prior to the alignment. Then perform the above alignment,

상기 접합은, 상기 열경화성 수지 시이트를 가열하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨 교정을 동시에 하면서 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여, 상기 전자부품과 상기 회로기판을 접합하도록 한, 제1특징에 기재한 전자부품의 실장방법을 제공한다.The joining presses the electronic component onto the circuit board while heating the thermosetting resin sheet to simultaneously perform bending correction of the circuit board while interposing the thermosetting resin sheet interposed between the electronic component and the circuit board as the heat. Provided is a method of mounting an electronic component according to the first aspect, wherein the electronic component and the circuit board are bonded to each other by curing.

본 발명의 제5특징에 의하면, 상기 위치맞춤 전에, 도전성 접착제를 상기 전자부품의 상기 전극의 상기 범프에 전사하고,According to a fifth aspect of the present invention, before the alignment, a conductive adhesive is transferred to the bumps of the electrodes of the electronic component,

상기 위치맞춤 전에, 상기 회로기판에는, 상기 열경화성 수지로서, 상기 전자부품의 상기 전극을 연결한 외형치수보다 작은 형상치수의 고정형의 열경화성 수지 시이트를 첩부한 다음, 상기 범프와 상기 회로기판의 전극의 위치를 맞추고,Before the positioning, the circuit board is affixed, as the thermosetting resin, a fixed type thermosetting resin sheet having a shape dimension smaller than the external dimension connecting the electrodes of the electronic component, and then the bumps and the electrodes of the circuit board. Position it,

상기 접합은, 상기 열경화성 수지 시이트를 가열하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨 교정을 동시에 하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여, 상기 전자부품과 상기 회로기판을 접합하도록 한, 제1특징에 기재한 전자부품의 실장방법을 제공한다.The bonding is performed by pressing the electronic component onto the circuit board while heating the thermosetting resin sheet to simultaneously perform bending correction of the circuit board while interposing the thermosetting resin sheet interposed between the electronic component and the circuit board. Provided is a method for mounting an electronic component according to the first aspect, wherein the electronic component and the circuit board are bonded by curing with heat.

본 발명의 제6특징에 의하면, 상기 회로기판에는, 상기 열경화성 수지로서, 한쪽면 또는 양면에 플럭스(flux) 층을 형성한 고정형의 열경화성 수지 시이트를 첩부한 다음, 상기 전자부품의 상기 전극의 상기 범프와 상기 회로기판의 상기 전극의 위치를 맞추고,According to a sixth aspect of the present invention, a fixed type thermosetting resin sheet having a flux layer formed on one or both surfaces thereof is affixed on the circuit board as the thermosetting resin, and then the electrode of the electrode of the electronic component is attached. Align the bumps with the electrodes on the circuit board,

상기 접합은, 가열된 헤드에 의하여 상기 전자부품을, 상기 회로기판에 가압 하여, 상기 회로기판의 휨 교정을 동시에 하면서, 상기 전자부품과 상기 회로기판의 사이에 개재하는 상기 열경화성 수지 시이트를 경화하고, 그 수지 시이트를 상기 범프가 돌파하는 경우에 상기 플럭스층의 플럭스 성분이 상기 범프에 부착하여, 이 범프가 상기 회로기판의 상기 전극과 접합되어서 상기 전자부품과 상기 회로기판을 접합하도록, 한 제1특징에 기재한 전자부품의 실장방법을 제공한다.The bonding is performed by pressing the electronic component to the circuit board by a heated head to simultaneously perform bending correction of the circuit board while curing the thermosetting resin sheet interposed between the electronic component and the circuit board. And when the bump breaks through the resin sheet, a flux component of the flux layer adheres to the bump so that the bump is joined to the electrode of the circuit board to bond the electronic component and the circuit board. Provided are a method for mounting an electronic component as described in one feature.

본 발명의 제7특징에 의하면, 상기 위치맞춤 전에, 상기 전자부품의 상기 전극의 상기 범프 및 상기 회로기판의 상기 전극의 적어도 한편에 대응하는 위치에 형성된 구멍내에, 표면에 금도금을 한 수지보올, 또는 니켈입자, 또는 은이나 은-팔라듐, 또는 금으로 된 도전입자, 또는 도전페이스트, 또는 쇠구슬(金球)로 된 입자를 상기 범프와 상기 회로기판의 상기 전극을 도통시키는 방향으로 매립한 고정형의 열경화성 수지 시이트를, 상기 열경화성 수지로서, 상기 회로기판의 상기 전극과 위치를 맞추어 첩부한 다음, 상기 전자부품의 상기 범프와 상기 회로기판의 상기 전극의 위치를 맞추고,According to a seventh aspect of the present invention, a resin bowl obtained by plating gold on a surface in a hole formed at a position corresponding to at least one of the bump of the electrode of the electronic component and the electrode of the circuit board before the positioning; Or a fixed type in which nickel particles, or silver, silver-palladium, or gold conductive particles, or conductive pastes or particles of iron beads are embedded in the direction in which the bumps and the electrodes of the circuit board are connected. The thermosetting resin sheet of the thermosetting resin was bonded to the electrode of the circuit board in position, and the position of the bump of the electronic component and the electrode of the circuit board were adjusted.

상기 접합은, 상기 열경화성 수지 시이트를 가열하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨을 교정하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여 접합하도록 한, 제1특징에 기재한 전자부품의 실장방법을 제공한다.The bonding cures the thermosetting resin sheet interposed between the electronic component and the circuit board with the heat while pressing the electronic component to the circuit board while heating the thermosetting resin sheet to correct the warpage of the circuit board. Provided is a method for mounting an electronic component according to the first aspect, which is bonded to each other.

본 발명의 제8특징에 의하면, 상기 위치맞춤 전에, 상기 전자부품을 상기 회로기판에 실장하는 경우에, 상기 전자부품의 상기 전극 및 상기 회로기판의 상기 전극의 적어도 한편에 대응하는 위치에 형성된 구멍에, 적어도 상기 전자부품의 전극에 입히는 패시베이션(passivation) 막의 두께보다 크고, 상기 회로기판의 전극의 두께보다 작은 치수이며, 또한, 표면에 금도금을 한 수지보올, 또는 니켈입자, 또는 은이나 은-팔라듐, 또는 금으로 된 도전입자, 또는 도전페이스트, 또는 쇠구슬로 된 입자를 상기 전자부품의 상기 전극과 상기 회로기판의 상기 회로전극을 서로 끼우는 방향으로, 또한 서로 도통시키는 방향으로 매립한 고정형의 열경화성 수지 시이트를, 상기 열경화성 수지로서, 상기 회로기판의 상기 전극과 위치를 맞추어 첩부한 다음, 상기 전자부품의 상기 전극과 상기 회로기판의 상기 전극의 위치를 맞추고,According to an eighth aspect of the present invention, in the case where the electronic component is mounted on the circuit board before the alignment, a hole formed at a position corresponding to at least one of the electrode of the electronic component and the electrode of the circuit board. At least larger than the thickness of the passivation film coated on the electrode of the electronic component, smaller than the thickness of the electrode of the circuit board, and a resin plate, nickel particles, silver or silver with gold plating on the surface thereof. Palladium or gold conductive particles or conductive pastes or iron beads particles are embedded in the direction in which the electrode of the electronic component and the circuit electrode of the circuit board are sandwiched with each other and in a direction in which they are connected to each other. The thermosetting resin sheet is bonded to the electrode of the circuit board by positioning the thermosetting resin as the thermosetting resin, and then the electronic Product by aligning the position of the electrode and the electrode of the circuit board,

상기 접합은, 상기 열경화성 수지 시이트를 가열하면서, 초음파진동을 상기 전자부품에 인가하면서 상기 전자부품을 상기 회로기판에 가압하여, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여 접합하도록 한, 제1특징에 기재한 전자부품의 실장방법을 제공한다.The joining pressurizes the electronic component onto the circuit board while applying ultrasonic vibration to the electronic component while heating the thermosetting resin sheet, and the thermosetting resin sheet interposed between the electronic component and the circuit board as the heat. Provided are a method for mounting an electronic component according to the first aspect, wherein the electronic component is cured and joined.

본 발명의 제9특징에 의하면, 상기 이방성 도전막에 포함되는 도전입자가, 니켈분말에 금도금을 한 것인, 제3특징에 기재한 전자부품의 실장방법을 제공한다.According to a ninth aspect of the present invention, there is provided a method for mounting an electronic component according to the third aspect, wherein the conductive particles contained in the anisotropic conductive film are plated with nickel powder.

본 발병의 제10특징에 의하면, 상기 열경화성 수지는 열경화성 수지 시이트로 한, 제1∼9특징 중 어느 한 특징에 기재한 전자부품의 실장방법을 제공한다.According to the tenth aspect of the present invention, there is provided a method for mounting an electronic component according to any one of the first to ninth aspects, wherein the thermosetting resin is a thermosetting resin sheet.

본 발명의 제11특징에 의하면, 상기 열경화성 수지의 시이트는, 그 두께가 접합후의 상기 전자부품의 작용면과 상기 회로기판의 전극이 형성된 면과의 틈새보다 두꺼운 두께로 한, 제10특징에 기재한 전자부품의 실장방법을 제공한다.According to the eleventh aspect of the present invention, the sheet of the thermosetting resin is characterized in that the thickness is thicker than the gap between the working surface of the electronic component after bonding and the surface on which the electrode of the circuit board is formed. A method of mounting an electronic component is provided.

본 발명의 제12특징에 의하면, 상기 열경화성 수지는 열경화성 접착제로 한, 제1 또는 제2특징에 기재한 전자부품의 실장방법을 제공한다.According to a twelfth aspect of the present invention, there is provided a method for mounting an electronic component according to the first or second aspect, wherein the thermosetting resin is a thermosetting adhesive.

본 발명의 제13특징에 의하면, 절연성이고 도전입자를 포함하지 않는 열경화성 수지를 개재시키면서, 회로기판의 전극과 전자부품의 전극에 와이어본딩에 의해 형성된 범프와 위치조정하는 위치맞춤장치와,According to a thirteenth aspect of the present invention, there is provided a positioning device for adjusting a bump formed by wire bonding to an electrode of a circuit board and an electrode of an electronic component while interposing a thermosetting resin that is insulating and does not contain conductive particles,

상기 열경화성 수지를 가열하는 가열장치와,A heating device for heating the thermosetting resin,

상기 가열장치에 의하여 상기 열경화성 수지를 가열하면서, 상기 전자부품을 상기 회로기판에 1범프당 20gf 이상의 가압력으로 가압하고, 상기 범프의 레벨링과 상기 기판의 휨 교정을 동시에 행하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지를 상기 열로 경화하여, 상기 전자부품과 상기 회로기판을 접합하여 양 전극을 전기적으로 접속하는 접합장치를 구비한 전자부품의 실장장치를 제공한다.While heating the thermosetting resin by the heating device, the electronic component is pressurized to the circuit board at a pressure of 20 gf or more per bump, the leveling of the bumps and the bending correction of the substrate are performed simultaneously. A thermosetting resin interposed between circuit boards is cured with the heat to provide a mounting apparatus for an electronic component having a bonding device for joining the electronic component and the circuit board to electrically connect both electrodes.

본 발명의 제14특징에 의하면, 상기 위치맞춤장치는, 레벨링하지 않고 위치맞춤을 행하며, 상기 접합장치는, 상기 범프의 레벨링과 상기 기판의 휨 교정을 동시에 실행하는, 제13특징에 기재한 전자부품의 실장장치를 제공한다.According to a fourteenth aspect of the present invention, the positioning apparatus performs alignment without leveling, and the bonding apparatus includes the electron according to the thirteenth aspect, wherein the leveling of the bumps and the bending correction of the substrate are simultaneously performed. Provides a device for mounting parts.

본 발명의 제15특징에 의하면, 상기 열경화성 수지는, 이방성 도전막을 구비한 열경화성 수지의 시이트인, 제13특징에 기재한 전자부품의 실장장치를 제공한다.According to a fifteenth aspect of the present invention, the thermosetting resin provides a mounting apparatus for an electronic component according to the thirteenth aspect, which is a sheet of a thermosetting resin having an anisotropic conductive film.

본 발명의 제16특징에 의하면, 상기 위치맞춤장치는, 상기 회로기판에, 상기 열경화성 수지로서, 상기 전자부품의 전극을 접속한 외형치수보다 작은 형상치수의 고정형의 열경화성 수지 시이트를 첩부한 다음, 상기 전자부품의 상기 전극의 범프와 상기 회로기판의 전극의 위치를 맞추고,According to a sixteenth aspect of the present invention, the positioning device attaches, as the thermosetting resin, a fixed type thermosetting resin sheet having a shape dimension smaller than the external dimension connecting the electrode of the electronic component to the circuit board. Matching the bumps of the electrodes of the electronic component with the electrodes of the circuit board,

상기 접합장치는, 상기 열경화성 수지 시이트를 가열하면서, 상기 전자부품을, 상기 회로기판에 가압하여, 상기 회로기판의 휨 교정을 동시에 실시하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여, 상기 전자부품과 상기 회로기판을 접합하는, 제13특징에 기재한 전자부품의 실장장치를 제공한다.The bonding apparatus presses the electronic component onto the circuit board while heating the thermosetting resin sheet, and simultaneously performs bending correction of the circuit board while interposing the thermosetting resin interposed between the electronic component and the circuit board. Provided is an electronic component mounting apparatus according to the thirteenth aspect, wherein the sheet is cured by the heat to bond the electronic component and the circuit board.

본 발명의 제17특징에 의하면, 상기 위치맞춤장치는, 위치맞춤 전에, 도전성 접착제를 상기 전자부품의 상기 전극의 상기 범프에 전사하고,According to a seventeenth aspect of the present invention, the alignment device transfers a conductive adhesive to the bumps of the electrodes of the electronic component before alignment.

상기 위치맞춤 전에, 상기 회로기판에는, 상기 열경화성 수지로서, 상기 전자부품의 상기 전극을 연결한 외형치수보다 작은 형상치수의 고정형의 열경화성 수지 시이트를 첩부한 다음, 상기 범프와 상기 회로기판의 전극의 위치를 맞추고,Before the positioning, the circuit board is affixed, as the thermosetting resin, a fixed type thermosetting resin sheet having a shape dimension smaller than the external dimension connecting the electrodes of the electronic component, and then the bumps and the electrodes of the circuit board. Position it,

상기 접합장치는, 상기 열경화성 수지 시이트를 가열하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨 교정을 동시에 실시하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여, 상기 전자부품과 상기 회로기판을 접합하는, 제13특징에 기재한 전자부품의 실장장치를 제공한다.The bonding apparatus presses the electronic component onto the circuit board while heating the thermosetting resin sheet, and simultaneously performs bending correction of the circuit board while interposing the thermosetting resin sheet between the electronic component and the circuit board. The apparatus for mounting an electronic component according to the thirteenth aspect, which is cured by the heat to bond the electronic component and the circuit board, is provided.

본 발명의 제18특징에 의하면, 상기 위치맞춤장치는, 상기 회로기판에는, 상기 열경화성 수지로서, 한쪽면 또는 양면에 플럭스층을 형성한 고정형의 열경화성 수지 시이트를 첩부한 다음, 상기 전자부품의 상기 전극의 상기 범프와 상기 회로기판의 상기 전극의 위치를 맞추고,According to an eighteenth aspect of the present invention, the alignment apparatus includes a fixed thermosetting resin sheet having a flux layer formed on one or both surfaces thereof, as the thermosetting resin, on the circuit board. Align the bumps of the electrodes with the electrodes of the circuit board;

상기 접합장치는, 가열된 헤드에 의하여 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨 교정을 동시에 실시하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 경화하고, 그 수지 시이트를 상기 범프가 돌파하는 경우에 상기 플럭스층의 플럭스 성분이 상기 범프에 부착하여, 이 범프가 상기 회로기판의 상기 전극과 접합되어 상기 전자부품과, 상기 회로기판을 접합하는, 제13특징에 기재한 전자부품의 실장장치를 제공한다.The bonding apparatus presses the electronic component to the circuit board by a heated head to simultaneously perform bending correction of the circuit board while curing the thermosetting resin sheet interposed between the electronic component and the circuit board. And when the bump breaks through the resin sheet, a flux component of the flux layer adheres to the bump, and the bump is joined to the electrode of the circuit board to bond the electronic component and the circuit board. Provided is a mounting apparatus for an electronic component described in 13 Features.

본 발명의 제19특징에 의하면, 상기 위치맞춤장치는, 상기 전자부품의 상기 전극의 상기 범프 및 상기 회로기판의 상기 전극의 적어도 한편에 대응하는 위치에 형성된 구멍내에, 표면에 금도금을 한 수지보올, 또는 니켈입자, 또는 은이나 은-팔라듐, 또는 금으로 된 도전입자, 또는 도전페이스트, 또는 쇠구슬로 된 입자를 상기 범프와 상기 회로기판의 상기 전극을 도통시키는 방향으로 매립한 고정형의 열경화성 수지 시이트를, 상기 열경화성 수지로서, 상기 회로기판의 상기 전극과 위치를 맞추고,According to a nineteenth aspect of the present invention, the alignment device includes a resin plate obtained by plating a surface with gold in a hole formed at a position corresponding to at least one of the bump of the electrode of the electronic component and the electrode of the circuit board. Or a fixed thermosetting resin in which nickel particles, conductive particles of silver, silver-palladium, or gold, conductive paste, or particles of iron beads are embedded in the direction in which the bumps and the electrodes of the circuit board are connected. The sheet is positioned as the thermosetting resin with the electrode on the circuit board,

상기 접합장치는, 상기 열경화성 수지 시이트를 가열하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨을 교정하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여 접합하는, 제13특징에 기재한 전자부품의 실장장치를 제공한다.The bonding apparatus presses the electronic component onto the circuit board while heating the thermosetting resin sheet, and corrects the warpage of the circuit board, while interposing the thermosetting resin sheet interposed between the electronic component and the circuit board as the heat. Provided is an electronic component mounting apparatus according to the thirteenth aspect, which is cured and joined.

본 발명의 제20특징에 의하면, 상기 위치맞춤장치는, 상기 전자부품을 상기 회로기판에 실장하는 경우에, 상기 전자부품의 상기 전극 및 상기 회로기판의 상기 전극의 적어도 한편에 대응하는 위치에 형성된 구멍에, 적어도 상기 전자부품의 전극에 입히는 패시베이션 막의 두께보다 크고, 상기 회로기판의 전극의 두께보다 작은 치수이며, 또한 표면에 금도금을 한 수지보올, 또는 니켈입자, 또는 은이나 은-팔라듐, 또는 도전페이스트, 또는 쇠구슬로 된 입자를 상기 전자부품의 상기 전극과 상기 회로기판의 상기 회로전극을 서로 끼우는 방향으로 또한 서로 도통시키는 방향으로 매립한 고정형의 열경화성 수지 시이트를, 상기 열경화성 수지로서, 상기 회로기판의 상기 전극과 위치를 맞추어 첩부한 다음, 상기 전자부품의 상기 전극과 상기 회로기판의 상기 전극의 위치를 맞추고,According to a twentieth aspect of the present invention, the positioning device is formed at a position corresponding to at least one of the electrode of the electronic component and the electrode of the circuit board when the electronic component is mounted on the circuit board. A hole having a dimension larger than the thickness of the passivation film coated on the electrode of the electronic component and smaller than the thickness of the electrode of the circuit board, and having a gold plated resin surface, nickel particles, silver or silver-palladium, or A fixed type thermosetting resin sheet in which conductive paste or particles of iron beads are embedded in a direction in which the electrode of the electronic component and the circuit electrode of the circuit board are sandwiched with each other and in a direction of conducting to each other is used as the thermosetting resin. Attach and align the electrode with the electrode of the circuit board, and then attach the electrode and the circuit board of the electronic component. Aligning the position of said electrode,

상기 접합장치는, 상기 열경화성 수지 시이트를 가열하면서 초음파진동을 상기 전자부품에 인가하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여 접합하는, 제13특징에 기재한 전자부품의 실장장치를 제공한다.The bonding apparatus presses the electronic component onto the circuit board while applying ultrasonic vibration to the electronic component while heating the thermosetting resin sheet, thereby interposing the thermosetting resin sheet interposed between the electronic component and the circuit board. Provided is an electronic component mounting apparatus according to the thirteenth feature, which is hardened by heat and joined.

본 발명의 제21특징에 의하면, 상기 이방성 도전막에 함유된 도전입자가, 니켈분말에 금도금을 한 것인, 제15특징에 기재한 전자부품의 실장장치를 제공한다.According to a twenty-first aspect of the present invention, there is provided an apparatus for mounting electronic components according to the fifteenth aspect, wherein the conductive particles contained in the anisotropic conductive film are gold plated with nickel powder.

본 발명의 제22특징에 의하면, 상기 열경화성 수지는 열경화성 수지 시이트로 한, 제13∼21특징 중 어느 한 특징에 기재한 전자부품의 실장장치를 제공한다.According to a twenty-second aspect of the present invention, there is provided an electronic component mounting apparatus according to any one of the thirteenth to twenty-first aspects, wherein the thermosetting resin is a thermosetting resin sheet.

본 발명의 제23특징에 의하면, 상기 열경화성 수지의 시이트는, 그 두께가 접합 후의 상기 전자부품의 작용면과 상기 회로기판의 전극이 형성된 면과의 틈새보다 두꺼운 두께로 한, 제22특징에 기재한 전자부품의 실장장치를 제공한다.According to a twenty-third aspect of the present invention, there is provided the twenty-second aspect, wherein the sheet of the thermosetting resin is thicker than the gap between the working surface of the electronic component after bonding and the surface on which the electrode of the circuit board is formed. Provided is an electronic component mounting apparatus.

본 발명의 제24특징에 의하면, 상기 열경화성 수지는 열경화성 접착제로 한, 제13 또는 14특징에 기재한 전자부품의 실장장치를 제공한다.According to a twenty-fourth aspect of the present invention, there is provided a mounting apparatus for an electronic component according to the thirteenth or fourteenth aspect, wherein the thermosetting resin is a thermosetting adhesive.

본 발명의 제25특징에 의하면, 상기 위치조정장치와 상기 접합장치는 하나의 장치로 구성되게 한, 제13 또는 14특징에 기재한 전자부품의 실장장치를 제공한다.According to a twenty fifth aspect of the present invention, there is provided an electronic component mounting apparatus according to the thirteenth or fourteenth feature, wherein the position adjusting device and the bonding device are constituted by one device.

본 발명의 제26특징에 의하면, 상기 위치맞춤 후에 또한 상기 접합 전에 있어서, 상기 범프에 도전성 페이스트를 부착한 다음, 이 도전성 페이스트를 경화시켜서 상기 범프의 일부로서 기능하게 하고, 상기 접합에 있어서, 상기 열경화성 수지를 상기 경화한 도전성 페이스트가 돌파하여 상기 회로기판의 전극과 전기적으로 접속하도록 한, 제1∼9특징 중 어느 한 특징에 기재한 전자부품의 실장방법을 제공한다.According to a twenty sixth aspect of the present invention, after the positioning and before the bonding, a conductive paste is attached to the bumps, and then the conductive paste is cured to function as a part of the bumps. Provided is a method of mounting an electronic component according to any one of the first to ninth aspects, wherein a thermosetting resin breaks through the cured conductive paste and is electrically connected to an electrode of the circuit board.

본 발명의 제27특징에 의하면, 상기 위치맞춤 후에 또한 상기 접합 전에 있어서, 상기 범프에 도전성 페이스트를 부착한 다음, 이 도전성 페이스트를 경화시켜서, 상기 범프의 일부로서 기능하게 하고, 상기 접합에 있어서, 상기 열경화성 수지를 상기 경화한 도전성 페이스트가 돌파하여 상기 회로기판의 전극과 전기적으로 접속하도록 한, 제13∼21특징 중 어느 한 특징에 기재한 전자부품의 실장장치를 제공한다.According to a twenty-seventh aspect of the present invention, after the alignment and before the bonding, a conductive paste is attached to the bumps, and then the conductive paste is cured to function as a part of the bumps. Provided is an electronic component mounting apparatus according to any one of the thirteenth to twenty-first aspects, wherein the thermosetting resin breaks through the cured conductive paste so as to be electrically connected to an electrode of the circuit board.

본 발명의 제28특징에 의하면, 상기 열경화성 수지 시이트는 상기 회로기판측에 배치되어 있는, 제1∼9특징 중 어느 한 특징에 기재한 전자부품의 실장방법을 제공한다.According to a twenty eighth aspect of the present invention, there is provided a method for mounting an electronic component according to any one of the first to ninth aspects, wherein the thermosetting resin sheet is disposed on the circuit board side.

본 발명의 제29특징에 의하면, 상기 열경화성 수지 시이트는 상기 전자부품측에 배치되어 있는, 제1∼9특징 중 어느 한 특징에 기재한 전자부품의 실장방법을 제공한다.According to a twenty-ninth aspect of the present invention, there is provided a method for mounting an electronic component according to any one of the first to ninth aspects, wherein the thermosetting resin sheet is disposed on the electronic component side.

본 발명의 제30특징에 의하면, 상기 열경화성 수지 시이트는 상기 회로기판측에 배치되어 있는, 제13∼21특징 중 어느 한 특징에 기재한 전자부품의 실장장치를 제공한다.According to a thirtieth aspect of the invention, the thermosetting resin sheet provides an electronic component mounting apparatus according to any one of the thirteenth to twenty-first aspects, wherein the thermosetting resin sheet is disposed on the circuit board side.

본 발명의 제31특징에 의하면, 상기 열경화성 수지 시이트는 상기 전자부품에 배치되어 있는, 제13∼제21 특징중 어느 한 특징에 기재한 전자부품의 실장장치를 제공한다. 상기 특징에 의하면, 예컨대 전자부품, 예컨대 IC칩을 회로에 실장하는 경우에, IC칩의 Al 또는 Al에 Si 또는 Cu 등을 첨가하여 형성된 전극패드(pad)에 와이어본딩장치를 사용하여 Au와이어에 방전에 의하여 보올을 형성하고, 모세관에 의하여 그 보올에 초음파를 가하면서 IC칩의 전극패드에 접합한다.According to a thirty first aspect of the invention, the thermosetting resin sheet provides the electronic component mounting apparatus according to any one of the thirteenth to twenty-first aspects, wherein the thermosetting resin sheet is disposed on the electronic component. According to the above features, for example, in the case of mounting an electronic component such as an IC chip on a circuit, Au wires are used on an electrode pad formed by adding Si or Cu to Al or Al of the IC chip. A bowl is formed by electric discharge, and is bonded to the electrode pad of the IC chip while applying ultrasonic waves to the bowl by a capillary tube.

본 발명을 설명하기 전에 첨부도면에 있어서 같은 부품에 대하여는 같은 참조부호를 붙이고 있음을 밝혀둔다.Before describing the present invention, the same reference numerals are used to refer to the same parts in the accompanying drawings.

이하, 본 발명의 제1실시형태에 관한 IC칩의 실장방법 및 그 제조장치를 도 1A∼도 1H를 참조하면서 설명한다.Hereinafter, an IC chip mounting method and a manufacturing apparatus thereof according to the first embodiment of the present invention will be described with reference to FIGS. 1A to 1H.

본 발명의 제1실시형태에 관한 회로기판에의 IC칩 실장방법을 도 1A∼도 3C에 의거하여 설명한다. 도 1A의 IC칩(1)에 있어서 IC칩(1)의 1패드전극(2)에 와이어본딩장치에 의하여 도 2A∼2F와 같은 동작에 의하여 범프(돌기전극)(3)를 형성한다, 즉, 도 2A에서 호울더(93)에서 돌출한 와이어(95)의 하단에 보올(ball; 96)을 형성하고, 도 2B에서 와이어(95)를 보유하는 호울더(93)를 하강시켜, 보올(96)을 IC칩(1)의 전극(2)에 접합하여 대략 범프(3)의 형상을 형성하고, 도 2C에서 와이어(95)를 하방으로 보내면서 호울더(93)의 상승을 개시하고, 도 2D에 도시한 바와 같은 대략 구형의 루우프(99)에 호울더(93)를 이동시켜서 도 2E에 도시한 바와 같이 범프(3)의 상부에 만곡부(98)를 형성하고, 잡아 끊음으로써 도 2F에 도시한 바와 같은 범프(3)를 형성한다. 또는 도 2B에서 와이어(95)를 호울더(93)로 클램프해서, 호울더(93)를 상승시켜 상방으로 끌어올림으로써, 금와이어(95)를 잡아 끊어, 도 2G와 같은 범프(3)의 형상을 형성하도록 하여도 좋다, 이와 같이, IC칩(1)의 각 전극(2)에 범프(3)를 형성한 상태를 도 1B에 도시하였다.An IC chip mounting method on a circuit board according to the first embodiment of the present invention will be described with reference to Figs. 1A to 3C. In the IC chip 1 of FIG. 1A, a bump (protrusion electrode) 3 is formed on the 1 pad electrode 2 of the IC chip 1 by the operation as shown in FIGS. 2B, a ball 96 is formed at the bottom of the wire 95 protruding from the holder 93, and the holder 93 holding the wire 95 is lowered in FIG. 96 is joined to the electrode 2 of the IC chip 1 to form a roughly bump 3 shape, and the rise of the holder 93 is started while sending the wire 95 downward in FIG. 2C, By moving the holder 93 to a substantially spherical loop 99 as shown in FIG. 2D, forming a curved portion 98 on top of the bump 3, as shown in FIG. 2E, and cutting it off. A bump 3 as shown in FIG. 2F is formed. Alternatively, the wire 95 is clamped to the holder 93 in FIG. 2B, the holder 93 is raised and pulled upward to catch and disconnect the gold wire 95, thereby removing the bump 3 as shown in FIG. 2G. A shape in which the bumps 3 are formed on the electrodes 2 of the IC chip 1 may be formed in FIG. 1B.

다음에, 도 1C에 도시한 회로기판(4)의 전극(5)상에, 도 1D에 도시한 바와 같이, IC칩(1)의 크기보다 약간 큰 치수로 절단된 열경화성 수지 시이트(6)를 배치하고, 예컨대 80∼120℃로 가열된 부착공구(7)로, 예컨대 5∼10kgf/cm2정도의 압력으로 열경화성 수지 시이트(6)를 기판(4)의 전극(5)상에 첩부한 후, 열경화성 수지 시이트(6)의 공구(7)측으로 떼어낼 수 있도록 배치된 세퍼레이터(6a)를 벗김으로써, 기판(4)의 준비공정을 완료한다. 이 세퍼레이터(6a)는, 공구(7)에 열경화성 시이트(6)가 첩부하는 것을 방지하기 위한 것이다. 여기서, 열경화성 수지 시이트(6)는 실리카 등의 무기계열 첨가제(filler)를 넣은 것(예컨대, 에폭시수지, 페놀수지, 폴리이미드 등), 무기계열 첨가제를 전혀 넣지 않은 것(예컨대, 에폭시수지, 페놀수지, 폴리이미드 등)이 바람직함과 동시에, 후공정의 리플로우(reflow)공정에서의 고온에 견딜 수 있을 정도의 내열성(예컨대, 240℃에 10초간 견딜수 있을 정도의 내열성)을 갖는 것이 바람직하다.Next, on the electrode 5 of the circuit board 4 shown in Fig. 1C, as shown in Fig. 1D, a thermosetting resin sheet 6 cut into a size slightly larger than the size of the IC chip 1 is placed. And attaching the thermosetting resin sheet 6 on the electrode 5 of the substrate 4 with, for example, the attachment tool 7 heated to 80 to 120 ° C., for example, at a pressure of about 5 to 10 kgf / cm 2 . The preparation process of the board | substrate 4 is completed by peeling the separator 6a arrange | positioned so that the thermosetting resin sheet 6 can be removed to the tool 7 side. This separator 6a is for preventing the thermosetting sheet 6 from sticking to the tool 7. Here, the thermosetting resin sheet 6 contains an inorganic filler such as silica (for example, epoxy resin, phenol resin, polyimide, etc.), and no inorganic additive (for example, epoxy resin, phenol). Resin, polyimide, etc.) are preferable, and at the same time, it is preferable to have heat resistance (for example, heat resistance to withstand 10 DEG C for 10 seconds) at a high temperature in a reflow process in a later step. .

다음에, 도 1E 및 도 1F에 도시한 바와 같이, 가열된 접합공구(8)에 의하여, 상기 전공정에서 범프(3)가 전극(2)상에 형성된 IC칩(1)을 상기 전공정에서 준비된 기판(4)의 IC칩(1)의 전극(2)에 대응하는 전극(5)상에 위치를 맞춘 다음 가압(加壓)한다. 이때, 범프(3)는, 그 헤드부(3a)가 기판(4)의 전극(5)상에서 도 3A에서 도 3B에 도시한 바와 같이 변형되면서 꽉 눌려지며, 이때, IC칩(1)을 개재하여 범프(3)측에 인가하는 하중은 범프(3)의 지름에 따라 다르지만, 절곡되어서 겹치도록 되어 있는 범프(3)의 헤드(3a)가, 반드시 도 3C와 같이 변형하는 정도의 하중을 가하는 것이 필요하다. 이 하중은 최저로도 20(gf)을 필요로 한다. 하중의 상한은, IC칩(1), 범프(3), 회로기판(4) 등이 손상하지 않을 정도로 한다. 경우에 따라서, 그 최대하중은 100(gf)을 초과하는 것도 있다. 또한, 6m 및 6s는 열경화성 수지 시이트(6)가 접합공구(8)의 열에 의하여 용융한 용융중의 열경화성 수지 및 용융후에 열경화된 수지이다.Next, as shown in Figs. 1E and 1F, the IC chip 1 having the bumps 3 formed on the electrodes 2 in the previous step is heated by the joining tool 8 in the previous step. After positioning on the electrode 5 corresponding to the electrode 2 of the IC chip 1 of the prepared board | substrate 4, it pressurizes. At this time, the bump 3 is pressed tightly while the head portion 3a is deformed on the electrode 5 of the substrate 4 as shown in Figs. 3A to 3B, and at this time, the IC chip 1 is interposed. The load applied to the bump 3 side varies depending on the diameter of the bump 3, but the head 3a of the bump 3, which is bent and overlaps, must be subjected to a load such that it deforms as shown in Fig. 3C. It is necessary. This load requires a minimum of 20 (gf). The upper limit of the load is such that the IC chip 1, the bump 3, the circuit board 4 and the like are not damaged. In some cases, the maximum load may exceed 100 (gf). In addition, 6m and 6s are the thermosetting resin in the melt which the thermosetting resin sheet 6 melted by the heat of the bonding tool 8, and the thermosetting resin after melt | fusion.

또한, 세라믹히이터 또는 펄스히이터 등의 내장하는 히이터(8a)에 의하여 가열된 접합공구(8)에 의하여, 상기 전공정에서 범프(3)가 전극(2)상에 형성된 IC칩(1)을 상기 전공정에서 준비된 기판(4)의 IC칩(1)의 전극(2)에 대응하는 전극(5)상에 도 1E 및 도 1F에 도시한 바와 같이, 위치를 맞추는 위치맞춤공정과, 위치맞춤 후, 도 1G에 도시한 바와 같이 가압 접합하는 공정 등을 하나의 위치맞춤겸 가압접합장치, 예컨대 도 1F의 위치맞춤겸 가압접합장치에서 실시하도록 하여도 좋다. 그러나, 각각의 장치, 예컨대 다수의 기판을 연속 생산하는 경우에 있어서, 위치맞춤작업과 가압접합작업을 동시에 실시함으로써 생산성을 향상시키기 때문에, 위치맞춤공정은 도 4B의 위치맞춤장치에서 실시하고, 가압접합공정은 도 4C의 접합장치에서 실시하여도 좋다. 또, 도 4C에서는, 생산성을 향상시키기 위하여, 2개의 접합장치를 도시하여, 1장의 회로기판(4)의 2개 장소를 동시에 가압, 접합할 수 있도록 하였다.In addition, the IC chip 1 in which the bumps 3 are formed on the electrodes 2 in the previous step by the bonding tool 8 heated by a built-in heater 8a, such as a ceramic heater or a pulse heater, is used. Positioning step for positioning, as shown in FIGS. 1E and 1F on the electrode 5 corresponding to the electrode 2 of the IC chip 1 of the substrate 4 prepared in the previous step, and after the alignment 1G may be performed by one positioning and pressure bonding device such as the positioning and pressure bonding device of FIG. 1F. However, in the case of continuously producing each apparatus, for example, a plurality of substrates, since the productivity is improved by simultaneously performing the alignment operation and the pressure bonding operation, the alignment process is performed in the alignment apparatus of FIG. 4B and pressurized. The bonding step may be performed in the bonding apparatus of FIG. 4C. In addition, in FIG. 4C, in order to improve productivity, two joining apparatuses are shown so that two places of one circuit board 4 can be simultaneously pressed and joined.

이때, 회로기판(4)은, 유리직물적층 에폭시기판(유리에폭시기판)이나 유리직물적층 폴리이미드수지기판 등이 사용된다. 이들 기판(4)은, 열이력(熱履歷)이나, 재단, 가공에 의하여 휨이나 꾸불꾸불함을 발생하고 있어, 반드시 완전한 평면은 아니다. 그래서, 도 4A 및 도 4B에 도시한 바와 같이, 예컨대 약 5㎛ 이하로 조정되도록 평행도가 각기 관리된 접합공구(8)와 스테이지(stage)(9)에 의하여, 접합공구(8)측에서 스테이지(9)측으로 향하여 열과 하중을 IC칩(1)을 통하여 회로기판(4)에 국소적으로 인가하므로써, 그 인가된 부분의 회로기판(4)의 휨이 교정된다, 또, IC칩(1)은 작용면의 중심이 오목하게 휘어저 있으나, 이것을 접합시에 20gf 이상의 강한 힘으로 가압하므로써, 기판(4)과 IC칩(1)의 양편의 휨이나 꾸불꾸불함을 교정할 수 있다. 이 IC칩(1)의 휨은, IC칩(1)을 형성할 때, Si에 박막을 형성하는 경우에 발생하는 내부 응력에 의하여 발생하는 것이다.At this time, as the circuit board 4, a glass fabric laminated epoxy substrate (glass epoxy substrate), a glass fabric laminated polyimide resin substrate, or the like is used. These board | substrates 4 generate | occur | produce warpage and serpentine by heat history, cutting, and a process, and are not necessarily a perfect plane. Thus, as shown in Figs. 4A and 4B, for example, the joining tool 8 and the stage 9 each of which the parallelism is managed so as to be adjusted to about 5 mu m or less, the stage on the joining tool 8 side. By locally applying heat and load to the circuit board 4 via the IC chip 1 toward the side of (9), the warpage of the circuit board 4 of the applied portion is corrected, and the IC chip 1 The center of the silver working surface is concavely curved, but by pressing it with a strong force of 20 gf or more at the time of bonding, the warpage and the irregularity of both sides of the substrate 4 and the IC chip 1 can be corrected. The deflection of the IC chip 1 is caused by internal stress generated when a thin film is formed on Si when the IC chip 1 is formed.

이렇게 하여 회로기판(4)의 휨이 교정된 상태에서, 예컨대 140∼230℃의 열이 IC칩(1)과 회로기판(4) 사이의 열경화성 수지 시이트(6)에, 예컨대 수초∼20초 정도 인가되어, 이 열경화성 시이트(6)가 경화된다. 이때, 처음은 열경화성 수지 시이트(6)를 구성하는 열경화성 수지가 흘러서 IC칩(1)의 단부까지 밀봉한다. 또, 수지이므로, 가열된 당시는, 자연히 연화하기 때문에 이와 같이 단부까지 흐르는 것과 같은 유동성이 발생한다. 열경화성 수지의 체적은 IC칩(1)과 회로기판 사이의 공간의 체적보다 크게 함으로써, 이 공간으로부터 수지가 비어져 흘러나와서, 밀봉효과를 얻을 수 있다. 그 후, 가열된 공구(8)가 상승함으로써, 가열원이 없어지므로 IC칩(1)과 열경화성 수지 시이트(6)의 온도가 급격하게 저하하여 열경화성 수지 시이트(6)는 유동성을 상실하여, 도 1G 및 도 3C에 도시한 바와 같이, IC칩(1)은 경화한 열경화성 수지(6s)에 의하여 회로기판(4)상에 고정된다. 또, 회로기판(4)측을 스테이지(9)에 의하여 가열하여 두면, 접합공구(8)의 온도를 보다 낮게 설정할 수 있다.In this way, in the state where the curvature of the circuit board 4 is correct | amended, the heat of 140-230 degreeC is sent to the thermosetting resin sheet 6 between the IC chip 1 and the circuit board 4, for example, several seconds-about 20 second. It is applied and this thermosetting sheet 6 is hardened. At this time, the thermosetting resin which comprises the thermosetting resin sheet 6 initially flows and seals to the edge part of the IC chip 1. Moreover, since it is resin, at the time of heating, it softens naturally, and fluidity like flowing to an edge part arises in this way. By making the volume of the thermosetting resin larger than the volume of the space between the IC chip 1 and the circuit board, the resin can flow out from this space, and a sealing effect can be obtained. After that, since the heated tool 8 rises, the heating source disappears, so that the temperature of the IC chip 1 and the thermosetting resin sheet 6 decreases rapidly, and the thermosetting resin sheet 6 loses fluidity. As shown in 1G and FIG. 3C, the IC chip 1 is fixed on the circuit board 4 by the cured thermosetting resin 6s. If the circuit board 4 side is heated by the stage 9, the temperature of the joining tool 8 can be set lower.

또, 열경화성 시이트(6)를 첩부하는 대신에, 도 1H에 도시한 바와 같이 열경화성 접착제(6b)를 회로기판(4)상에, 투여 등에 의한 도포, 또는 인쇄 또는 전사하도록 하여도 좋다. 열경화성 접착제(6b)를 사용하는 경우는, 기본적으로는 상기한 열경화성 수지 시이트(6)를 사용하는 공정과 동일한 공정을 실시한다. 열경화성 수지 시이트(6)를 사용하는 경우에는, 고체이기 때문에 취급하기 쉬움과 동시에, 액체성분이 없으므로 고분자로 형성할 수 있으며, 유리 전이점이 높은 것을 형성하기 쉽다고 하는 이점이 있다. 이에 대하여, 열경화성 접착제(6b)를 사용하는 경우에는, 기판(4)의 임의의 위치에 임의의 크기로 도포, 인쇄 또는 전사할 수 있다,Instead of attaching the thermosetting sheet 6, as shown in Fig. 1H, the thermosetting adhesive 6b may be applied onto the circuit board 4 by application or by printing or printing or transferring. When using the thermosetting adhesive 6b, the process similar to the process of using the above-mentioned thermosetting resin sheet 6 is implemented basically. In the case of using the thermosetting resin sheet 6, since it is a solid, it is easy to handle, and since there is no liquid component, it can be formed with a polymer, and there exists an advantage that it is easy to form a thing with a high glass transition point. On the other hand, when using the thermosetting adhesive 6b, it can apply | coat, print, or transfer to arbitrary positions in the board | substrate 4,

또, 열경화성 수지에 대신하여 이방성 도전막(ACF)을 사용하여도 좋고, 또한, 이방성 도전막에 포함되는 도전입자로서, 니켈분말에 금도금을 한 것을 사용함으로써, 전극(5)과 범프(3)와의 사이에서의 접속저항값을 저하시킬 수 있어서 더욱 적합하다.In addition, an anisotropic conductive film (ACF) may be used in place of the thermosetting resin, and the electrode 5 and the bump 3 are formed by using a nickel plated gold powder as the conductive particles contained in the anisotropic conductive film. Since the connection resistance value between and can be reduced, it is more suitable.

이와 같이, 열경화성 수지 시이트(6) 대신에 이방성 도전막(10)을 사용한 경우의 실장프로세스를 도 2A∼5F에 의해 설명한다. 도 5A의 IC칩(1)에 있어서 IC칩(1)의 A1패드전극(2)에 와이어본딩장치에 의하여 도 2A∼2F와 같은 동작에 의해 범프(돌기전극)(3)를 도 5B와 같이 형성한다. 또는, 도 2B에서 와이어(95)를 호울더(93)로 클램프하여 상방으로 끌어 올림으로써 와이어(95)를 잡아 끊어서, 도 2G와 같은 범프형상으로 하여도 좋다.Thus, the mounting process at the time of using the anisotropic conductive film 10 instead of the thermosetting resin sheet 6 is demonstrated with reference to FIGS. 2A-5F. In the IC chip 1 of FIG. 5A, the bump (protrusion electrode) 3 is moved to the A1 pad electrode 2 of the IC chip 1 by a wire bonding apparatus as shown in FIGS. 2A to 2F, as shown in FIG. 5B. Form. Alternatively, in FIG. 2B, the wire 95 may be clamped with the holder 93 and pulled upward to grasp and disconnect the wire 95 to form a bump shape as shown in FIG. 2G.

다음에, 도 5C의 회로기판(4)의 전극(5)상에, 도 5D에 도시한 바와 같이, IC칩(1)의 크기보다 약간 큰 치수로 절단한 이방성 도전막 시이트(10)를 배치하고, 예컨대 80∼120℃로 가열된 부착공구(7)에 의하여 예컨대 5∼10kgf/cm2정도의 압력으로 기판(4)에 첩부한 후, 이방성 도전막 시이트(10)의 공구측의 세퍼레이터를 벗기므로서 기판(4)의 준비공정이 완료한다.Next, on the electrode 5 of the circuit board 4 of FIG. 5C, as shown in FIG. 5D, an anisotropic conductive film sheet 10 cut to a size slightly larger than the size of the IC chip 1 is disposed. After attaching to the substrate 4 with a pressure of about 5 to 10 kgf / cm 2 , for example, by the attachment tool 7 heated at 80 to 120 ° C., the separator on the tool side of the anisotropic conductive film sheet 10 is removed. By peeling off, the preparation process of the board | substrate 4 is completed.

다음에, 도 5E에 도시한 바와 같이, 가열된 접합공구(8)에 의하여, 상기 공정에서 범프(3)가 형성된 IC칩(1)을 상기 공정에서 준비된 기판(4)의 IC칩(1)에 대응하는 전극(5)상에 위치를 맞추어서 이방성 도전막 시이트(10)를 개재하여 가압한다. 이때, 범프(3)는 기판(4)의 전극(5) 상에서 범프(3)의 헤드(3a)가 도 3B∼3C와 같이 변형하면서 밀어 붙여지게 된다. 이때, 인가하는 하중은, 범프(3)의 지름에 따라서 다르지만, 헤드(3a)의 겹쳐 쌓여진 부분이 도 3C와 같이 반드시 변형하도록 한다. 또, 이때, 도 6에 도시한 바와 같이, 이방성 도전막 시이트(10)속의 도전입자(10a)가 수지보올구슬에 금속도금을 하였을 경우에는, 도전입자(10a)가 변형할 필요가 있다. 또, 이방성 도전막 시이트(10)속의 도전입자(10a)가 니켈 등 금속입자의 경우에는 범프(3)나 기판측의 전극(5)에 박히도록 하는 하중을 가하는 것이 필요하다. 이 하중은 최저라도 20(gf)을 필요로 한다. 최대로서는 100(gf)을 초과하는 경우도 있다.Next, as shown in FIG. 5E, the IC chip 1 having the bumps 3 formed in the above step by the heated bonding tool 8 is mounted on the IC chip 1 of the substrate 4 prepared in the above step. The pressure is applied through the anisotropic conductive film sheet 10 while aligning the position on the electrode 5 corresponding to. At this time, the bump 3 has the head 3a of the bump 3 deformed on the electrode 5 of the substrate 4 as shown in Figs. 3B to 3C. Pushed. At this time, the load to be applied varies depending on the diameter of the bump 3, but the stacked portion of the head 3a is necessarily deformed as shown in FIG. 3C. At this time, as shown in Fig. 6, when the conductive particles 10a in the anisotropic conductive film sheet 10 are plated with resin beads, the conductive particles 10a need to be deformed. In addition, in the case where the conductive particles 10a in the anisotropic conductive film sheet 10 are metal particles such as nickel, it is necessary to apply a load to be imposed on the bumps 3 and the electrodes 5 on the substrate side. This load requires at least 20 (gf). As a maximum, it may exceed 100 (gf).

이때, 회로기판(4)으로서는 다층 세라믹기판, 유리직물 적층 에폭시기판(유리에폭시기판), 아라미드 부직포기판, 유리직물 적층 폴리이미드수지기판, FPC(flexible printed circatit) 등이 사용된다, 이들 기판(4)은, 열이력이나, 재단, 가공에 의하여 휨이나 꾸불꾸불함을 발생하고 있어, 반드시 완전한 평면은 아니다. 그래서, 열과 하중을 IC칩(1)을 통하여 회전기판(4)에 국소적으로 인가하므로써, 그 인가된 부분의 회로기판(4)의 휨이 교정된다.At this time, as the circuit board 4, a multilayer ceramic substrate, a glass fabric laminated epoxy substrate (glass epoxy substrate), an aramid nonwoven substrate, a glass fabric laminated polyimide resin substrate, a flexible printed circuit (FPC), and the like are used. ) Generate warpage and creep due to thermal history, cutting and processing, and are not necessarily completely flat. Thus, by locally applying heat and load to the rotary substrate 4 via the IC chip 1, the warpage of the circuit board 4 in the applied portion is corrected.

이렇게 회로기판(4)의 휨이 교정된 상태에서, 예컨대 140∼230℃의 열이 IC칩(1)과 회로기판(4) 사이의 이방성 도전막(10)에 예컨대 수초∼20초 정도 인가되어, 이 이방성 도전막(10)이 경화된다. 이때, 최초는 열경화성 수지 시이트(6)를 구성하는 열경화성 수지가 흘러서 IC칩(1)의 단부까지 밀봉한다. 또한, 수지이므로, 가열되었을 때, 당시는 자연히 연화하므로 이와 같이 단부까지 흐르는 것과 같은 유동성이 발생한다. 열경화성 수지의 체적은 IC칩(1)과 회로기판 사이의 공간의 체적보다 크게 함으로써, 이 공간으로 부터 수지가 비어져 흘러나와서, 밀봉효과를 성취할 수 있다. 그 후, 가열된 공구(8)가 상승함으로써, 가열원이 없어지기 때문에 IC칩(1)과 이방성 도전막(10)의 온도는 급격하게 저하하여, 이방성 도전막(10)은 유동성을 상실하여, 도 5F에 도시한 바와 같이, IC칩(1)은, 이방성 도전막(10)을 구성한 수지(10s)에 의하여 회로기판(4)상에 고정된다. 또, 회로기판(4)측을 가열하여 두면 접합공구(8)의 온도를 더욱 낮게 할 수 있다,In this state in which the warpage of the circuit board 4 is corrected, for example, heat of 140 to 230 ° C. is applied to the anisotropic conductive film 10 between the IC chip 1 and the circuit board 4, for example, for several seconds to about 20 seconds. This anisotropic conductive film 10 is cured. At this time, the thermosetting resin which comprises the thermosetting resin sheet 6 flows initially, and it seals to the edge part of the IC chip 1. Moreover, since it is resin, when heated, it softens naturally at that time, and fluidity like flowing to an end part like this arises. By making the volume of the thermosetting resin larger than the volume of the space between the IC chip 1 and the circuit board, the resin can flow out from this space, thereby achieving a sealing effect. After that, when the heated tool 8 rises, the heating source is lost, so that the temperature of the IC chip 1 and the anisotropic conductive film 10 decreases rapidly, and the anisotropic conductive film 10 loses fluidity. 5F, the IC chip 1 is fixed on the circuit board 4 by resin 10s constituting the anisotropic conductive film 10. In addition, when the circuit board 4 side is heated, the temperature of the joining tool 8 can be further lowered.

이와 같이 하면, 열경화성 수지 시이트(6) 대신에 이방성 도전막(10)을 사용할 수 있으며, 또한, 이방성 도전막(10)에 함유되는 도전입자(10a)로서 니켈분말에 금도금을 한 것을 사용함으로써, 접속저항값을 저하시킬 수 있어서 가장 적합하다.In this way, the anisotropic conductive film 10 can be used instead of the thermosetting resin sheet 6, and by using the gold-plated nickel powder as the electrically-conductive particle 10a contained in the anisotropic conductive film 10, The connection resistance value can be reduced, which is most suitable.

또한, 도 1A에서 도 1H까지는, 열경화성 수지 시이트(6) 또는 열경화성 접착제(6b)를 회로기판(4)측에 형성하는 것에 대하여 설명하였으나, 이에 한정되는 것은 아니며, 도 1I 또는 도 1J에 도시한 바와 같이 IC칩(1)측에 형성하도록 하여도 좋다. 이 경우, 특히, 열경화성 수지 시이트(6)의 경우에는, 열경화성 수지 시이트(6)의 회로기판측으로 떼어낼 수 있도록 배치된 세퍼레이터(6a)와 함께 고무 등의 탄성체(117)에 IC칩(1)을 밀어 붙여셔, 범프(3)의 형상에 따라서 열경화성 수지 시이트(6)를 IC칩(1)에 첩부되도록 하여도 좋다. 다음에, 본 발명의 제2실시형태에 관한 실장방법 및 장치를 도 7A∼7C 및 도 8A∼8C에 의해 설명한다. 전술한 바와 같이, IC칩(1)상의 전극(2)에 돌기전극(범프)(3)을 형성하여 두고, 회로기판(4)에는, 도 7B, 7C 및 도 8A에 도시한 바와 같이, IC칩(1)의 전극(2)의 안쪽단부를 연결한 외형치수(OL)보다 작은 형상치수의 시이트 형상의 열경화성 수지 또는 열경화성 접착제(6)를 회로기판(4)의 전극(5)을 연결한 중심부분에 첩부하거나 또는 도포하여 둔다. 다음에, 범프(3)와 회로기판(4)의 전극(5)의 위치를 맞추어, 도 7A 및 도 8B에 도시한 바와 같이, 가열된 헤드(8)에 의하여, IC칩(1)을 회로기판(4)에 가압하여, 기판(4)의 휨의 교정을 동시에 실행하면서, IC칩(1)과 회로기판(4) 사이에 개재하는 열경화성 수지 또는 열경화성 접착제(6)를 경화한다. 이때, 열경화성 수지 또는 열경화성 접착제(6)는, 헤드(8)로부터 IC칩(1)을 개재하여 가하여진 열에 의하여 상기한 바와 같이 연화하여, 도 8C와 같이 첩부된 위치에서 가압되어 바깥쪽으로 향하여 흘러나온다. 이 흘러나온 열경화성 수지 또는 열경화성 접착제(6)가 밀봉재료(underfill)로 되어, 범프(3)와 전극(5)의 접합의 신뢰성을 현저하게 향상시킨다. 또, 어떤 일정시간이 지나면, 상기 열경화성 수지 또는 열경화성 접착제(6)에서는 서서히 경화가 진행하여, 최종적으로는 경화한 수지(6s)에 의해 IC칩(1)과 회로기판(4)을 접합하게 된다. IC칩(1)을 가압하는 접합공구(8)를 상승시킴으로써, IC칩(1)과 회로기판(4)의 전극(5)의 접합이 완료한다. 엄밀하게 말하면, 열경화의 경우에는, 열경화성 수지의 반응은 가열하는 동안에 진행하여 접합공구(8)가 상승함과 동시에 유동성은 거의 없어진다. 상기한 바와 같은 방법에 의하면, 접합전에는 열경화성 수지 또는 열경화성 접착제(6)가 전극(5)을 피복하고 있지 않으므로, 접합하는 경우에 범프(3)가 전극(5)에 직접 접촉하여, 전극(5)의 밑에 열경화성 수지 또는 열경화성 접착제(6)가 뒤섞이지 않아서, 범프(3)와 전극(5) 사이에서의 접속저항값을 낮출 수 있다, 또한, 회로기판측을 가열하여 두면, 접합헤드(8)의 온도를 보다 낮게 할 수 있다.1A to 1H have been described in which the thermosetting resin sheet 6 or the thermosetting adhesive 6b is formed on the circuit board 4 side, but the present invention is not limited thereto. As described above, it may be formed on the IC chip 1 side. In this case, in particular, in the case of the thermosetting resin sheet 6, the IC chip 1 is placed on an elastic body 117 such as rubber together with the separator 6a arranged so that the thermosetting resin sheet 6 can be detached to the circuit board side. The thermosetting resin sheet 6 may be attached to the IC chip 1 in accordance with the shape of the bump 3. Next, the mounting method and apparatus which concerns on 2nd Embodiment of this invention are demonstrated with FIGS. 7A-7C and 8A-8C. As described above, the protruding electrode (bump) 3 is formed on the electrode 2 on the IC chip 1, and the circuit board 4 has the IC as shown in FIGS. 7B, 7C and 8A. The sheet-shaped thermosetting resin or thermosetting adhesive 6 having a shape dimension smaller than the external dimension OL connecting the inner end of the electrode 2 of the chip 1 is connected to the electrodes 5 of the circuit board 4. It is affixed or apply | coated to a central part. Next, the IC chip 1 is circuited by the heated head 8 as shown in FIGS. 7A and 8B by aligning the positions of the bumps 3 and the electrodes 5 of the circuit board 4. The thermosetting resin or the thermosetting adhesive 6 interposed between the IC chip 1 and the circuit board 4 is cured while pressurizing the substrate 4 to simultaneously correct the warpage of the substrate 4. At this time, the thermosetting resin or the thermosetting adhesive 6 is softened as described above by the heat applied from the head 8 via the IC chip 1, and is pressed at the attached position as shown in FIG. 8C and flows outward. Comes out. This flow-out thermosetting resin or thermosetting adhesive 6 becomes an underfill, which significantly improves the reliability of the bonding between the bump 3 and the electrode 5. After a certain period of time, the thermosetting resin or the thermosetting adhesive 6 is gradually cured, and finally the IC chip 1 and the circuit board 4 are joined by the cured resin 6s. . By raising the joining tool 8 which presses the IC chip 1, the joining of the IC chip 1 and the electrode 5 of the circuit board 4 is completed. Strictly speaking, in the case of thermosetting, the reaction of the thermosetting resin proceeds during the heating to increase the joining tool 8 and almost no fluidity. According to the above method, since the thermosetting resin or the thermosetting adhesive 6 does not cover the electrode 5 before joining, the bump 3 directly contacts the electrode 5 when joining, and the electrode 5 The thermosetting resin or the thermosetting adhesive 6 is not mixed under the) so that the connection resistance value between the bump 3 and the electrode 5 can be lowered. Further, when the circuit board side is heated, the bonding head 8 Can lower the temperature.

다음에, 본 발명의 제3실시형태에 관한 실장방법 및 장치를 도 9A∼9C에 의해 설명한다. 이 제3실시형태는, 레벨링한 다음에 접합하는 실장방법 및 장치이다.Next, the mounting method and apparatus which concerns on 3rd Embodiment of this invention are demonstrated with reference to FIGS. 9A-9C. This third embodiment is a mounting method and apparatus for joining after leveling.

먼저, 도 9A에 도시한 바와 같이, IC칩(1)상의 전극(2)에 돌기전극(범프)(3)을 앞에서 설명한 방법에 따라 와이어본딩장치를 사용하여 형성하고, 접시형의 용기에 수납된 도전성 접착제(11)에 범프(3)를 담그어서 범프(3)에 도전성 접착제(11)를 전사한다. 한편, 회로기판(4)에는, IC칩(1)의 전극(2)을 연결한 외형치수(L1)보다 작은 형상치수(L2)의 열경화성 수지 시이트 또는 열경화성 접착제(6)를 회로기판(4)의 전극(5)을 연결한 중심부분에 첩부하거나 또는 도포하여 둔다. 다음에, 도 9C에 도시한 바와 같이, 범프(3)와 회로기판(4)의 전극(5)의 위치를 맞추고, 가열된 접합헤드(8)에 의하여 IC칩(1)을 회로기판(4)에 가압하여, 기판(4)의 휨의 교정을 동시에 실시하면서 IC칩(1)과 회로기판(4) 사이에 개재하는 열경화성 수지 또는 열경화성 접착제(6)를 경화하여, 경화한 수지(6s)에 의하여 IC칩(1)과 회로기판(4)을 접합한다. 이때, 열경화성 수지 또는 열경화성 접착제(6)는, 접합헤드(8)로부터 IC칩을 개재하여 가하여진 열에 의하여 상기한 바와 같이 연화하고, 도 9B와 같이 첩부된 위치로부터 가압되어서 바깥쪽으로 향하여 흘러나온다. 이렇게 흘러나온 열경화성 수지 또는 열경화성 접착제(6)가 밀봉재료(underfill)로 되어, 범프(3)와 전극(5) 사이에서의 접합의 신뢰성을 현저하게 향상시킨다. 또, 이때, 범프(3)에 부착한 도전성 접착제(11)도 경화하게 되어, 도전성 접착제(11)만을 경화하는 가열공정이 불필요하게 된다. 이어서, IC칩(1)을 가압하는 공구(8)를 상승시킨다. 이상의 공정에 의하여, IC칩(1)과 회로기판(4)의 전극(5)의 접합이 완료한다. 또, 회로기판측을 가열하여 두면, 접합헤드(8)의 온도를 보다 낮출 수 있다. 또, L2＜LB 로 하여도 더욱 적합하다. 또, 상기 가열을 단시간에 실시한 후, 다시 본 가열을 노(로(爐)) 등에서 실시하여도 좋다, 이때에는 수지의 임의의 경화수축작용을 이용함으로써 동등한 작용을 얻을 수 있다. 또, 언더필(underfill)을 모두 상기 수지로 하지 않고, 도 9D에 도시한 바와 같이, 그 일부를 이 방법으로 실시하며, 후에, 도 9E에 도시한 바와 같이, 언더필(400)을 주입하도록 하여도 좋다.First, as shown in FIG. 9A, the protruding electrode (bump) 3 is formed on the electrode 2 on the IC chip 1 using a wire bonding apparatus according to the method described above, and stored in a dish-shaped container. The bumps 3 are immersed in the conductive adhesives 11 to transfer the conductive adhesives 11 to the bumps 3. On the other hand, the circuit board 4 includes a thermosetting resin sheet or a thermosetting adhesive 6 having a shape dimension L 2 smaller than the external dimension L 1 connecting the electrodes 2 of the IC chip 1 to the circuit board ( It is affixed or apply | coated to the center part which connected the electrode 5 of 4). Next, as shown in FIG. 9C, the bumps 3 and the electrodes 5 of the circuit board 4 are aligned, and the IC chip 1 is connected to the circuit board 4 by the heated bonding head 8. 6s of the thermosetting resin or the thermosetting adhesive 6 interposed between the IC chip 1 and the circuit board 4 while being cured at the same time and simultaneously correcting the warpage of the substrate 4. The IC chip 1 and the circuit board 4 are joined by this. At this time, the thermosetting resin or the thermosetting adhesive 6 is softened as described above by the heat applied from the bonding head 8 via the IC chip, and is pressed out from the bonded position as shown in FIG. 9B and flows outward. The thermosetting resin or the thermosetting adhesive 6 thus flowed out becomes an underfill, which significantly improves the reliability of the bonding between the bump 3 and the electrode 5. At this time, the conductive adhesive 11 attached to the bump 3 is also cured, and the heating step of curing only the conductive adhesive 11 is unnecessary. Next, the tool 8 which presses the IC chip 1 is raised. By the above steps, the bonding between the IC chip 1 and the electrode 5 of the circuit board 4 is completed. If the circuit board side is heated, the temperature of the bonding head 8 can be lowered further. Further, L 2 is more suitable to be <LB. Moreover, after performing the said heating for a short time, this heating may be performed again in a furnace etc. At this time, the equivalent effect can be acquired by using arbitrary hardening shrinkage | action of resin. In addition, as shown in Fig. 9D, a part of the method is implemented as shown in Fig. 9D without any underfill being made of the above resin, and then, as shown in Fig. 9E, the underfill 400 may be injected. good.

또한, 도 9A에 있어서, IC칩(1)을 보유하는 공구(8)에 세라믹 히터 또는 펄스 히터 등의 히터(8)를 내장시켜서 도 9B의 공정을 실행하기 전에 도전성 접착제(11)를 가열(예컨대 60에서 200℃로 가열)하여 경화시켜 도전성 접착제(11)가 범프(3)의 일부로서 기능하도록 하면, 열경화성 수지 시이트 또는 열경화성 접착제(6)를 통해서 관통시킬 수 있다. 따라서, 이 경우에는, IC칩(1)의 전극(2)을 연결한 외형치수(L1) 이상의 커다란 형상치수(L2)의 열경화성 수지 시이트 또는 열경화성 접착제(6)를 사용할 수 있다. 바꾸어 말하면, 열경화성 수지 시이트 또는 열경화성 접착제(6)의 크기를 모두 고려할 필요가 없어진다. 전의 실시형태와 마찬가지로, 상기 열경화성 수지 시이트 또는 열경화성 접착제(6) 대신 이방성 도전막(10)을 사용하여도 좋다. 더욱이, 이방성 도전막에 포함되는 도전입자(10a)가 니켈분말에 금도금을 한 것을 사용하고 있으므로, 범프(3)와 전극(5) 사이의 접속저항값을 저하시킬 수 있어 더욱 적합하다.In FIG. 9A, a heater 8 such as a ceramic heater or a pulse heater is incorporated in the tool 8 holding the IC chip 1 to heat the conductive adhesive 11 before performing the process of FIG. 9B. For example, if the conductive adhesive 11 functions as a part of the bump 3 to be cured by heating at 60 to 200 ° C., it can penetrate through the thermosetting resin sheet or the thermosetting adhesive 6. Therefore, in this case, it is possible to use a thermosetting resin sheet or the thermosetting adhesive 6 of the IC chip 1, the external dimensions (L 1) a large-like dimensions (L 2) than the connection electrode (2). In other words, it is not necessary to consider all the sizes of the thermosetting resin sheet or the thermosetting adhesive 6. As in the previous embodiment, the anisotropic conductive film 10 may be used instead of the thermosetting resin sheet or the thermosetting adhesive 6. Moreover, since the electroconductive particle 10a contained in an anisotropic conductive film uses the thing which gold-plated the nickel powder, the connection resistance value between bump 3 and electrode 5 can be reduced, and it is more suitable.

본 발명의 제4실시형태에 관한 실장방법 및 장치를 도 10A∼10F에 의거하여 설명한다. 도 10A에 도시한 바와 같이, IC칩(1)을 회로기판(4)에 실장하는 경우에, IC칩(1)상의 전극(패드)(2)에 돌기전극(범프)(3)을 형성한다. 한편, 도 10B에 도시한 바와 같이, 열경화성 수지(6)의 한쪽 면 또는 양면에 플럭스 성분을 도포하여 건조함으로써, 플럭스층(12)을 형성한다. 또는 플럭스 성분을 건조시켜서 형성한 플럭스 성분 시이트를 상기 열경화성 수지 시이트(6)에 첩부하여 플럭스층(12)을 형성한다. 이와 같이 플럭스층(12)을 구비한 열경화성 수지 시이트(6)를 도 10C에 도시한 바와 같이, 회로기판(4)에 첩부한다. 이때, 플럭스층(12)이 회로기판(4)에 접촉하도록 열경화성 수지 시이트(6)를 첩부한다. 다음에, 범프(3)와 회로기판(4)의 전극(5)의 위치를 맞추어서, 가열된 헤드(8)로 IC칩(1)을 회로기판(4)에 가압한다. 이때, 도 10E에 도시한 바와 같이 열경화성 수지 시이트(6)의 IC칩 측에도 플럭스층(12)을 도포, 형성하는 경우에는, 범프(3)가 상기 열경화성 수지 시이트(6)의 플럭스층(12)에 접촉하여 부착한다, 또, 열경화성 수지 시이트(6)의 기판측에 형성된 플럭스층(12)은 도 10D에 도시한 바와 같이, 기판측의 전극(5)에 형성된 접합 금속층(13)에 상기 열경화성 수지 시이트(6)가 기판(4)에 첩부된 단계에서 부착한다, 헤드(8)에 의하여 IC칩(1)을 회로기판(4)에 가압하여가면 헤드(8)로부터 열이 IC칩(1)을 개재하여 열경화성 수지 시이트(6)에 전달됨과 동시에, 기판(4)의 휨의 교정을 동시에 실시하면서, 플럭스층(12)의 플럭스 성분을 활성화한다. 또, IC칩(1)과 회로기판(4) 사이에 개재하는 열경화성 수지 시이트(6)를 경화하여, 그 수지 시이트(6)를 범프(3)가 돌파하는 경우에 플럭스층(12)의 플럭스가 범프(3)에 부착함과 동시에, 상기 열에 의하여 용융되며, 또한 회로기판(4)의 전극(5)상에 형성된 접합금속층(13)과 접촉하므로써, 도 10F에 도시한 바와 같이, 범프(3)와 전극(5)이 플럭스 및 접합금속층(13)을 개재하여 접합하여 IC칩(1)과 회로기판(4)을 접합한다.A mounting method and apparatus according to a fourth embodiment of the present invention will be described with reference to Figs. 10A to 10F. As shown in FIG. 10A, when the IC chip 1 is mounted on the circuit board 4, the protruding electrode (bump) 3 is formed on the electrode (pad) 2 on the IC chip 1. . On the other hand, as shown in FIG. 10B, the flux layer 12 is formed by apply | coating and drying a flux component to one side or both surfaces of the thermosetting resin 6. As shown in FIG. Or the flux component sheet formed by drying a flux component is affixed on the said thermosetting resin sheet 6, and the flux layer 12 is formed. Thus, the thermosetting resin sheet 6 provided with the flux layer 12 is affixed on the circuit board 4, as shown to FIG. 10C. At this time, the thermosetting resin sheet 6 is affixed so that the flux layer 12 may contact the circuit board 4. Next, the bumps 3 and the electrodes 5 of the circuit board 4 are aligned to press the IC chip 1 against the circuit board 4 with the heated head 8. At this time, when the flux layer 12 is also applied and formed on the IC chip side of the thermosetting resin sheet 6 as shown in FIG. 10E, the bumps 3 are formed on the flux layer 12 of the thermosetting resin sheet 6. The flux layer 12 formed on the substrate side of the thermosetting resin sheet 6 is bonded to the bonding metal layer 13 formed on the electrode 5 on the substrate side as shown in FIG. 10D. The resin sheet 6 is attached at the step of being affixed to the substrate 4. When the IC chip 1 is pressed against the circuit board 4 by the head 8, heat is transferred from the head 8 to the IC chip 1. The flux component of the flux layer 12 is activated, while being transmitted to the thermosetting resin sheet 6 via), and simultaneously correcting warping of the substrate 4. In addition, the flux of the flux layer 12 when the thermosetting resin sheet 6 interposed between the IC chip 1 and the circuit board 4 is cured and the bump 3 breaks through the resin sheet 6. Is attached to the bump 3 and is melted by the heat and in contact with the bonding metal layer 13 formed on the electrode 5 of the circuit board 4, as shown in FIG. 10F. 3) and the electrode 5 are bonded through the flux and the bonding metal layer 13 to bond the IC chip 1 and the circuit board 4.

범프(3)로서, 예컨대 비교적 저온 300℃ 이하에서 용융하는 금속을 사용하는 경우에는, 회로기판(4)에 접합금속층(13)을 구비하거나 구비하지 않아도 좋음은 물론이다. 또, 회로기판측을 가열하여 두면, 접합헤드(8)의 온도를 보다 낮게 할 수 있다.As the bump 3, for example, in the case of using a metal that is melted at a relatively low temperature of 300 ° C. or less, it is, of course, not necessary to provide or have the joining metal layer 13 in the circuit board 4. If the circuit board side is heated, the temperature of the bonding head 8 can be lowered.

또한, 이 실시형태에 있어서도 전의 실시형태와 마찬가지로 열경화성 수지 시이트(6) 대신 열경화성 접착제나 이방성 도전막 시이트(10)를 사용할 수 있음은 물론이다.In addition, also in this embodiment, the thermosetting adhesive agent and the anisotropic conductive film sheet 10 can be used instead of the thermosetting resin sheet 6 similarly to previous embodiment.

다음에, 본 발명의 제5실시형태에 관한 실장방법 및 장치를 도 11A∼11G에 의거하여 설명한다. 이 제5실시형태는, 접합과 동시이거나 동시가 아니어도 레벨링은 전혀 하지 않는 실장방법 및 장치이다.Next, a mounting method and apparatus according to the fifth embodiment of the present invention will be described with reference to Figs. 11A to 11G. This fifth embodiment is a mounting method and apparatus that performs no leveling at the same time or not simultaneously with the joining.

도 11E, 11F에 도시한 바와 같이 IC칩(1)을 회로기판(4)에 실장하는 경우에 IC칩(1)에 도시하지 않은 와이어본딩장치를 이용하여 IC칩(1)상의 전극(2)에 돌기전극(범프)(3)을 형성하여 둔다. 도 11A, 11B에 도시한 바와 같이, 열경화성 수지 시이트(6)에는, 범프(3) 및 회로기판(4)의 전극(5)에 대응하는 위치에, 범프(3)와 기판(4)의 전극(5)을 접촉시켜서 도통시키는 방향(수지 시이트(6)의 두께방향)으로 관통한 관통구멍(15)을 형성한다. 그리고, 도 11C, 11D에 도시한 바와 같이, 도전입자(14), 예컨대, 표면에 금도금을 한 수지보올, 또는 니켈입자, 또는 은이나 은-팔라듐, 또는 금으로 된 도전입자, 또는 도전페이스트 또는 쇠구슬로 된 입자를 페이스트 형상으로 한 것을 상기 관통구멍(15)내에 인쇄로 또는 압착(squeeze)으로 밀어넣는 등으로 하여 매립하여서 도전성을 갖는 열경화성 수지 시이트(66)를 형성한다. 이와 같이 형성된 수지 시이트(66)를 도 11E, 11F에 도시한 바와 같이 회로기판(4)의 전극(5)과 위치를 맞추어서 접착한다. 페이스트 형상의 상기 도전입자(14)를 하는 경우에는, 열경화성 수지 시이트(66)의 열경화성 접착제의 접합시의 점도보다도 상기 페이스트의 점도를 높게 하여 두면, IC칩(1)의 가압시에 상기 페이스트가 상기 열경화성 수지 시이트(66)의 수지에 흘러가기 어렵게 되어, 보다 적합하다. 다음에, 도 11E, 11F에 도시한 바와 같이, IC칩(1)의 범프(3)와 회로기판(4)의 전극(5)의 위치를 맞추어, 가열된 접합헤드(8)에 의하여 IC칩(1)을 회로기판(4)에 가압하여, 범프(3)의 레벨링과 기판(4)의 휨 교정을 동시에 하면서, IC칩(1)과 회로기판(4) 사이에 개재하는 열경화성 수지 시이트(66)속의 열경화성 수지를 경화하여, 도 11G에 도시한 바와 같이, 경화된 수지(66s)에 의하여 IC칩(1)과 회로기판(4)을 접합한다. 또, 회로기판측을 가열하여두면, 접합헤드(8)의 온도를 보다 낮게 할 수 있다.11E and 11F, when the IC chip 1 is mounted on the circuit board 4, the electrode 2 on the IC chip 1 using a wire bonding apparatus not shown in the IC chip 1 is used. Protrusion electrodes (bumps) 3 are formed on the substrate. 11A and 11B, the thermosetting resin sheet 6 includes the bumps 3 and the electrodes of the substrate 4 at positions corresponding to the bumps 3 and the electrodes 5 of the circuit board 4. The through hole 15 which penetrates in the direction (thickness direction of the resin sheet 6) which contacts 5 and is made to conduct is formed. 11C and 11D, the conductive particles 14, for example, a resin plate with gold plating on the surface, or nickel particles, or conductive particles made of silver or silver-palladium, or gold, or conductive paste or The particles made of iron beads are pasted into the through-holes 15 by printing or squeeze or the like to form a thermosetting resin sheet 66 having conductivity. The resin sheet 66 thus formed is bonded to each other by being aligned with the electrode 5 of the circuit board 4 as shown in Figs. 11E and 11F. In the case of the paste-shaped conductive particles 14, if the viscosity of the paste is made higher than the viscosity at the time of bonding the thermosetting adhesive of the thermosetting resin sheet 66, the paste may be pressed at the time of pressurization of the IC chip 1. It becomes difficult to flow in resin of the said thermosetting resin sheet 66, and it is more suitable. Next, as shown in Figs. 11E and 11F, the bumps 3 of the IC chip 1 and the electrodes 5 of the circuit board 4 are aligned so that the IC chips are heated by the bonded bonding heads 8. The thermosetting resin sheet interposed between the IC chip 1 and the circuit board 4 while pressing (1) against the circuit board 4 while simultaneously performing leveling of the bumps 3 and bending correction of the board 4. The thermosetting resin in 66) is cured and the IC chip 1 and the circuit board 4 are bonded by the cured resin 66s as shown in Fig. 11G. If the circuit board side is heated, the temperature of the bonding head 8 can be lowered.

다음에, 본 발명의 제6실시형태에 관한 실장방법 및 장치를 도 12A∼12H에 의거하여 설명한다. 이 제6실시형태는 접합과 동시이거나 동시가 아니어도 레벨링을 전혀 실행하지 않는 실장방법 및 장치이다.Next, the mounting method and apparatus which concerns on 6th Embodiment of this invention are demonstrated based on FIGS. 12A-12H. This sixth embodiment is a mounting method and apparatus that does not perform leveling at all, either simultaneously or not simultaneously with the joining.

도 12A에 있어서, 열경화성 수지 시이트(66)에 회로기판(4)의 전극(5)에 대응하는 위치에, 회로기판(4)의 전극(5)과 상호 끼이는 방향으로, 상호 도통시키는 방향으로 구멍(15)을 형성하며, 도 12B에 도시한 바와 같이, 그 구멍(15)에 도통입자(16)를 삽입하여 형성한다. 이 도전입자(16)로서는, 그 입자직경이, 적어도 IC칩(1)의 전극(2)에 입히는 패시베이션(passivation)막(1a)의 두께(tpc)(도 12H 참조)보다 크고, 기판(4)의 전극(5)의 두께(te) (도 12C 참조)보다 작은 치수이며, 또한, 도 12F에 도시한 바와 같이 수지보올(16a)의 표면에 금도금(16b)을 한 도전입자(16), 또는 도 12E에 도시한 바와 같이 니켈입자(17a)의 표면에 금도금(17b)을 한 도전입자(17), 또는 도 12G에 도시한 바와 같이 은이나 은-팔라듐 또는 금 그 자체로 된 도전입자(18), 또는 도전페이스트 또는 쇠구슬로 된 입자 등이 바람직하다, 다음에, 도 12C에 도시한 바와 같이, IC칩(1)의 전극(2)을 회로기판(4)의 전극(5)과 위치를 맞추어 첩부한 다음에, IC칩(1)의 전극(2)과 회로기판(4)의 전극(5)의 위치를 맞추어, 전의 실시형태와 마찬가지로, 가열된 접합헤드(8)로, 이 헤드(8)에 연결된 초음파진동 발진장치로부터 초음파진동을 헤드(8)를 개재하여 IC칩(1)에 인가하면서 IC칩(1)을 회로기판(4)에 가압하여, 상기 도전입자(16)의 표면의 금속을 개재하여, IC칩(1)의 A1전극(2)과 회로기판(4)의 전극(5)을 접합한다. 동시에, IC칩(1)과 회로기판(4) 사이에 개재하는 열경화성 수지 시이트(66)를 경화하여, 도 12D에 도시한 바와 같이, 경화된 수지(66s)로 IC칩(1)과 회로기판(4)을 접합한다. 가장 적합하게는, 회로기판(4)의 전극(5)의 표면을 금도금하여 두는 것이 바람직하다. 또, 회로기판측을 가열하여두면, 접합헤드(8)의 온도를 보다 낮게할 수 있다. 여기서, 초음파에 의하여, IC칩(1)의 패드(pad)상의 A1막의 산화물을 부수어, 새로운 A1을 노출시킬 수 있다. 또, 접합할 때의 온도를 낮출수도 있음과 동시에, Au-Al합금화를 촉진시킬 수도 있다. 더욱이, 상기 실시형태에 있어서는, 앞의 실시형태와 마찬가지로 열경화성 수지 시이트 대신에 열경화성 접착제나 이방성 도전막(10)을 사용할 수도 있다.In FIG. 12A, the thermosetting resin sheet 66 is in a position corresponding to the electrodes 5 of the circuit board 4 at a position corresponding to the electrodes 5 of the circuit board 4, and in a direction of mutual conduction. A hole 15 is formed, and as shown in FIG. 12B, the conductive particles 16 are inserted into the hole 15 to form it. As the conductive particles 16, the particle diameter thereof is larger than the thickness t pc (see FIG. 12H) of the passivation film 1a coated on the electrode 2 of the IC chip 1, and the substrate ( A conductive particle 16 having a size smaller than the thickness t e (see FIG. 12C) of the electrode 5 of FIG. 4 and having a gold plating 16b formed on the surface of the resin bowl 16a as shown in FIG. 12F. Or conductive particles 17 having a gold plated 17b on the surface of the nickel particles 17a as shown in FIG. 12E, or conductive silver or silver-palladium or gold itself as shown in FIG. 12G. Particles 18, or particles made of conductive paste or metal beads are preferable. Next, as shown in Fig. 12C, the electrode 2 of the IC chip 1 is replaced by the electrodes 5 of the circuit board 4; ) And then attach the electrode 2 of the IC chip 1 and the electrode 5 of the circuit board 4 to the heated junction head 8 in the same manner as in the previous embodiment. To this head (8) By applying the ultrasonic vibration from the ultrasonic wave oscillation device to the IC chip 1 via the head 8, the IC chip 1 is pressed against the circuit board 4 to press the metal on the surface of the conductive particles 16. The A1 electrode 2 of the IC chip 1 and the electrode 5 of the circuit board 4 are bonded to each other. At the same time, the thermosetting resin sheet 66 interposed between the IC chip 1 and the circuit board 4 is cured, and as shown in Fig. 12D, the IC chip 1 and the circuit board are made of cured resin 66s. Join (4). Most suitably, the surface of the electrode 5 of the circuit board 4 is preferably plated with gold. If the circuit board side is heated, the temperature of the bonding head 8 can be lowered. Here, by the ultrasonic waves, the oxide of the A1 film on the pad of the IC chip 1 can be broken down to expose new A1. Moreover, the temperature at the time of joining can be reduced and Au-Al alloying can also be promoted. Moreover, in the said embodiment, the thermosetting adhesive and the anisotropic conductive film 10 can also be used instead of the thermosetting resin sheet similarly to the previous embodiment.

다음에, 본 발명의 제7실시형태에 관한 실장방법 및 장치를 도 15A∼15G에 의거하여 설명한다. 이 제7실시형태는 접합과 동시에 레벨링을 하는 실장방법 및 장치이다.Next, the mounting method and apparatus which concerns on 7th Embodiment of this invention are demonstrated based on FIGS. 15A-15G. This seventh embodiment is a mounting method and apparatus for leveling simultaneously with bonding.

도 15A에 도시한 IC칩(1)의 전극(2)에 형성된 범프(3)를 도 15B에 도시한 바와 같이, IC칩(1)을 공구(8)로 유지하면서, 도전성 페이스트통(101)의 도전성 페이스트(100)내에 담금으로써, 도 15C에 도시내한 바와 같이, 범프(3)에 도전성 페이스트(100)를 부착시킨다, 그런 다음, 도 15C에 도시한 바와 같이, 내장된 히이터(8a)에 의하여 도전성 페이스트(100)를 가열하여 경화시킴으로써, 다음 공정에서 열경화성 수지 시이트(6) 또는 열경화성 접착제(6b)를 관통하기 쉽게 한다. 즉, 이 도전성 페이스트(100)는, 범프(3)의 일부로서 기능하는 것이다. 그 후, 도 15D에 도시한 열경화성 수지 시이트(6)를 올려 놓은 회로기판(4)의 전극(5) 또는 도 15G에 도시한 열경화성 접착제(6b)를 올려 놓은 회로기판(4)의 전극(5)에 대하여, 도 15E에 도시한 바와 같이 상기 범프(3)가 접촉하도록 IC칩(1)을 회로기판(4)에 가압한다. 그 결과, 도 15F에 도시한 바와 같이, 도전성 페이스트(100)를 개재하여 범프(3)와 전극(5)이 전기적으로 접속되며, 또는 경우에 따라서는 범프(3)가 직접 전극(5)에 전기적으로 접속된다. 이와 같이 하여, 도전성 페이스트(100)를 개재시킴으로써 레벨링의 가지런하지 않은 범프(3)를 전극(5)에 접속할 수 있다. 또, 이때, 앞의 실시형태와 마찬가지로, 가열된 접합헤드(8)에 의하여 IC칩(1)을 회로기판(4)에 가압하여 접합할 때, 기판(4)의 휨의 교정을 동시에 실행할 수 있다. 그 위에, 도전성 페이스트(100)로서는 상기한 바와 같은 여러가지의 것을 사용할 수 있다.As shown in FIG. 15B, the bump 3 formed on the electrode 2 of the IC chip 1 shown in FIG. 15A is held by the tool 8 while the IC chip 1 is held by the tool 8. By soaking in the conductive paste 100 of FIG. 15C, the conductive paste 100 is attached to the bump 3, as shown in FIG. 15C. Then, as shown in FIG. 15C, the built-in heater 8a is attached. By heating and hardening the electrically conductive paste 100 by this, it becomes easy to penetrate the thermosetting resin sheet 6 or the thermosetting adhesive 6b in a next process. In other words, the conductive paste 100 functions as part of the bump 3. Thereafter, the electrode 5 of the circuit board 4 on which the thermosetting resin sheet 6 shown in FIG. 15D is placed or the electrode 5 of the circuit board 4 on which the thermosetting adhesive 6b shown in FIG. 15G is placed. ), The IC chip 1 is pressed against the circuit board 4 so that the bumps 3 come into contact with each other as shown in FIG. 15E. As a result, as shown in FIG. 15F, the bump 3 and the electrode 5 are electrically connected via the conductive paste 100, or in some cases, the bump 3 is directly connected to the electrode 5. Electrically connected. In this manner, the uneven bumps 3 of the leveling can be connected to the electrodes 5 by interposing the conductive paste 100. At this time, similarly to the previous embodiment, when the IC chip 1 is pressurized and bonded to the circuit board 4 by the heated bonding head 8, the warping of the substrate 4 can be simultaneously performed. have. As the conductive paste 100, various ones described above can be used thereon.

상기 여러가지의 실시형태에 있어서는, 열경화성 수지 시이트 대신, 열경화성 접착제를 사용할 수 있다. 또, 열경화성 접착제 대신, 이방성 도전막(10)을 사용할 수도 있다. 이 경우에 있어서는, 또한, 이방성 도전막(10)에 포함되는 도전입자로서 니켈분말에 금도금을 한 것을 사용하도록 하면, 범프(3)와 전극(5) 사이에서의 접속저항값을 더욱 저하시킬 수 있어서 가장 적합하다.In the above various embodiments, a thermosetting adhesive may be used instead of the thermosetting resin sheet. In addition, the anisotropic conductive film 10 can also be used instead of the thermosetting adhesive agent. In this case, when the nickel powder is plated with nickel powder as the conductive particles included in the anisotropic conductive film 10, the connection resistance value between the bump 3 and the electrode 5 can be further lowered. Is most suitable for you.

본 발명에 의하면, 전자부품, 예컨대 IC칩과 회로기판을 접합함에 종래 필요하였던 공정의 대부분을 제거할 수 있어, 대단히 생산성이 좋아지게 된다. 또, 접합재료로서 도전입자가 없는 열경화성 수지 시이트 또는 열경화성 접착제를 사용한 경우에는 종래예 2에서 도시한 방법에 비하여 저가인 IC칩의 실장방법을 제공할 수 있다.According to the present invention, most of the processes conventionally required for joining an electronic component such as an IC chip and a circuit board can be eliminated, and the productivity is extremely improved. In addition, when a thermosetting resin sheet or a thermosetting adhesive without conductive particles is used as the bonding material, a method of mounting an IC chip having a lower cost than that in the conventional example 2 can be provided.

나아가서, 다음과 같은 효과도 얻을 수 있다.Furthermore, the following effects can also be obtained.

(1) 범프형성(1) bump formation

범프를 도금으로 형성하는 방법(종래예 2)에서는, 전용의 범프형성공정을 반도체 메이커에서 실행할 필요가 있으며, 한정된 메이커에서밖에 범프의 형성을 할 수 없다. 그런데, 본 발명의 방법에 의하면, 와이어본딩장치에 의하여 범용의 와이어본딩용의 IC칩을 사용할 수 있어, IC칩의 입수가 용이하다.In the method of forming bumps by plating (former example 2), it is necessary to perform a dedicated bump forming step in a semiconductor manufacturer, and bumps can be formed only in a limited manufacturer. By the way, according to the method of the present invention, the IC chip for general wire bonding can be used by the wire bonding apparatus, and the IC chip can be easily obtained.

종래예 1의 방법에 비하여, 도전성 접착제의 전사라고 하는 불안정한 전사공정에서의 접착제의 전사량을 안정시키기 위한 범프레벨링이 불필요하게 되어, 그와 같은 레벨링 공정용의 레벨링장치가 불필요하게 된다.Compared with the method of the conventional example 1, bump leveling for stabilizing the transfer amount of the adhesive in an unstable transfer process called transfer of the conductive adhesive becomes unnecessary, and the leveling device for such a leveling process becomes unnecessary.

본 발명의 상기 제5실시형태의 방법에 의하면, IC칩에의 범프형성이 불필요하여, 보다 간편하고 또한 생산성이 좋고, 염가의 실장방법을 제공할 수 있다.According to the method of the fifth embodiment of the present invention, bump formation on the IC chip is unnecessary, so that a simpler and more productive product can be provided, and a cheaper mounting method can be provided.

(2) IC칩과 회로기판의 접합(2) Bonding IC chip and circuit board

종래예 2의 방법에 의하면, 접속저항은, 범프와 회로기판의 전극 사이에 존재하는 도전입자의 수에 의존하고 있었으나, 본 발명에서는 독립한 공정으로서의 레벨링공정에 있어서 범프를 레벨링하지 않고 회로기판의 전극에 종래예 1, 2 보다도 강한 하중으로 밀어붙여서 접합하므로, 개재하는 입자수에 접속저항값이 좌우되지 않아서, 안정하게 접속저항값을 얻을 수 있다.According to the method of the conventional example 2, the connection resistance was dependent on the number of conductive particles existing between the bumps and the electrodes of the circuit board. However, in the present invention, the circuit board is not leveled in the leveling step as an independent process. Since the electrode is pushed and bonded to the electrode with a stronger load than the conventional examples 1 and 2, the connection resistance value is not influenced by the number of particles interposed, and the connection resistance value can be obtained stably.

범프의 레벨링을 접합과 동시에 실시하므로, 독립한 레벨링공정이 불필요할 뿐 아니라, 접합시에 회로기판의 휨이나 꾸불꾸불함을 변형시켜서 교정하면서 접합하므로, 또는 범프에 부착시킨 도전성 페이스트를 경화하여 접합시에 도전성 페이스트를 변형시킴으로써 범프의 레벨링이 일체 불필요하며, 접합시에 회로기판의 휨이나 꾸불꾸불함을 변형시켜서 교정하면서 접합하므로, 휨이나 꾸불꾸불함에 강하다. 종래예 1에서는 10㎛/IC(1개의 IC칩당 10㎛ 두께 휨의 치수정밀도가 필요함을 의미한다), 종래예 2에서는 2㎛/IC, 종래예 3에서는 1㎛/IC(범프높이의 불규칙함 ±1㎛ 이하)와 같은 고정밀도의 기판이나 범프의 균일화가 필요하며, 실제상은 LCD로 대표되는 유리기판이 사용되고 있다. 그런데, 본 발명의 방법에 의하면, 상기 실시형태에서 설명한 바와 같이, 수지기판, 플렉서블(flexible)기판, 다층 세라믹기판 등을 사용할 수 있으며, 보다 염가이고 범용성이 있는 IC칩의 접합방법을 제공할 수 있다.Since bumping is performed simultaneously with bonding, not only an independent leveling process is required, but also bonding is performed by modifying the warpage and undulation of the circuit board at the time of joining. When the conductive paste is deformed at the time of bumping, the leveling of the bumps is not necessary at all, and the bonding is performed while modifying and correcting the warpage and the undulation of the circuit board at the time of joining. 10 µm / IC in conventional Example 1 (meaning that the dimensional precision of 10 µm thickness warping is required per IC chip), 2 µm / IC in Conventional Example 2, and 1 µm / IC in bump Example 3 (irregular bump height) High-precision substrates or bumps are required, such as ± 1 μm or less, and in reality, glass substrates represented by LCDs are used. By the way, according to the method of the present invention, as described in the above embodiments, a resin substrate, a flexible substrate, a multilayer ceramic substrate, and the like can be used, and a method of joining an IC chip having a more inexpensive and versatile structure can be provided. have.

또, 종래예 1에서 필요로 한 도전성 접착제로 IC칩과 회로기판을 접합한 후에 IC칩의 하부에 밀봉수지(underfill coat)를 할 필요가 없어서, 공정을 단축할 수 있다.Further, after bonding the IC chip and the circuit board with the conductive adhesive required in the prior art example 1, there is no need to underfill coat the lower part of the IC chip, thereby shortening the process.

또한, 상기 열경화성 수지 시이트(66)에 있어서 형성되는 구멍(15)은, IC칩(1)의 전극(2) 또는 범프(3)의 위치, 또는, 회로기판(4)의 전극(5)의 위치중의 어느 한편의 위치에 형성하는 것이 좋다. 예컨대, 회로기판(4)의 전극(5)의 수가 IC칩(1)의 전극(2)의 수 보다 많을 경우에는, IC칩(1)의 전극(2)을 접합하는 것에 필요한 수, 따라서, IC칩(1)의 전극(2)에 대응하는 위치 및 수의 구멍(15)을 형성하는 것이 좋다.In addition, the hole 15 formed in the thermosetting resin sheet 66 is located at the position of the electrode 2 or the bump 3 of the IC chip 1 or the electrode 5 of the circuit board 4. It is good to form in either of the positions. For example, when the number of electrodes 5 of the circuit board 4 is larger than the number of electrodes 2 of the IC chip 1, the number necessary for joining the electrodes 2 of the IC chip 1, and therefore, It is preferable to form the holes 15 of the position and number corresponding to the electrodes 2 of the IC chip 1.

이상, 본 발명에 의하면, 종래에서 행한 어느 접합공법보다도 생산성이 좋고, 저렴한 IC칩과 회로기판의 접합방법 및 그 장치를 제공할 수 있다.As described above, according to the present invention, it is possible to provide a method for joining an IC chip and a circuit board and a device thereof, which are more productive than any conventional bonding method.

명세서, 청구의 범위, 도면, 요약서를 포함한 1996년 12월 27일에 출원된 일본 특허출원 제8-350738호에 개시된 것의 모두는, 참고로서 여기에 도입하였다.All of what is disclosed in Japanese Patent Application No. 8-350738 for which it applied on December 27, 1996, including a specification, a claim, drawing, and a summary, were taken in here as a reference.

본 발명은, 첨부도면을 참조하면서 바람직한 실시형태에 관련하여 충분히 기재되어 있으나, 이 기술의 숙련한 사람들에게 있어서는 여러가지의 변형이나 수정은 명백하다. 이와 같은 변형이나 수정은, 첨부한 청구의 범위에 의한 본 발명의 범위에서 벗어나지 않는 한에 있어서, 그 속에 포함된 것으로 이해해야 한다.The present invention has been sufficiently described in connection with the preferred embodiments with reference to the accompanying drawings, but various changes and modifications are apparent to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims.

Claims (31)

절연성으로 도전입자를 포함하지 않은 열경화성 수지(6, 6b)를 개재시키면서, 회로기판(4)의 전극(5)과 전자부품(1)의 전극(2)에 와이어본딩(wire bonding)에 의해 형성된 범프(3)와 위치맞춤을 행하고,Formed by wire bonding to the electrode 5 of the circuit board 4 and the electrode 2 of the electronic component 1 while interposing the thermosetting resins 6 and 6b which are insulating and do not contain conductive particles. Align with bump 3, 가열하면서, 상기 전자부품을 상기 회로기판에 1 범프당 20gf 이상의 가압력으로 가압하고, 상기 범프의 레벨링과 상기 기판의 휨 교정을 동시에 행하면서, 상기 전자부품과 상기 회로기판의 사이에 개재하는 상기 열경화성 수지를 상기 열로 경화하여, 상기 전자부품과 상기 회로기판을 접합하여 양 전극을 전기적으로 접속하도록 한 것을 특징으로 하는 전자부품의 실장방법.The thermosetting material interposed between the electronic component and the circuit board while heating, pressurizing the electronic component to the circuit board at a pressing force of 20 gf or more per bump, and simultaneously performing leveling of the bump and bending correction of the substrate. A method for mounting an electronic component, wherein the resin is cured with the heat to bond the electronic component and the circuit board to electrically connect both electrodes. 제1항에 있어서, 상기 위치맞춤은 레벨링하지 않고 행하며, 상기 접합은, 가열하면서, 상기 범프의 레벨링과 상기 기판의 휨 교정을 동시에 실행하는 것을 특징으로 하는 전자부품의 실장방법.The electronic component mounting method according to claim 1, wherein the positioning is performed without leveling, and the joining is performed simultaneously with leveling of the bumps and bending correction of the substrate while heating. 제1항에 있어서, 상기 열경화성 수지는 이방성 도전막을 구비한 열경화성 수지 시이트(10)임을 특징으로 하는 전자부품의 실장방법.The method of mounting an electronic part according to claim 1, wherein the thermosetting resin is a thermosetting resin sheet (10) having an anisotropic conductive film. 제1항에 있어서, 상기 위치맞춤 전에 상기 회로기판(4)에 상기 열경화성 수지로서, 상기 전자부품(1)의 전극(2)을 연결한 외형치수(OL)보다 작은 형상치수의 고정형의 열경화성 수지 시이트(6)를 첩부한 다음, 상기 위치맞춤을 행하고,The fixed type thermosetting resin according to claim 1, wherein the thermosetting resin is connected to the circuit board 4 before the alignment, and is smaller than the external dimension OL in which the electrode 2 of the electronic component 1 is connected. After attaching the sheet 6, the above alignment is performed, 상기 접합은, 상기 열경화성 수지 시이트(6)를 가열하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨 교정을 동시에 하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여, 상기 전자부품과 상기 회로기판을 접합하도록 한 것을 특징으로 하는 전자부품의 실장방법.The joining is the thermosetting resin interposed between the electronic component and the circuit board while simultaneously pressing the electronic component to the circuit board while heating the thermosetting resin sheet 6 to perform bending correction of the circuit board. A method of mounting an electronic component, wherein a sheet is cured by the heat to bond the electronic component and the circuit board together. 제1항에 있어서, 상기 위치맞춤 전에, 도전성 접착제(11)를 상기 전자부품(1)의 상기 전극(2)의 상기 범프(3)에 전사하고, 상기 위치맞춤 전에, 상기 회로기판(4)에는, 상기 열경화성 수지로서, 상기 전자부품의 상기 전극을 연결한 외형치수보다 작은 형상치수의 고정형의 열경화성 수지 시이트(6)를 첩부한 다음, 상기 범프와 상기 회로기판의 전극(5)의 위치를 맞추고,The circuit board 4 according to claim 1, wherein before the alignment, the conductive adhesive 11 is transferred to the bumps 3 of the electrodes 2 of the electronic component 1, and before the alignment, the circuit board 4 Next, as the thermosetting resin, a fixed thermosetting resin sheet 6 having a shape dimension smaller than the external dimension connecting the electrodes of the electronic component is attached, and then the position of the bump and the electrode 5 of the circuit board is fixed. Fit, 상기 접합은, 상기 열경화성 수지 시이트(6)를 가열하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨 교정을 동시에 하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여 상기 전자부품과 상기 회로기판을 접합하도록 한 것을 특징으로 하는 전자부품의 실장방법.The joining is the thermosetting resin interposed between the electronic component and the circuit board while simultaneously pressing the electronic component to the circuit board while heating the thermosetting resin sheet 6 to perform bending correction of the circuit board. A method of mounting an electronic component, wherein a sheet is cured by the heat to bond the electronic component to the circuit board. 제1항에 있어서, 상기 회로기판(4)에는, 상기 열경화성 수지로서, 한쪽 면 또는 양면에 플럭스층(12)을 형성한 고정형의 열경화성 수지 시이트(6)를 첩부한 다음, 상기 전자부품(1)의 상기 전극(2)의 상기 범프(3)와 상기 회로기판의 상기 전극(5)의 위치를 맞추고,A fixed thermosetting resin sheet (6) having a flux layer (12) formed on one or both surfaces thereof is affixed to the circuit board (4), and then the electronic component (1). Position the bump 3 of the electrode 2 of the electrode 2 with the electrode 5 of the circuit board, 상기 접합은, 가열된 헤드(8)에 의하여 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨 교정을 동시에 하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 경화하고, 그 수지 시이트를 상기 범프가 돌파하는 경우에 상기 플럭스층의 플럭스 성분이 상기 범프에 부착하여, 이 범프가 상기 회로기판의 상기 전극과 접합되어서 상기 전자부품과 상기 회로기판을 접합하도록 한 것을 특징으로 하는 전자부품의 실장방법.The bonding hardens the thermosetting resin sheet interposed between the electronic component and the circuit board while simultaneously pressing the electronic component to the circuit board by the heated head 8 to simultaneously perform bending correction of the circuit board. And when the bump breaks through the resin sheet, a flux component of the flux layer adheres to the bump so that the bump is joined to the electrode of the circuit board to bond the electronic component and the circuit board. An electronic component mounting method. 제1항에 있어서, 상기 위치맞춤 전에, 상기 전자부품(1)의 상기 전극(2)의 상기 범프(3) 및 상기 회로기판(4)의 상기 전극(5)의 적어도 한편에 대응하는 위치에 형성된 구멍(15)내에, 표면에 금도금을 한 수지보올, 또는 니켈입자, 또는 은이나 은-팔라듐, 또는 금으로 된 도전입자, 또는 도전페이스트, 또는 쇠구슬로 된 입자(14)를 상기 범프와 상기 회로기판의 상기 전극을 도통시키는 방향으로 매립한 고정형의 열경화성 수지 시이트(66)를, 상기 열경화성 수지로서, 상기 회로기판의 상기 전극과 위치를 맞추어 첩부한 다음, 상기 전자부품의 상기 범프와 상기 회로기판의 상기 전극의 위치를 맞추고,2. The apparatus according to claim 1, wherein, before the alignment, at a position corresponding to at least one of the bumps 3 of the electrodes 2 of the electronic component 1 and the electrodes 5 of the circuit board 4. In the formed hole 15, a resin plate coated with a surface of gold, or nickel particles, or conductive particles made of silver or silver-palladium, or gold, or conductive paste, or particles of iron beads 14 are formed with the bumps. The fixed thermosetting resin sheet 66 embedded in the direction in which the electrode of the circuit board is conducted is attached to the electrode of the circuit board in a position where the fixed thermosetting resin sheet 66 is bonded with the bumps of the electronic component. Position the electrode on the circuit board, 상기 접합은, 상기 열경화성 수지 시이트(6)를 가열하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨을 교정하면서 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여 접합하도록 한 것을 특징으로 하는 전자부품의 실장방법.The joining presses the electronic component onto the circuit board while heating the thermosetting resin sheet 6 to correct the warpage of the circuit board while interposing the thermosetting resin sheet interposed between the electronic component and the circuit board. A method of mounting an electronic component, characterized in that it is bonded by curing with heat. 제1항에 있어서, 상기 위치맞춤 전에, 상기 전자부품(1)을 상기 회로기판(4)에 실장하는 경우에, 상기 전자부품의 상기 전극(2) 및 상기 회로기판의 상기 전극(5)의 적어도 한편에 대응하는 위치에 형성된 구멍(15)에, 적어도 상기 전자부품의 전극(2)에 입히는 패시베이션막(1a)의 두께(tpc)보다 크고, 상기 회로기판의 전극의 두께(tpcb)보다 작은 치수이며 또한, 표면에 금도금을 한 수지보올, 또는 니켈입자, 또는 은이나 은-팔라듐, 또는 금으로 된 도전입자, 또는 도전페이스트, 또는 쇠구슬로 된 입자(16)를, 상기 전자부품의 상기 전극과, 상기 회로기판의 상기 회로전극을 서로 끼우는 방향 또는 서로 도통시키는 방향으로 매립한 고정형의 열경화성 수지 시이트(66)를, 상기 열경화성 수지로서, 상기 회로기판의 상기 전극과 위치를 맞추어 첩부한 다음, 상기 전자부품의 상기 전극과 상기 회로기판의 상기 전극의 위치를 맞추고,The method according to claim 1, wherein when mounting the electronic component (1) on the circuit board (4) before the alignment, the electrode (2) of the electronic component and the electrode (5) of the circuit board At least the thickness t pcb of the electrode of the circuit board is greater than the thickness t pc of the passivation film 1a coated on the electrode 2 of the electronic component in the hole 15 formed at the corresponding position. The smaller size and the surface of the resin plate which is gold-plated on the surface, or nickel particles, or conductive particles of silver or silver-palladium, or gold, or conductive paste, or particles of iron beads 16, the electronic component The fixed thermosetting resin sheet 66 embedded in the electrode of the circuit board and the circuit electrode of the circuit board in a direction of sandwiching or conducting with each other is used as the thermosetting resin to be bonded to the electrode of the circuit board. Then, award The electrode of the electronic component and the circuit by aligning the position of the electrode of the substrate, 상기 접합은, 상기 열경화성 수지 시이트(6)를 가열하면서 초음파진동을 상기 전자부품에 인가하면서 상기 전자부품을 상기 회로기판에 가압하여, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여 접합하도록 한 것을 특징으로 하는 전자부품의 실장방법.The bonding presses the electronic component onto the circuit board while applying ultrasonic vibration to the electronic component while heating the thermosetting resin sheet 6, thereby interposing the thermosetting resin sheet interposed between the electronic component and the circuit board. A method for mounting an electronic component, characterized in that to be bonded by curing with the heat. 제3항에 있어서, 상기 이방성 도전막(10)에 포함된 도전입자가, 니켈분말에 금도금을 한 것임을 특징으로 하는 전자부품의 실장방법.4. The method of mounting electronic components according to claim 3, wherein the conductive particles contained in the anisotropic conductive film (10) are gold plated on nickel powder. 제1항∼제9항중 어느 한 항에 있어서, 상기 열경화성 수지는 열경화성 수지 시이트(6)로 한 것을 특징으로 하는 전자부품의 실장방법.The electronic component mounting method according to any one of claims 1 to 9, wherein the thermosetting resin is a thermosetting resin sheet (6). 제10항에 있어서, 상기 열경화성 수지의 시이트(6)는, 그 두께가 접합후의 상기 전자부품의 작용면과 상기 회로기판의 전극(5)이 형성된 면과의 틈새보다 두꺼운 두께로 한 것을 특징으로 하는 전자부품의 실장방법.The sheet 6 of the thermosetting resin is characterized in that its thickness is thicker than the gap between the working surface of the electronic component after bonding and the surface on which the electrode 5 of the circuit board is formed. Method of mounting electronic components 제1항 또는 제2항에 있어서, 상기 열경화성 수지는 열경화성 접착제(6b)로 한 것을 특징으로 하는 전자부품의 실장방법.The electronic component mounting method according to claim 1 or 2, wherein the thermosetting resin is a thermosetting adhesive (6b). 절연성으로 도전입자를 함유하지 않은 열경화성 수지(6, 6b)를 개재시키면서 회로기판(4)의 전극(5)과 전자부품(1)의 전극(2)에 와이어본딩에 의해 형성된 범프(3)와 위치맞춤을 행하는 위치맞춤장치와,Bumps 3 formed by wire bonding the electrodes 5 of the circuit board 4 and the electrodes 2 of the electronic component 1 with the thermosetting resins 6 and 6b not insulating and containing conductive particles; A positioning device for performing positioning; 상기 열경화성 수지(6, 6b)를 가열하는 가열장치(8a)와,A heating device 8a for heating the thermosetting resins 6 and 6b; 상기 가열장치에 의하여 상기 열경화성 수지(6, 6b)를 가열하면서, 상기 전자부품을 상기 회로기판에 1 범프당 20gf 이상의 가압력으로 가압하고, 상기 범프의 레벨링과 상기 기판의 휨 교정을 동시에 행하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지를 상기 열로 경화하여, 상기 전자부품과 상기 회로기판을 접합하여 양전극을 전기적으로 접속하는 접합장치를 구비하는 것을 특징으로 하는 전자부품의 실장장치.While heating the thermosetting resins 6 and 6b by the heating device, the electronic component is pressed to the circuit board at a pressure of 20 gf or more per bump, while simultaneously performing leveling of the bumps and bending correction of the substrate. And a bonding apparatus for curing the thermosetting resin interposed between the electronic component and the circuit board with the heat to bond the electronic component and the circuit board to electrically connect the positive electrodes. . 제13항에 있어서, 상기 위치맞춤장치는, 레벨링하지 않고 위치맞춤을 행하며, 상기 접합장치는, 상기 범프의 레벨링과 상기 기판의 휨 교정을 동시에 실행하는 것을 특징으로 하는 전자부품의 실장장치.The mounting apparatus of claim 13, wherein the alignment device performs alignment without leveling, and the bonding apparatus simultaneously performs leveling of the bumps and bending correction of the substrate. 제13항에 있어서, 상기 열경화성 수지는, 이방성 도전막을 구비한 열경화성 수지의 시이트(10)임을 특징으로 하는 전자부품의 실장장치.The electronic component mounting apparatus according to claim 13, wherein the thermosetting resin is a sheet (10) of a thermosetting resin having an anisotropic conductive film. 제13항에 있어서, 상기 위치맞춤장치는, 상기 회로기판(4)에, 상기 열경화성 수지로서, 상기 전자부품(1)의 전극(2)을 연결한 외형치수(OL)보다 작은 형상치수의 고정형의 열경화성 수지 시이트(6)를 첩부한 다음, 상기 전자부품의 상기 전극의 범프(3)와 상기 회로기판의 전극(5)의 위치를 맞추고,15. The fixed type according to claim 13, wherein the alignment device has a shape dimension smaller than the external dimension OL connecting the electrode 2 of the electronic component 1 to the circuit board 4 as the thermosetting resin. A thermosetting resin sheet 6 is attached, and the bumps 3 of the electrodes of the electronic component are aligned with the electrodes 5 of the circuit board, 상기 접합장치는, 상기 열경화성 수지 시이트(6)를 가열하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨 교정을 동시에 실시하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여, 상기 전자부품과 상기 회로기판을 접합하도록 한 것을 특징으로 하는 전자부품의 실장장치.The bonding apparatus is interposed between the electronic component and the circuit board while pressing the electronic component onto the circuit board while simultaneously heating the thermosetting resin sheet 6 to perform bending correction of the circuit board. A thermosetting resin sheet is cured by said heat, and the said electronic component and said circuit board are bonded together, The mounting apparatus of the electronic component characterized by the above-mentioned. 제13항에 있어서, 상기 위치맞춤장치는, 상기 위치맞춤 전에 도전성 접착제(11)를 상기 전자부품(1)의 상기 전극(2)의 상기 범프(3)에 전사하고, 상기 위치맞춤 전에, 상기 회로기판(4)에는 상기 열경화성 수지로서, 상기 전자부품의 상기 전극을 연결한 외형치수보다 작은 형상치수의 고정형의 열경화성 수지 시이트(6)를 첩부한 다음, 상기 범프와 상기 회로기판의 전극(5)의 위치를 맞추고,The positioning device according to claim 13, wherein the positioning device transfers the conductive adhesive 11 to the bumps 3 of the electrodes 2 of the electronic component 1 before the positioning, and before the positioning, As the thermosetting resin, a fixed thermosetting resin sheet 6 having a shape dimension smaller than the external dimension connecting the electrodes of the electronic component is attached as the thermosetting resin, and then the bumps and the electrodes of the circuit board 5 are attached. ) Position, 상기 접합장치는, 상기 열경화성 수지 시이트(6)를 가열하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨 교정을 동시에 실시하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여, 상기 전자부품과 상기 회로기판을 접합하는 것을 특징으로 하는 전자부품의 실장장치.The bonding apparatus is interposed between the electronic component and the circuit board while pressing the electronic component onto the circuit board while simultaneously heating the thermosetting resin sheet 6 to perform bending correction of the circuit board. A thermosetting resin sheet is cured by the heat, and the electronic component and the circuit board are bonded to each other. 제13항에 있어서, 상기 위치맞춤장치는, 상기 회로기판(4)에는, 상기 열경화성 수지로서, 한쪽 면 또는 양면에 플럭스층(12)을 형성한 고정형의 열경화성 수지 시이트(6)를 첩부한 다음, 상기 전자부품(1)의 상기 전극(2)의 상기 범프(3)와 상기 회로기판의 상기 전극(5)의 위치를 맞추고,14. The positioning device according to claim 13, wherein the positioning device is affixed to the circuit board 4 a fixed thermosetting resin sheet 6 having the flux layer 12 formed on one or both surfaces thereof as the thermosetting resin. The position of the bump 3 of the electrode 2 of the electronic component 1 and the electrode 5 of the circuit board 상기 접합장치는, 가열된 헤드(8)에 의하여 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨 교정을 동시에 실시하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 경화하고, 그 수지 시이트를 상기 범프가 돌파하는 경우에 상기 플럭스층의 플러스 성분이 상기 범프에 부착하여, 그 범프가 상기 회로기판의 상기 전극과 접합되어 상기 전자부품과 상기 회로기판을 접합하는 것을 특징으로 하는 전자부품의 실장장치.The bonding apparatus presses the electronic component onto the circuit board by a heated head 8 to simultaneously perform bending correction of the circuit board while interposing the thermosetting resin sheet between the electronic component and the circuit board. And a positive component of the flux layer adheres to the bumps when the bumps break through the resin sheet, and the bumps are bonded to the electrodes of the circuit boards to bond the electronic components and the circuit boards. An electronic component mounting apparatus, characterized in that. 제13항에 있어서, 상기 위치맞춤장치는, 상기 전자부품(1)의 상기 전극(2)의 상기 범프(3) 및 상기 회로기판(4)의 상기 전극(5)의 적어도 한편에 대응하는 위치에 형성된 구멍(15)내에, 표면에 금도금을 한 수지보올, 또는, 니켈입자, 또는 은이나 은-팔라듐, 또는 금으로 된 도전입자, 또는 도전페이스트, 또는 쇠구슬로 된 입자(14)를 상기 범프와 상기 회로기판의 상기 전극을 도통시키는 방향으로 매립한 고정형의 열경화성 수지 시이트(66)를, 상기 열경화성 수지로서, 상기 회로기판의 상기 전극과 위치를 맞추어 첩부한 다음, 상기 전자부품의 상기 범프와 상기 회로기판의 상기 전극의 위치를 맞추고,The positioning device according to claim 13, wherein the alignment device corresponds to at least one of the bumps 3 of the electrodes 2 of the electronic component 1 and the electrodes 5 of the circuit board 4. In the hole 15 formed in the hole, a resin plate coated with gold, or nickel particles, or conductive particles made of silver or silver-palladium, or gold, or conductive paste or particles of iron beads 14 are formed. The fixed thermosetting resin sheet 66 embedded in the direction in which the bumps and the electrodes of the circuit board are connected to each other is bonded to the electrode of the circuit board in a position such that the fixed thermosetting resin sheet 66 is bonded to the bump of the electronic component. And the position of the electrode of the circuit board, 상기 접합장치는, 상기 경화성 수지 시이트(6)를 가열하면서, 상기 전자부품을 상기 회로기판에 가압하여, 상기 회로기판의 휨을 교정하면서, 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여 접합하는 것을 특징으로 하는 전자부품의 실장장치.The bonding apparatus presses the electronic component onto the circuit board while heating the curable resin sheet 6, and corrects the warpage of the circuit board while interposing the thermosetting resin sheet between the electronic component and the circuit board. The electronic component mounting apparatus, characterized in that the bonding by curing with the heat. 제13항에 있어서, 상기 위치맞춤장치는, 상기 전자부품(1)을 상기 회로기판(4)에 실장하는 경우에, 상기 전자부품의 상기 전극(2) 및 상기 회로기판의 상기 전극(5)의 적어도 한편에 대응하는 위치에 형성된 구멍(15)에, 적어도 상기 전자부품의 전극(2)에 입히는 패시베이션막(1a)의 두께(tpc)보다 크고, 상기 회로기판의 전극의 두께(tpcb)보다 작은 치수이며, 또한 표면에 금도금을 한 수지보올, 또는 니켈입자, 또는 은이나 은-팔라듐, 또는 금으로 된 도전입자, 또는 도전페이스트, 또는 쇄구슬로 된 입자(16)를, 상기 전자부품의 상기 전극과 상기 회로기판의 상기 회로전극을 서로 끼우는 방향으로 또한 서로 도통하는 방향으로 매립한 고정형의 열경화성 수지 시이트(66)를, 상기 열경화성 수지로서, 상기 회로기판의 상기 전극과 위치를 맞추어 첩부한 다음, 상기 전자부품의 상기 전극과 상기 회로기판의 상기 전극의 위치를 맞추고,The electrode according to claim 13, wherein the positioning device is adapted to mount the electronic component (1) on the circuit board (4), the electrode (2) of the electronic component and the electrode (5) of the circuit board. At least a thickness t pc of the passivation film 1a to be applied to the electrode 2 of the electronic component in the hole 15 formed at a position corresponding to at least one of the thicknesses of the electrodes of the circuit board t pcb. And the particles 16 having a size smaller than) and having a gold-plated resin bowl, or nickel particles, or conductive particles of silver or silver-palladium, or gold, or conductive paste, or chain beads 16, The fixed thermosetting resin sheet 66, which is embedded in the direction in which the electrode of the component and the circuit electrode of the circuit board are sandwiched with each other and in the direction of conducting with each other, is positioned as the thermosetting resin with the electrode of the circuit board. After attaching, Position the electrode of the electronic component with the electrode of the circuit board; 상기 접합장치는, 상기 열경화성 수지 시이트(6)를 가열하면서 초음파진동을 상기 전자부품에 인가하면서 상기 전자부품을 상기 회로기판에 가압하여 상기 전자부품과 상기 회로기판 사이에 개재하는 상기 열경화성 수지 시이트를 상기 열로 경화하여 접합하는 것을 특징으로 하는 전자부품의 실장장치.The bonding apparatus presses the electronic component onto the circuit board while applying ultrasonic vibration to the electronic component while heating the thermosetting resin sheet 6 to open the thermosetting resin sheet interposed between the electronic component and the circuit board. A device for mounting an electronic component, comprising curing by bonding with the heat. 제15항에 있어서, 상기 이방성 도전막(10)에 포함되는 도전입자가 니켈분말에 금도금을 한 것임을 특징으로 하는 전자부품의 실장장치.The electronic component mounting apparatus according to claim 15, wherein the conductive particles contained in the anisotropic conductive film (10) are gold plated on nickel powder. 제13항 내지 제21항 중 어느 한 항에 있어서, 상기 열경화성 수지는 열경화성 수지 시이트(6)로 한 것을 특징으로 하는 전자부품의 실장장치.The electronic component mounting apparatus according to any one of claims 13 to 21, wherein the thermosetting resin is a thermosetting resin sheet (6). 제22항에 있어서, 상기 열경화성 수지의 시이트(6)는, 그 두께가 접합 후의 상기 전자부품의 작용면과 상기 회전기판의 전극(5)이 형성된 면과의 틈새보다 두꺼운 두께로 한 것을 특징으로 하는 전자부품의 실장장치.The sheet 6 of the thermosetting resin is characterized in that its thickness is thicker than a gap between the working surface of the electronic component after bonding and the surface on which the electrode 5 of the rotary substrate is formed. Device for mounting electronic components. 제13항 또는 제14항에 있어서, 상기 열경화성 수지는 열경화성 접착제(6b)로 한 것을 특징으로 하는 전자부품의 실장장치.The electronic component mounting apparatus according to claim 13 or 14, wherein the thermosetting resin is a thermosetting adhesive (6b). 제13항 또는 제14항에 있어서, 상기 위치맞춤장치와 상기 접합장치는 하나의 장치로 구성되도록 한 것을 특징으로 하는 전자부품의 실장장치.15. The mounting apparatus of claim 13 or 14, wherein the alignment device and the bonding device are configured as one device. 제1항 내지 제9항 중 어느 한 항에 있어서, 상기 위치맞춤 후, 또한 상기 접합전에 있어서, 상기 범프에 도전성 페이스트(100)를 부착한 다음, 이 도전성 페이스트를 경화시켜서, 상기 범프의 일부로서 기능하게 하고, 상기 접합에 있어서, 상기 열경화성 수지를 상기 경화한 도전성 페이스트가 돌파하여 상기 회로기판의 전극과 전기적으로 접속하도록 한 것을 특징으로 하는 전자부품의 실장방법.10. The conductive paste 100 according to any one of claims 1 to 9, wherein the conductive paste 100 is attached to the bumps after the positioning and before the bonding, and then the conductive paste is cured to form a part of the bumps. And in said bonding, said thermosetting resin breaks through said hardened conductive paste so as to be electrically connected to an electrode of said circuit board. 제13 내지 제21항중 어느 한 항에 있어서, 상기 위치맞춤 후, 또한 상기 접합전에 있어서, 상기 범프에 도전성 페이스트(100)를 부착한 다음, 이 도전성 페이스트를 경화시켜서 상기 범프의 일부로서 기능하게 하고, 상기 접합에 있어서, 상기 열경화성 수지를 상기 경화한 도전성 페이스트가 돌파하여 상기 회로기판의 전극과 전기적으로 접속하도록 한 것을 특징으로 하는 전자부품의 실장장치.22. The method according to any one of claims 13 to 21, wherein after the positioning and before the bonding, the conductive paste 100 is attached to the bumps, and then the conductive paste is cured to function as part of the bumps. And wherein, in the bonding, the thermosetting resin breaks through the cured conductive paste and is electrically connected to an electrode of the circuit board. 제1항 내지 제9항 중 어느 한 항에 있어서, 상기 열경화성 수지 시이트는 상기 회로기판측에 배치되어 있는 것을 특징으로 하는 전자부품의 실장방법.The electronic component mounting method according to any one of claims 1 to 9, wherein the thermosetting resin sheet is disposed on the circuit board side. 제1항 내지 제9항 중 어느 한 항에 있어서, 상기 열경화성 수지 시이트는 상기 전자부품측에 배치되어 있는 것을 특징으로 하는 전자부품의 실장방법.The electronic component mounting method according to any one of claims 1 to 9, wherein the thermosetting resin sheet is disposed on the electronic component side. 제13항 내지 제21항중 어느 한 항에 있어서, 상기 열경화성 수지 시이트는 상기 회로기판측에 배치되어 있는 것을 특징으로 하는 전자부품의 실장장치.The electronic component mounting apparatus according to any one of claims 13 to 21, wherein the thermosetting resin sheet is disposed on the circuit board side. 제13항 내지 제21항중 어느 한 항에 있어서, 상기 열경화성 수지 시이트는 상기 전자부품측에 배치되어 있는 것을 특징으로 하는 전자부품의 실장장치.The electronic component mounting apparatus according to any one of claims 13 to 21, wherein the thermosetting resin sheet is disposed on the electronic component side.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101022921B1 (en) 2008-11-25 2011-03-16 삼성전기주식회사 Manufacturing Method of Printed Circuit Board with Electronic Device

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2781924B1 (en) * 1998-07-30 2002-11-29 St Microelectronics Sa METHOD FOR MOUNTING INTEGRATED CIRCUITS
JP4097378B2 (en) * 1999-01-29 2008-06-11 松下電器産業株式会社 Electronic component mounting method and apparatus
JP4977194B2 (en) * 1999-01-29 2012-07-18 パナソニック株式会社 Electronic component mounting method
KR100502222B1 (en) * 1999-01-29 2005-07-18 마츠시타 덴끼 산교 가부시키가이샤 Electronic parts mounting method and device therefor
JP4097379B2 (en) * 1999-01-29 2008-06-11 松下電器産業株式会社 Electronic component mounting method and apparatus
JP4459258B2 (en) * 1999-01-29 2010-04-28 パナソニック株式会社 Electronic component mounting method
WO2001006558A1 (en) * 1999-07-16 2001-01-25 Matsushita Electric Industrial Co., Ltd. Package of semiconductor device and method of manufacture thereof
US7916492B1 (en) * 1999-08-12 2011-03-29 Ibiden Co., Ltd. Multilayered printed circuit board
EP1087435A1 (en) * 1999-09-23 2001-03-28 Ming-Tung Shen Electro-optic device and method for manufacturing the same
JP3451373B2 (en) * 1999-11-24 2003-09-29 オムロン株式会社 Manufacturing method of data carrier capable of reading electromagnetic wave
JP4489221B2 (en) * 1999-12-14 2010-06-23 大日本印刷株式会社 Wiring member for transfer and manufacturing method thereof
DE10002182A1 (en) * 2000-01-19 2001-08-09 Fraunhofer Ges Forschung Device for electrical and mechanical joining of flat connection structures
ATE352101T1 (en) * 2000-02-09 2007-02-15 Imec Inter Uni Micro Electr METHOD FOR FLIP-CHIP ASSEMBLY OF SEMICONDUCTOR DEVICES USING ADHESIVES
JP2002313841A (en) * 2000-04-14 2002-10-25 Namics Corp Flip-chip mounting method
EP1223612A4 (en) * 2000-05-12 2005-06-29 Matsushita Electric Ind Co Ltd Semiconductor device mounting circuit board, method of producing the same, and method of producing mounting structure using the same
US20040106334A1 (en) * 2000-06-14 2004-06-03 Tatsuo Suzuki Microparticle arrangement film, electrical connection film, electrical connection structure, and microparticle arrangement method
JP2002110715A (en) * 2000-10-04 2002-04-12 Sony Corp Manufacturing method of semiconductor device
KR100373186B1 (en) * 2000-12-29 2003-02-25 엘지이노텍 주식회사 A SAW Device and a Manufacturing Method of the same
DE10103456C1 (en) 2001-01-25 2002-08-29 Infineon Technologies Ag Device with at least one semiconductor component and a printed circuit board and method for producing an electromechanical connection between the two
JP4753329B2 (en) * 2001-02-14 2011-08-24 日東電工株式会社 Thermosetting resin composition and semiconductor device
JP2002270642A (en) * 2001-03-12 2002-09-20 Sony Corp Manufacturing method for semiconductor device
JP4417596B2 (en) * 2001-09-19 2010-02-17 富士通株式会社 Electronic component mounting method
JP4663184B2 (en) * 2001-09-26 2011-03-30 パナソニック株式会社 Manufacturing method of semiconductor device
JP2003179099A (en) * 2001-12-12 2003-06-27 Toshiba Corp Semiconductor device and method of manufacturing the same
JP2003243448A (en) 2002-02-18 2003-08-29 Seiko Epson Corp Semiconductor device, method of manufacturing the same, and electronic device
KR100499134B1 (en) * 2002-10-28 2005-07-04 삼성전자주식회사 Compression bonding method
JP4489411B2 (en) * 2003-01-23 2010-06-23 新光電気工業株式会社 Manufacturing method of electronic component mounting structure
US6815836B2 (en) * 2003-03-24 2004-11-09 Texas Instruments Incorporated Wire bonding for thin semiconductor package
US20050014313A1 (en) * 2003-03-26 2005-01-20 Workman Derek B. Underfill method
US8518304B1 (en) 2003-03-31 2013-08-27 The Research Foundation Of State University Of New York Nano-structure enhancements for anisotropic conductive material and thermal interposers
JPWO2004093508A1 (en) * 2003-04-18 2006-07-13 イビデン株式会社 Flex rigid wiring board
FI20030833A0 (en) 2003-06-04 2003-06-04 Rafsec Oy Smart sticker and method for making a smart sticker
JP3804649B2 (en) * 2003-09-19 2006-08-02 株式会社村田製作所 Electronic circuit device manufacturing method and electronic circuit device
JP4696450B2 (en) * 2004-01-21 2011-06-08 パナソニック株式会社 Screen printing device
US20070164079A1 (en) * 2004-02-24 2007-07-19 Matsushita Electric Industrial Co., Ltd. Electronic component mounting method, and circuit substrate and circuit substrate unit used in the method
JP4536430B2 (en) * 2004-06-10 2010-09-01 イビデン株式会社 Flex rigid wiring board
FR2875995B1 (en) * 2004-09-24 2014-10-24 Oberthur Card Syst Sa METHOD FOR MOUNTING AN ELECTRONIC COMPONENT ON A SUPPORT, PREFERABLY MOU, AND ELECTRONIC ENTITY THUS OBTAINED, SUCH AS A PASSPORT
JP2006206833A (en) * 2005-01-31 2006-08-10 Toshiba Matsushita Display Technology Co Ltd Anisotropic conductive adhesive, connection structure using the same and connection method
JP4558539B2 (en) * 2005-03-09 2010-10-06 日立協和エンジニアリング株式会社 Electronic circuit board, electronic circuit, method for manufacturing electronic circuit board, and method for manufacturing electronic circuit
JP4733441B2 (en) * 2005-06-27 2011-07-27 アスリートＦａ株式会社 Electronic component joining equipment
CN100414404C (en) * 2005-09-06 2008-08-27 群康科技(深圳)有限公司 Circuit element connection structure and liquid crystal display panel
US20070054512A1 (en) * 2005-09-08 2007-03-08 International Business Machines Corporation Topography compensating land grid array interposer
JP5029597B2 (en) * 2006-02-13 2012-09-19 パナソニック株式会社 Card type recording medium and method for manufacturing card type recording medium
JP4509043B2 (en) * 2006-02-14 2010-07-21 株式会社新川 Stud bump formation method
JP4844168B2 (en) 2006-02-28 2011-12-28 パナソニック株式会社 Component joining method and component stacking method
DE102006036728B4 (en) * 2006-08-05 2017-01-19 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Method for the electrical contacting of microelectronic components on a printed circuit board
KR101292634B1 (en) 2006-09-11 2013-08-16 파나소닉 주식회사 Electronic component placing apparatus and electronic component mounting method
JP2008192984A (en) * 2007-02-07 2008-08-21 Elpida Memory Inc Semiconductor device and method of manufacturing the same
DE102007010731A1 (en) * 2007-02-26 2008-08-28 Würth Elektronik GmbH & Co. KG Method for arranging electronic chip in circuit board, involves forming of cavity in circuit board and base of cavity is structured for forming connection point
US7851342B2 (en) * 2007-03-30 2010-12-14 Intel Corporation In-situ formation of conductive filling material in through-silicon via
US20090014852A1 (en) * 2007-07-11 2009-01-15 Hsin-Hui Lee Flip-Chip Packaging with Stud Bumps
US8390115B2 (en) * 2008-04-03 2013-03-05 Sharp Kabushiki Kaisha Wiring board and semiconductor device using the wiring board
CN102027584B (en) * 2008-05-16 2013-03-27 住友电木株式会社 Semiconductor component fabrication method and semiconductor component
EP2413676A4 (en) * 2009-03-26 2013-03-27 Sharp Kk Chip component mounting structure, chip component mounting method and liquid crystal display device
FR2943849B1 (en) * 2009-03-31 2011-08-26 St Microelectronics Grenoble 2 METHOD FOR PRODUCING SEMICONDUCTOR HOUSINGS AND SEMICONDUCTOR HOUSING
US8371497B2 (en) * 2009-06-11 2013-02-12 Qualcomm Incorporated Method for manufacturing tight pitch, flip chip integrated circuit packages
KR101208028B1 (en) 2009-06-22 2012-12-04 한국전자통신연구원 Method of fabricating a semiconductor package and the semiconductor package
JP5533199B2 (en) * 2010-04-28 2014-06-25 ソニー株式会社 Device board mounting method and board mounting structure thereof
JP5719997B2 (en) * 2011-09-16 2015-05-20 パナソニックＩｐマネジメント株式会社 Electronic component mounting method and mounting system
US9105552B2 (en) * 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
JP5965185B2 (en) * 2012-03-30 2016-08-03 デクセリアルズ株式会社 Circuit connection material and method of manufacturing semiconductor device using the same
US8932909B2 (en) 2012-11-14 2015-01-13 International Business Machines Corporation Thermocompression for semiconductor chip assembly
JP5714631B2 (en) * 2013-03-26 2015-05-07 富士フイルム株式会社 Anisotropic conductive sheet and conductive connection method
WO2015004830A1 (en) 2013-07-08 2015-01-15 ソニー株式会社 Method for determining curing conditions, method for producing circuit device, and circuit device
CN104869754B (en) * 2014-02-25 2018-06-26 财团法人工业技术研究院 Flexible substrate embedded with conducting wire and manufacturing method thereof
KR102181010B1 (en) * 2014-07-20 2020-11-20 엑스-셀레프린트 리미티드 Apparatus and methods for micro-transfer printing
JP2016058026A (en) * 2014-09-12 2016-04-21 大日本印刷株式会社 Non-contact and contact common module, and non-contact and contact common ic card
EP3660989A1 (en) * 2014-12-26 2020-06-03 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
CN105895539B (en) * 2016-06-08 2018-08-10 华进半导体封装先导技术研发中心有限公司 Flip-chip encapsulates intermediate structure and flip-chip packaged structure and flip-chip packaged method
KR102656068B1 (en) * 2016-10-28 2024-04-12 삼성디스플레이 주식회사 Press apparatus and pressing method thereof
US10923365B2 (en) * 2018-10-28 2021-02-16 Richwave Technology Corp. Connection structure and method for forming the same
CN111009475B (en) * 2019-11-22 2021-08-27 青岛歌尔智能传感器有限公司 Packaging structure and packaging method of optical module
CN112242385B (en) * 2020-10-28 2022-08-23 长春希龙显示技术有限公司 Mirco-LED passive driving display unit based on glass substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02155257A (en) * 1988-12-07 1990-06-14 Matsushita Electric Ind Co Ltd Mounting device for semiconductor

Family Cites Families (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3777220A (en) * 1972-06-30 1973-12-04 Ibm Circuit panel and method of construction
US3811186A (en) * 1972-12-11 1974-05-21 Ibm Method of aligning and attaching circuit devices on a substrate
US3909680A (en) * 1973-02-16 1975-09-30 Matsushita Electric Ind Co Ltd Printed circuit board with silver migration prevention
US3936575A (en) * 1973-02-21 1976-02-03 Sumitomo Bakelite Company, Limited Flexible metal-clad laminates and method for manufacturing the same
US4731282A (en) * 1983-10-14 1988-03-15 Hitachi Chemical Co., Ltd. Anisotropic-electroconductive adhesive film
JPS60262430A (en) 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
IT1177870B (en) * 1984-07-04 1987-08-26 Texas Instr Semiconduttori Ita Assembling electronic components upon PCB
JPS6143438A (en) * 1984-08-08 1986-03-03 Hitachi Ltd semiconductor equipment
JPS626652A (en) 1985-07-01 1987-01-13 Nippon Shiyotsuken Kk Production of liquid seasoning
JPS62136865A (en) 1985-12-11 1987-06-19 Hitachi Ltd Module mounting structure
US4740657A (en) * 1986-02-14 1988-04-26 Hitachi, Chemical Company, Ltd Anisotropic-electroconductive adhesive composition, method for connecting circuits using the same, and connected circuit structure thus obtained
JPS62188184A (en) 1986-02-14 1987-08-17 日立化成工業株式会社 Adhesive compound with anisotropic conductivity and adhesivefilm for circuit connection and connection of circuits usingthose materials
JPH0815167B2 (en) * 1986-03-26 1996-02-14 株式会社日立製作所 Semiconductor device
US4811081A (en) * 1987-03-23 1989-03-07 Motorola, Inc. Semiconductor die bonding with conductive adhesive
US5014111A (en) * 1987-12-08 1991-05-07 Matsushita Electric Industrial Co., Ltd. Electrical contact bump and a package provided with the same
JPH063820B2 (en) * 1988-07-25 1994-01-12 松下電器産業株式会社 Semiconductor device mounting method
JP2596960B2 (en) * 1988-03-07 1997-04-02 シャープ株式会社 Connection structure
JPH0818430B2 (en) * 1988-07-08 1996-02-28 日本ボールドウィン株式会社 Cylinder cleaning device for printing machine
JPH0254932A (en) * 1988-08-20 1990-02-23 Fujitsu Ltd How to form solder bumps
US5001542A (en) * 1988-12-05 1991-03-19 Hitachi Chemical Company Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips
JP2833111B2 (en) * 1989-03-09 1998-12-09 日立化成工業株式会社 Circuit connection method and adhesive film used therefor
US5071787A (en) * 1989-03-14 1991-12-10 Kabushiki Kaisha Toshiba Semiconductor device utilizing a face-down bonding and a method for manufacturing the same
US5040069A (en) * 1989-06-16 1991-08-13 Fuji Photo Optical Co., Ltd. Electronic endoscope with a mask bump bonded to an image pick-up device
US4967950A (en) * 1989-10-31 1990-11-06 International Business Machines Corporation Soldering method
US5086558A (en) * 1990-09-13 1992-02-11 International Business Machines Corporation Direct attachment of semiconductor chips to a substrate with a substrate with a thermoplastic interposer
US5128746A (en) 1990-09-27 1992-07-07 Motorola, Inc. Adhesive and encapsulant material with fluxing properties
JPH04169001A (en) 1990-11-01 1992-06-17 Matsushita Electric Ind Co Ltd Method of mounting conductive paste and semiconductor device
JP2940269B2 (en) * 1990-12-26 1999-08-25 日本電気株式会社 Connecting method of integrated circuit element
JPH04348540A (en) * 1991-05-27 1992-12-03 Sony Corp Flip chip bonder
JP2890890B2 (en) 1991-05-30 1999-05-17 日立化成工業株式会社 Manufacturing method of connecting member
JP3352705B2 (en) * 1991-06-07 2002-12-03 日東電工株式会社 Mounting structure using anisotropic conductive adhesive film
JP3131246B2 (en) 1991-07-24 2001-01-31 富士通株式会社 Mounting method of bare chip having bump
JP2762813B2 (en) 1992-01-30 1998-06-04 日立化成工業株式会社 Connection method of semiconductor chip
JPH0637144A (en) 1992-07-17 1994-02-10 Matsushita Electric Ind Co Ltd Electrode connection method
JPH0666355A (en) 1992-08-20 1994-03-08 Mitsubishi Motors Corp Coupling structure between engine and torque converter of automobile
US5859470A (en) * 1992-11-12 1999-01-12 International Business Machines Corporation Interconnection of a carrier substrate and a semiconductor device
US5303862A (en) * 1992-12-31 1994-04-19 International Business Machines Corporation Single step electrical/mechanical connection process for connecting I/O pins and creating multilayer structures
JPH06240217A (en) 1993-02-16 1994-08-30 Shin Etsu Polymer Co Ltd Production of anisotropically electroconductive adhesive
JP2795788B2 (en) * 1993-02-18 1998-09-10 シャープ株式会社 Semiconductor chip mounting method
JPH06299373A (en) * 1993-04-12 1994-10-25 Seiko Instr Inc Method for working member
US5485949A (en) * 1993-04-30 1996-01-23 Matsushita Electric Industrial Co., Ltd. Capillary for a wire bonding apparatus and a method for forming an electric connection bump using the capillary
US5386624A (en) * 1993-07-06 1995-02-07 Motorola, Inc. Method for underencapsulating components on circuit supporting substrates
DE69426347T2 (en) * 1993-09-29 2001-05-17 Matsushita Electric Industrial Co., Ltd. Method of mounting a semiconductor device on a circuit board and a circuit board with a semiconductor device thereon
US5508561A (en) 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US5435482A (en) * 1994-02-04 1995-07-25 Lsi Logic Corporation Integrated circuit having a coplanar solder ball contact array
JPH07318962A (en) * 1994-03-30 1995-12-08 Seiko Instr Inc Electrode substrate of electric device, formation of electrode and packaging method
JP3255796B2 (en) 1994-05-26 2002-02-12 松下電器産業株式会社 Semiconductor device mounting method
US5578874A (en) * 1994-06-14 1996-11-26 Hughes Aircraft Company Hermetically self-sealing flip chip
JPH0837208A (en) 1994-07-25 1996-02-06 Toshiba Corp Method of mounting semiconductor element and its device
JP2925946B2 (en) 1994-09-19 1999-07-28 沖電気工業株式会社 Method for mounting semiconductor device using anisotropic conductive film and apparatus therefor
DE19535282A1 (en) * 1994-09-23 1996-03-28 Fraunhofer Ges Forschung Connecting electronic component to substrate with several contact faces
JP2616471B2 (en) * 1994-12-02 1997-06-04 日本電気株式会社 Semiconductor element mounting method
JP3480754B2 (en) * 1994-12-28 2003-12-22 住友ベークライト株式会社 Method for producing anisotropic conductive film
JP3209875B2 (en) * 1995-03-23 2001-09-17 株式会社日立製作所 Substrate manufacturing method and substrate
JP2770821B2 (en) 1995-07-27 1998-07-02 日本電気株式会社 Semiconductor device mounting method and mounting structure
US5874780A (en) * 1995-07-27 1999-02-23 Nec Corporation Method of mounting a semiconductor device to a substrate and a mounted structure
US5749997A (en) * 1995-12-27 1998-05-12 Industrial Technology Research Institute Composite bump tape automated bonding method and bonded structure
US5704116A (en) * 1996-05-03 1998-01-06 Motorola, Inc. Method of holding a component using an anhydride fluxing agent
US6022761A (en) * 1996-05-28 2000-02-08 Motorola, Inc. Method for coupling substrates and structure
JP2830852B2 (en) * 1996-08-08 1998-12-02 松下電器産業株式会社 Electronic component mounting method
US5796590A (en) * 1996-11-05 1998-08-18 Micron Electronics, Inc. Assembly aid for mounting packaged integrated circuit devices to printed circuit boards
US5848466A (en) * 1996-11-19 1998-12-15 Motorola, Inc. Method for forming a microelectronic assembly
US6082610A (en) * 1997-06-23 2000-07-04 Ford Motor Company Method of forming interconnections on electronic modules
JP2997231B2 (en) * 1997-09-12 2000-01-11 富士通株式会社 Method for manufacturing multi-semiconductor bare chip mounting module
US6326241B1 (en) * 1997-12-29 2001-12-04 Visteon Global Technologies, Inc. Solderless flip-chip assembly and method and material for same
US5953814A (en) * 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02155257A (en) * 1988-12-07 1990-06-14 Matsushita Electric Ind Co Ltd Mounting device for semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101022921B1 (en) 2008-11-25 2011-03-16 삼성전기주식회사 Manufacturing Method of Printed Circuit Board with Electronic Device

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EP0954208A4 (en) 2002-09-11
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JP2001024034A (en) 2001-01-26
EP0954208A1 (en) 1999-11-03
JP3927759B2 (en) 2007-06-13
JP3150347B2 (en) 2001-03-26
EP1448034A1 (en) 2004-08-18
EP1445995B1 (en) 2007-02-14
DE69737375T2 (en) 2007-11-29
JP3880775B2 (en) 2007-02-14
DE69737375D1 (en) 2007-03-29
US6981317B1 (en) 2006-01-03
WO1998030073A1 (en) 1998-07-09
JP2001007159A (en) 2001-01-12
KR20000062375A (en) 2000-10-25

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