KR100352482B1 - 주파수특성이개선되는피엘엘집적회로 - Google Patents
주파수특성이개선되는피엘엘집적회로 Download PDFInfo
- Publication number
- KR100352482B1 KR100352482B1 KR1019970026812A KR19970026812A KR100352482B1 KR 100352482 B1 KR100352482 B1 KR 100352482B1 KR 1019970026812 A KR1019970026812 A KR 1019970026812A KR 19970026812 A KR19970026812 A KR 19970026812A KR 100352482 B1 KR100352482 B1 KR 100352482B1
- Authority
- KR
- South Korea
- Prior art keywords
- divider
- output
- signal
- variable
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims (2)
- 일정한 발진신호가 생성되는 발진소자부와, 상기 발진소자부의 신호가 비교하기 위한 기준신호로 분주되는 기준분주기와, 출력에서부터 궤환된 신호가 분주되는 프리스케일러(Prescaler)와, 상기 프리스케일러의 출력이 설정된 값으로 분주되는 가변분주기와, 상기 기준분주기의 출력이 비교기의 기준이 되는 입력으로 사용되고, 가변분주기의 출력이 다른 입력으로 되는 비교기와, 상기 비교기 출력이 적분되는 적분기 및 상기 적분기의 출력이 입력되어 제어되는 발진회로부로 구성되는 PLL 집적회로에 있어서:상기 기준분주기를 제어분부기로 대치하되,
- 제 1 항에 있어서,상기 제어분주기는 2 배 또는 4 배로 제어되는 것을 특징으로 하는 주파수 특성이 개선되는 피엘엘 집적회로.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970026812A KR100352482B1 (ko) | 1997-06-24 | 1997-06-24 | 주파수특성이개선되는피엘엘집적회로 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970026812A KR100352482B1 (ko) | 1997-06-24 | 1997-06-24 | 주파수특성이개선되는피엘엘집적회로 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR19990003023A KR19990003023A (ko) | 1999-01-15 |
KR100352482B1 true KR100352482B1 (ko) | 2002-12-28 |
Family
ID=37489208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970026812A Expired - Fee Related KR100352482B1 (ko) | 1997-06-24 | 1997-06-24 | 주파수특성이개선되는피엘엘집적회로 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100352482B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4771572B2 (ja) * | 2000-04-10 | 2011-09-14 | 富士通セミコンダクター株式会社 | Pll半導体装置並びにその試験の方法及び装置 |
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1997
- 1997-06-24 KR KR1019970026812A patent/KR100352482B1/ko not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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KR19990003023A (ko) | 1999-01-15 |
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Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19970624 |
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