KR100350762B1 - Formation method of micropattern - Google Patents
Formation method of micropattern Download PDFInfo
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- KR100350762B1 KR100350762B1 KR1019950050498A KR19950050498A KR100350762B1 KR 100350762 B1 KR100350762 B1 KR 100350762B1 KR 1019950050498 A KR1019950050498 A KR 1019950050498A KR 19950050498 A KR19950050498 A KR 19950050498A KR 100350762 B1 KR100350762 B1 KR 100350762B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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Abstract
Description
본 발명은 반도체소자의 미세 패턴 형성 방법에 관한것으로, 특히 노광파장(Exposure Wavelength)이하의 크기를 갖는 콘택홀(Contact Hole)을 형성할수 있는 미세 패턴 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly, to a method of forming a fine pattern capable of forming a contact hole having a size of less than or equal to an exposure wavelength.
보통 해상도(Resolution)는 Rayleigh가 제안한 식(equation)에 따라 정의되어진다.Resolution is usually defined according to Rayleigh's proposed equation.
그 식은로서, 여기서 R은 해상도이고, K는 공정상수(Process Constant), λ는 노광파장, 그리고 NA는 렌즈(Lens)의 개구수(Numerical Aperture)를 나타낸다. 콘택홀 패턴의 해상도(R)를 노광파장(λ) 이하의 크기로 하려면 NA가 K보다 커야 하는데 양산공정에서 K값은 0.8정도이므로 NA값은 0.8보다 크게 만들지 않으면 안된다.That way Where R is the resolution, K is the process constant, λ is the exposure wavelength, and NA is the numerical aperture of the lens. In order for the resolution R of the contact hole pattern to be less than or equal to the exposure wavelength λ, NA must be larger than K. Since the K value is about 0.8 in the mass production process, the NA value must be made larger than 0.8.
그러나, 렌즈를 가공할때 노광 필드 크기(Exposure Field Size)를 일정하게 유지하면서 제조할 수 있는 렌즈의 최대 NA는 0.7정도이므로 Rayleigh식에서 해상도를 노광파장이하의 크기로 맞추는 것은 불가능하다. 0.365㎛파장기 I-line과 0.248㎛파장의 DUV(Deep Ultraviolet)노광에서 해상도는 각각이다.However, since the maximum NA of a lens that can be manufactured while maintaining a constant exposure field size when processing the lens is about 0.7, it is impossible to adjust the resolution to the size of the exposure wavelength or less in the Rayleigh equation. The resolution of 0.365㎛ wavelength I-line and 0.248㎛ wavelength DUV (Deep Ultraviolet) exposure are respectively to be.
따라서, 콘택홀크기 0.3×0.3㎛2를 갖는 64M-256M DRAM에서는 DUV노광에 의해 패턴형성이 가능하지만, 0.2×0.2㎛2정도의 크기를 갖는 1G-4G DRAM에서는 DUV노광으로도 콘택홀 형성이 어렵게 된다.Therefore, in the 64M-256M DRAM having a contact hole size of 0.3 × 0.3 μm 2 , pattern formation is possible by DUV exposure. However, in 1G-4G DRAM having a size of 0.2 × 0.2 μm 2 , contact hole formation is not possible even in DUV exposure. Becomes difficult.
제1도는 종래의 기술에 의해 0.2×0.2㎛2크기의 콘택홀을 DUV노광으로 패턴형성하는 공정순서를 도시한 것이다.1 shows a process sequence for patterning a contact hole having a size of 0.2 × 0.2 μm 2 by DUV exposure according to a conventional technique.
제1도의 가는 웨이퍼(5)상에 절연막(4)을 증착하고 그상부에 감광막(3)을 도포하고 마스크(2)를 이용하여 광(1)을 노광하는 단계를 도시한 단면도이다.1 is a cross-sectional view showing the steps of depositing the insulating film 4 on the thin wafer 5, applying the photosensitive film 3 thereon, and exposing the light 1 using the mask 2.
제1도의 나는 노광된 지역의 감광막(3)을 TMAH(Tetramethylammonium Hydroxide)로 현상하여 감광막패턴(3')을 형성한 단면도이다.In FIG. 1, sectional drawing which developed the photosensitive film pattern 3 'by developing the photosensitive film 3 of an exposed area | region by TMAH (Tetramethylammonium Hydroxide) is shown.
제1도의 다는 상기 감광막패턴(3')을 마스크로 이용하여 하부의 절연막(4)을 식각하여 절연막패턴(4')을 형성한다음, 상기 감광막패턴(3')을 제거한 단면도이다.FIG. 1 is a cross-sectional view of the lower insulating film 4 being etched using the photosensitive film pattern 3 'as a mask to form the insulating film pattern 4' and then removing the photosensitive film pattern 3 '.
제1도의 나에서 0.248㎛파장을 갖는 DUV노광에 의해 0.2×0.2㎛2의 콘택홀 패턴을 형성하는 것은 거의 불가능함을 알 수 있다. 감광막의 상부에서는 콘택홀이 열리지만 감광막의 저부에서는 콘택홀의 패턴이 형성되지 않아서 이 감광막패턴을 마스크로 이용하고 식각공정으로 절연막을 식각 하더라도 결국 절연막(4)에는 콘택홀의 프로파일이 정확하게 형성되지 않게 된다.It can be seen from the diagram of FIG. 1 that it is almost impossible to form a contact hole pattern of 0.2 × 0.2 μm 2 by DUV exposure having a wavelength of 0.248 μm. The contact hole is opened at the top of the photoresist film, but the contact hole pattern is not formed at the bottom of the photoresist film. Even though the photoresist pattern is used as a mask and the insulating film is etched by the etching process, the contact hole profile is not formed accurately in the insulating film 4. .
따라서, 본 발명은 상기한 문제점을 해결하기 위하여 웨이퍼상에 제1 감광막 패턴을 형성하고, 제2감광막 패턴을 제1감광막 패턴의 일정부분과 겹치도록 형성한다음, 상기 제1, 제2 감광막패턴을 마스크로 이용하여 하부 절연막을 식각하여 콘택홀을 형성하는 미세 패턴 형성 방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problem, the present invention forms a first photoresist pattern on a wafer, and forms a second photoresist pattern so as to overlap a portion of the first photoresist pattern, and then the first and second photoresist pattern It is an object of the present invention to provide a fine pattern forming method for forming a contact hole by etching a lower insulating film by using a mask as a mask.
즉, 콘택홀이 구비된 제1감광막패턴을 형성한다음, 마스크(Mask)는 고정시킨채 웨이퍼만을 이동시켜 제2감광막 패턴이 제1감광막 패턴과 일정부분 겹쳐서 형성되도록 한다. 예를들어, 0.3×0.3㎛2크기의 콘택홀을 갖는 제1콘택홀과 제2콘택홀을 형성함에 있어서 두 콘택홀이 완전히 겹치면 최종콘택홀 크기는 0.3×0.3㎛2이지만, 두 콘택홀이 0.2㎛만큼 겹치면 0.2×0.2㎛2콘택홀이 형성되고, 0.1㎛겹치면 0.1×0.1㎛2크기의 패턴이 형성된다. 즉, 두 콘택홀이 겹친만큼이 크기를 갖는 콘택홀이 형성된다.That is, after forming the first photoresist pattern having the contact hole, only the wafer is moved while the mask is fixed so that the second photoresist pattern overlaps the first photoresist pattern. For example, but 0.3 × 0.3㎛ the two contact holes in two as to form a first contact hole and the second contact hole with a size of the contact hole completely overlapping end contact hole size is 0.3 × 0.3㎛ 2, the two contact holes 0.2 × 0.2 μm 2 contact holes are formed when overlapped by 0.2 μm, and 0.1 × 0.1 μm 2 size patterns are formed when overlapped by 0.1 μm. That is, a contact hole having this size is formed as the two contact holes overlap.
상기한 목적을 달성하기 위한 본 발명은 반도체소자의 미세 콘택홀형성 방법에 있어서,In the present invention for achieving the above object in the method for forming a fine contact hole of a semiconductor device,
웨이퍼 상부에 절연막과 절연막에 대한 하드 마스크용 필름을 증착하는 단계와,Depositing an insulating film and a film for a hard mask on the insulating film on the wafer;
상기 하드 마스크용 필름 상부에 제1 감광막을 도포하고, 콘택홀 마스크를 이용한 노광 및 현상공정으로 제1 감광막 패턴을 형성하는 단계와,Coating a first photoresist film on the hard mask film, and forming a first photoresist pattern by an exposure and development process using a contact hole mask;
상기 제1 감광막 패턴을 경화 시키는 단계와,Curing the first photoresist pattern;
상기 제1 감광막 패턴 상부에 제2 감광막을 도포하고 웨이퍼를 일정위치만큼 이동시킨다음, 상기 콘택홀 마스크를 이용한 노광 및 현상 공정으로 상기 제1 감광막 패턴과 일정 부분 오버랩되는 제2 감광막 패턴을 형성하여 콘택홀의 크기를 감소시키는 단계와,After applying a second photoresist film on the first photoresist pattern pattern and moving the wafer by a predetermined position, a second photoresist pattern is formed to overlap a portion of the first photoresist pattern by an exposure and development process using the contact hole mask. Reducing the size of the contact hole,
상기 제1, 2 감광막 패턴을 플라즈마 마스크로 하여 하드 마스크용 필름을 식각하고, 상기 제1, 2 감광막 패턴과 하드 마스크용 필름 패턴을 마스크로 하여노출된 절연막을 식각하여 미세 콘택홀을 형성하고, 상기 제1, 제2 감광막 패턴을 제거하는 단계를 포함하는 것을 특징으로 한다.Etching the hard mask film using the first and second photoresist patterns as a plasma mask, etching the exposed insulating film using the first and second photoresist patterns and the film pattern for the hard mask as a mask to form a fine contact hole, And removing the first and second photoresist patterns.
상기한 목적을 달성하기 위한 또다른 본 발명의 반도체소자의 미세콘택홀 형성 방법에 있어서,In another method of forming a micro contact hole of a semiconductor device of the present invention for achieving the above object,
웨이퍼 상부에 절연막을 증착하고 그 상부에 제1 감광막을 도포하고, 콘택홀 마스크를 이용한 노광 및 현상공정으로 제1 감광막 패턴을 형성하는 단계와,Depositing an insulating film on the wafer and applying a first photosensitive film on the wafer, and forming a first photosensitive film pattern by an exposure and development process using a contact hole mask;
상기 제1 감광막 패턴을 경화 시키는 단계와,Curing the first photoresist pattern;
상기 제1 감광막 패턴 상부에 제2 감광막을 도포하고 웨이퍼를 일정위치만큼 이동시킨다음, 상기 콘택홀 마스크를 이용한 노광 및 현상 공정으로 상기 제1 감광막 패턴과 일정 부분 오버랩되는 제2 감광막 패턴을 형성하여 콘택홀의 크기를 감소시키는 단계와,After applying a second photoresist film on the first photoresist pattern pattern and moving the wafer by a predetermined position, a second photoresist pattern is formed to overlap a portion of the first photoresist pattern by an exposure and development process using the contact hole mask. Reducing the size of the contact hole,
상기 제1, 2 감광막 패턴을 플라즈마 마스크로 하여 노출된 절연막을 식각하여 미세 콘택홀을 형성하고, 상기 제1, 제2 감광막 패턴을 제거하는 단계를 포함하는 것을 특징으로 한다.And etching the exposed insulating film using the first and second photoresist pattern as a plasma mask to form a fine contact hole, and removing the first and second photoresist pattern.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 의해 제1 콘택홀과 제2 콘택홀을 웨이퍼 상에 형성한 단면도이다.2 is a cross-sectional view of a first contact hole and a second contact hole formed on a wafer according to the present invention.
제2도의 가는 웨이퍼(11) 상에 절연막(12)을 형성하고, 그상부에 감광막(13)을 도포하고, 제1 콘택홀 마스크(14)를 이용한 노광 및 현상공정으로 감광막(13)패턴을 형성한다음, 이것을 마스크로 이용한 식각공정으로 절연막(12)에 제1 콘택홀(16)을 형성한 단면도이다. 여기서, 제1 콘택홀(16)의 크기는 x 가 된다.The insulating film 12 is formed on the thin wafer 11 of FIG. 2, the photoresist film 13 is apply | coated on it, and the photosensitive film 13 pattern is formed by the exposure and image development process using the 1st contact hole mask 14. FIG. After the formation, the first contact hole 16 is formed in the insulating film 12 by an etching process using this as a mask. Here, the size of the first contact hole 16 is x.
제2도의 나는 상기 감광막(13)의 패턴을 제거하고, 전체적으로 감광막(18)을 도포하고, 제2콘택홀 마스크(15)를 이용한 노광 및 현상공정으로 감광막(18) 패턴을 형성한다음, 이것을 마스크로 이용한 식각공정으로 노출된 절연막(12)에 제2 콘택홀(17)을 형성한 단면도로서, 상기 제1 콘택홀(16)과 제2 콘택홀(17)이 중복되는 지역의 크기는 x' 로 작게 됨을 도시한다.In FIG. 2, the pattern of the photoresist film 13 is removed, the photoresist film 18 is entirely applied, and the photoresist film 18 pattern is formed by an exposure and development process using the second contact hole mask 15. A cross-sectional view of forming a second contact hole 17 in the insulating film 12 exposed by the etching process using a mask, the size of the region where the first contact hole 16 and the second contact hole 17 overlap with each other x 'Becomes small.
제3도는 본 발명의 실시예에 의해 미세 크기의 콘택홀을 형성하는 단계를 도시한 단면도이다.3 is a cross-sectional view showing a step of forming a contact hole of a fine size according to an embodiment of the present invention.
제3도의 가는 웨이퍼(26)위에 TEOS나 BPSG, MTO등의 절연막(25)을 1000-10000Å두께로 증착(Deposition)하고, 이어서 절연막(25)에 대한 하드마스크(21)로써의 폴리실리콘층 또는 질화막을 500-2000Å두께로 증착한 다음, 그 위에 제1감광막(23)을 0.1-0.5㎛두께로 도포하고 마스크(22)를 사용하여 광(21)을 노광시키는 단면도이다.An insulating film 25 such as TEOS, BPSG, MTO, etc. is deposited on the thin wafer 26 of FIG. 3 to a thickness of 1000-10000 kPa, and then a polysilicon layer as a hard mask 21 for the insulating film 25 or After the nitride film is deposited to a thickness of 500-2000 kPa, the first photosensitive film 23 is applied thereon at a thickness of 0.1-0.5 µm, and the light 21 is exposed using the mask 22.
제3도의 나는 노광된 지역의 제1 감광막(23)을 TMAH(Tetramethyl Ammonium Hydroxide)로 현상시키고 순수 (Deionized Water)로 세척한 다음 웨이퍼를 스핀 드라이 시킴으로써 노광되지 않은 지역에 제1 감광막패턴(23')이 형성된 상태를 도시한 단면도이다.In FIG. 3, the first photoresist layer 23 in the exposed area is developed with TMAH (Tetramethyl Ammonium Hydroxide), washed with deionized water, and spin-dried the wafer to expose the first photoresist pattern 23 'to the unexposed area. It is sectional drawing which shows the state in which () was formed.
제3도의 다는 상기 제1 감광막패턴(23')의 전면에 광대역 (Broad Band) 200-400nm의 원자외선(Deepultraviolet)을 조사하는 동시에 100-200℃에서 경화를 실시함으로써 제1 감광막 패턴(23')을 경화(Hardening)된 상태를 도시된 단면도이다.3 shows the first photoresist pattern 23 'by irradiating a broad band 200-400 nm deep pultraviolet on the entire surface of the first photoresist pattern 23' and curing at 100-200 ° C. ) Is a cross-sectional view showing a hardened state.
제3도의 라는 상기 제1 감광막패턴(23') 상부에 다시 제2 감광막('28)을 도포한 다음 마스크를 고정시킨채 웨이퍼를 좌측으로 이동시킨 상태를 도시한 단면도이다.3 is a cross-sectional view illustrating a state in which the second photoresist film '28 is applied on the first photoresist pattern 23 'again, and then the wafer is moved to the left with the mask fixed.
제3도의 마는 웨이퍼가 이동된 상태에서 광을 조사시키고 TMAH로 현상하여 제2 감광막 패턴(28')을 형성한 상태를 도시한 단면도이다.FIG. 3 is a cross-sectional view showing a state in which the second photosensitive film pattern 28 'is formed by irradiating light with the wafer moved and developing with TMAH.
제3도의 바는 제1 감광막 패턴(23')과 제2 감광막 패턴(28')을 Plasma에 대한 마스크로 사용하여 하드 마스크를 식각하여 콘택홀 패턴을 형성한 것을 도시한 단면도이다.3 is a cross-sectional view showing a contact hole pattern formed by etching a hard mask using the first photoresist pattern 23 'and the second photoresist pattern 28' as a mask for the plasma.
제3도의 사는 상기 제1, 2 감광막 패턴(23', 28')과 상기 하드 마스크(24)를 플라즈마 마스크로 사용하여 하층의 절연막(25)을 식각하여 웨이퍼(26)가 노출된 미세 콘택홀(30)을 형성하고, 상기 제1, 2 감광막 패턴(23', 28')을 제거한 단면도이다.3 shows a micro contact hole in which a lower layer insulating layer 25 is etched using the first and second photoresist layer patterns 23 ′ and 28 ′ and the hard mask 24 as a plasma mask to expose the wafer 26. 30 is a cross-sectional view from which the first and second photosensitive film patterns 23 'and 28' are removed.
상기 절연막은 TEOS, BPSG 또는 MTO 막으로 형성하고, 상기 절연막에 대한 하드 마스크용 필름으로 폴리실리콘층 또는 질화막으로 형성하고, 상기 감광막을 노광할때 G-line, DUV, E-beam 또는 X-ray 등의 파장을 이용한다. 그리고, 상기 제1 감광막 패턴을 경화시킬때 200-400nm의 광대역 파장을 갖는 자외선을 이용하고 자외선 노광과 동시에 100-200℃에서 경화 시킨다. 또한, 상기 웨이퍼를 이동시킬때 마스크는 고정시키고 스테퍼내의 스테이지 상의 웨이퍼에 대해 간단하게 Offset을 주어 상하 좌우 어느 방향으로도 이동시킬 수 있도록 할수 있다.The insulating film is formed of a TEOS, BPSG, or MTO film, a hard mask film for the insulating film, a polysilicon layer or a nitride film, and G-line, DUV, E-beam, or X-ray when the photosensitive film is exposed. Etc. wavelength is used. When the first photoresist pattern is cured, ultraviolet rays having a broadband wavelength of 200 to 400 nm are used, and at the same time as the ultraviolet exposure, curing is performed at 100 to 200 ° C. Further, when the wafer is moved, the mask can be fixed and simply offset to the wafer on the stage in the stepper so that the wafer can be moved in any of up, down, left, and right directions.
상기 하드 마스크용 필름을 식각할때 필름이 폴리실리콘층인 경우 Cl2+O2, Cl2+N2, Cl2+HBr+He 등의 Cl계 GaS를 사용하며, 하드 마스크용 필름이 질화막인 경우 CHF3, CF4+O2, CF4+CHF3+O2+Ar등의 F계 Gas를 사용하며, 상기 절연막을 식각하여 콘택홀을 형성할때 하드마스크가 폴리실리콘층인 경우에는 C2F6, C3F8+CO Gas를 사용하고, 질화막인 경우에는 C3F8+Ar, C4F8+Ar+CH3F Gas를 사용한다.When etching the hard mask film, if the film is a polysilicon layer, Cl-based GaS such as Cl 2 + O 2 , Cl 2 + N 2 , Cl 2 + HBr + He, and the like, the hard mask film is a nitride film. In case of F-type gas such as CHF 3 , CF 4 + O 2 , CF 4 + CHF 3 + O 2 + Ar, etc., if the hard mask is a polysilicon layer when etching the insulating film to form a contact hole 2 F 6 , C 3 F 8 + CO Gas is used, and in the case of a nitride film, C 3 F 8 + Ar, C 4 F 8 + Ar + CH 3 F Gas.
그리고, 상기 감광막 패턴을 제거할때 O2plasma 또는 Thinner를 사용한다.When removing the photoresist pattern, O 2 plasma or thinner is used.
상기 하드 마스크용 필름을 형성하는 대신에 제2 감광막 두께를 0.5-1.0㎛으로 도포할수 있다.Instead of forming the film for the hard mask, the second photosensitive film thickness may be applied to 0.5-1.0 μm.
참고로, 상기에서 하드 마스크를 사용하는 이유는 감광막 포토레지스트만으로는 하층 절연막 에칭에 있어서 Plasma Mask로써 충분치 못하기 때문이다. 또한, 제1 감광막의 두께를 얇게 하는 이유는 제2 감광막을 도포할때 잘 도포되게 하기 위함이다.For reference, the reason why the hard mask is used in the above is that the photoresist photoresist alone is not sufficient as the plasma mask in etching the lower insulating film. In addition, the reason why the thickness of the first photoresist film is thin is to be well applied when the second photoresist film is applied.
노광파장이하의 콘택홀을 형성시키기 위해서는 보통 노광파장을 보다 작은 파장을 갖는 새로운 노광장비를 이용해야 하지만, 본 방법에서는 노광파장을 바꾸지 않고 노광파장이하의 콘택홀형성이 가능하므로 장비의 수명을 늘릴 수 있을뿐 아니라 새로운 장비에 대한 투자비용도 줄일 수 있다. 즉, I-line이나 DUV를 이용하여 E-beam이나 X-ray선으로나 가능한 0.1×0.1㎛2크기의 콘택홀도 형성가능하다.In order to form contact holes below the exposure wavelength, new exposure equipment having a smaller wavelength is usually used. However, in this method, contact holes below the exposure wavelength can be formed without changing the exposure wavelength. Not only can you reduce your investment in new equipment? In other words, I-line or DUV can be used to form a contact hole having a size of 0.1 × 0.1 μm 2 , which can be an E-beam or an X-ray.
제1도는 종래의 기술에 의해 콘택홀을 형성하는 단계를 도시한 단면도.1 is a cross-sectional view showing a step of forming a contact hole by a conventional technique.
제2도는 본 발명에 의해 콘택홀을 형성하는 단계를 도시한 단면도.2 is a cross-sectional view showing a step of forming a contact hole according to the present invention.
제3도는 본 발명의 구체적인 실시예에 의해 콘택홀을 형성하는 단계를 도시한 단면도.3 is a cross-sectional view showing a step of forming a contact hole according to a specific embodiment of the present invention.
※ 도면의 주요부분에 대한 부호의 설명※ Explanation of code for main part of drawing
14 : 제1 마스크 15 : 제2 마스크14: first mask 15: second mask
21 : 광 22 : 마스크21: light 22: mask
13, 23 : 제1 감광막 24 : 하드 마스크용 필름13, 23: 1st photosensitive film 24: film for hard masks
4,12,25 : 절연막 5,11,26 : 웨이퍼4,12,25 insulating film 5,11,26 wafer
27 : 광 18, 28 : 제2 감광막27 light 18, 28 second photosensitive film
30 : 콘택홀30: contact hole
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