KR100349350B1 - Method for isolating semiconductor devices - Google Patents

Abstract

[0001] The present invention relates to a device isolation method for a semiconductor device, and more particularly, to a semiconductor device isolation method in which a pad nitride film pattern defining a device active region in an STI (shallow trench isolation) process is formed into a concave- To a method of forming a field insulating film of a semiconductor device using chemical mechanical polishing in which a step of a field insulating film is planarized by chemical mechanical polishing to prevent excessive etching of edges of the active region of the device during chemical mechanical polishing to form a field insulating film having a uniform surface will be. A method of isolating a semiconductor device according to the present invention includes the steps of: forming a hard mask on a semiconductor substrate, covering a device active region and having an edge portion thicker than a center portion; A third step of forming a trench to define a device isolation region by removing the trench at a predetermined depth; and a third step of forming an insulating material layer on the substrate including the hard mask to a thickness enough to fill the trench, Performing a chemical mechanical polishing on the insulating material layer so as to expose a central portion of the hard mask, thereby leaving the insulating material layer only in the trench; and a fifth step of removing the hard mask.

Description

[0001] The present invention relates to a method for isolating semiconductor devices,

[0001] The present invention relates to a device isolation method for a semiconductor device, and more particularly, to a semiconductor device isolation method in which a pad nitride film pattern defining a device active region in an STI (shallow trench isolation) process is formed into a concave- To a method of forming a field insulating film of a semiconductor device using chemical mechanical polishing in which a step of a field insulating film is planarized by chemical mechanical polishing to prevent excessive etching of edges of the active region of the device during chemical mechanical polishing to form a field insulating film having a uniform surface will be.

BACKGROUND ART As the integration of semiconductor devices continues, the development of techniques for reducing a device isolation region occupying a considerable area of a semiconductor device is actively under way.

A shallow trench isolation (BOX) type shallow trench isolation technique is used to form a trench in a semiconductor substrate and to form a trench in a semiconductor substrate by a CVD (Chemical Vapor Deposition) And the like. Therefore, buzz beaks are not generated and there is no loss of the active region. Further, the oxide film is buried and etched back to obtain a flat surface.

In the STI method applied to a device isolation method of a semiconductor device, the step of the active region and the insulating material buried in the trench defining the device isolation region must be kept constant. CMP is used for this purpose, and a nitride film is used as a protective film to protect the substrate of the active region during the CMP.

However, when the element active region is relatively larger than the element isolation region, the level difference between the element isolation region and the element active region of the insulating material layer for forming a field insulating film becomes worsened and it is difficult to obtain a uniform planarization result in the planarization process using the chemical mechanical polishing Do.

In the STI process for defining the active region and the isolation region in the semiconductor device manufacturing process, chemical mechanical polishing is applied, so that a specific additional layer is formed in order to improve the poor flatness due to the surface step difference of the deposited insulating material layer, The total number of process steps is increased due to the addition of a photolithography process for patterning in the form of a mask.

Another technique is to repeatedly perform deposition and gap-filling of a gap-filling material for forming an element isolation film. However, this technique deepens the step between the element active region and the element isolation region, The overpolishing of the edge of the region and the increase of the process steps increase the manufacturing cost.

1A to 1D are process sectional views showing a device isolation method of a semiconductor device according to the prior art.

1A, a buffer oxide film 11 is formed on a semiconductor substrate 10 made of s-silicon by a thermal oxidation method and then a chemical vapor deposition (hereinafter referred to as CVD) Silicon nitride is deposited to form the pad nitride film 12. At this time, the buffer oxide film 11 is formed to relieve stress generated between the silicon nitride and the silicon of the substrate, and the pad nitride film 12 is formed to prevent the silicon substrate from being etched.

After the photoresist is applied on the pad nitride film 12, exposure and development are performed using an exposure mask that defines a trench forming region to be a device isolation region to expose the surface of the pad nitride film 12 in the device isolation region A photoresist pattern 13 is formed.

Referring to FIG. 1B, the pad nitride film and the buffer oxide film, which are not protected by the photoresist pattern 13, are sequentially removed by anisotropic etching such as dry etching so as to expose the semiconductor substrate 10, . At this time, the remaining pad nitride film 120 through the remaining buffer oxide film 110 is a protective film for protecting the substrate of the active region in the CMP planarization process.

Then, the element isolation region of the exposed semiconductor substrate, which is not protected by the photoresist pattern, is etched to a predetermined depth to form the trench T1. The trenches T1 are formed by anisotropic etching using Reactive Ion Etching (RIE) or plasma etching. Therefore, the upper portion of the substrate 100 on which the trench T1 is not formed becomes the active region.

Next, the photoresist pattern is removed by a method such as oxygen ashing (O ₂ ashing), and then a charring process is performed on the semiconductor substrate 100 in order to remove foreign substances.

In order to heal the exposed portion of the substrate 100 damaged during the formation of the trench T1 and to relieve the stress between the insulating material and the substrate before the insulating material for trench filling is deposited, Not shown) can be formed.

Referring to FIG. 1C, an insulating material layer 14 serving as an element isolation film is formed on the exposed pad nitride film 120 including the trench to a thickness enough to fill the trench. At this time, the thickness of the pad nitride film 120 is about 1000 angstroms. The insulating material layer 14 is formed by depositing a HDP oxide film (high density plasma oxide), and the HDP oxide film is deposited on the upper corner of the trench The density of the HDP oxide film is lower than that of the other regions.

The step difference d2 in the device isolation region and the device active region on the upper surface of the insulating material layer 14 causes a defect in the subsequent planarization process such as CMP.

Referring to FIG. 1D, the substrate 100 is annealed to increase the density of the insulating material layer to be an element isolation film.

Then, a planarization process is performed on the insulating material layer to leave only the insulating material layer in the trench and expose the surface of the pad nitride film 120 at the same time. At this time, the planarization process proceeds by chemical mechanical polishing (CMP), which partially removes the thickness of the pad nitride film 120, thereby securing the planarization of the entire substrate. Therefore, the thickness of the CMP pad nitride film 120 is about 700 ANGSTROM. If the CMP is excessively polished, the portion E of the substrate 100 corresponding to the active region of the device may be damaged.

Although not shown, the remaining pad nitride film is removed to expose the surface of the buffer oxide film. At this time, the pad nitride film is removed using hot H ₃ PO ₄ , and a portion of the insulating material layer 140 remaining in the trench is also removed to a predetermined thickness during the etching to remove the exposed buffer oxide film 110 And the surface step of the remaining insulating material layer 140 is partially reduced.

Then, the buffer oxide film is removed by wet etching using a hydrofluoric acid (HF) solution to expose the surface of the device active region. At this time, since the density of the upper edge portion of the flattened insulating material layer made of the oxide film is lower than that of the other portions, a part of the insulating material layer at the boundary between the device isolation region defined by the planarized insulating material layer 140 and the active region So as to form a groove M.

An oxide layer (not shown) is formed on the active region of the exposed substrate 100 by a thermal oxidation process so as to be used as an ion implantation buffer layer for adjusting a threshold voltage of the active region.

Then, the threshold voltage of the active region is adjusted by implanting ions for controlling the threshold voltage into the entire surface of the substrate with an impurity ion of a suitable conductivity type.

Referring to the next, an oxide film used as an ion implantation buffer film is removed by wet etching to form a semiconductor device including a gate and the like.

Thus, the device isolation film made of a planarized and remaining insulating material layer is completed, and the device isolation region and the active region are isolated.

Then, although not shown, a conductive layer such as doped polysilicon is formed on a substrate and then patterned to manufacture a device such as a gate.

However, in the above-described conventional device isolation method of a semiconductor device, when the active area of the device is relatively larger than the device isolation area, the step between the isolation region of the field insulation film formation insulating material layer and the active area of the device becomes deeper, It is difficult to obtain a uniform planarization result in the planarization process to be used, and since the thickness of the pad nitride film is uniform, there is a problem that the edge portion of the substrate of the active region may be damaged when the pad nitride film is subjected to excessive polishing.

Accordingly, it is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, in which a pad nitride film pattern defining a device active region in a shallow trench isolation (STI) process is formed in a recessed shape with a concave central portion and a convex edge, And a method of forming a field insulating film of a semiconductor device using chemical mechanical polishing, which prevents over-etching of corner portions of the active region during chemical mechanical polishing for planarization and forms a field insulating film having a uniform surface.

According to another aspect of the present invention, there is provided a method of isolating elements in a semiconductor device, the method comprising: a first step of forming a hard mask covering a device active region on a semiconductor substrate and having a thicker edge than a central region; A second step of forming a trench to define a device isolation region by removing the exposed substrate to a predetermined depth; forming an insulating material layer having a thickness enough to fill the trench on the substrate including the hard mask A fourth step of chemical-mechanical polishing the insulating material layer to expose a center portion of the hard mask, thereby leaving the insulating material layer only in the trench; and a fifth step of removing the hard mask .

Preferably, the first step includes sequentially forming a buffer layer and a pad layer on the substrate, forming a photoresist pattern covering only the active region of the device on the pad layer, And removing the photoresist pattern by anisotropically etching the pad layer of the portion not protected by the photoresist pattern and exposing the buffer layer; and removing the photoresist pattern, The step of applying the photoresist on the pad layer comprises the steps of: applying a photoresist on the pad layer; and applying a photoresist on the pad layer by completely exposing the element isolation region, shielding the edge portion of the element active region, Exposing the photoresist to light, exposing the exposed photoresist The achieved by further comprising the step of developing.

1A to 1D are process sectional views showing a device isolation method of a semiconductor device according to the related art

FIGS. 2A to 2F are cross-sectional views showing a device isolation method of a semiconductor device according to the present invention

In the present invention, when a gap filling insulating material layer is polished by CMP (Chemical Mechanical Polishing) in the STI process for defining an active region by using an isolation film to expose the surface of the pad nitride film to planarize, A cross section pattern of the pad nitride film covering the upper portion of the active device region having a large size is formed in a convex and concave shape having a concave central portion and a convex edge portion to artificially form steps in a pad nitride film as a hard mask for etch blocking of a silicon substrate , The upper surface step of the layer of insulating material to be deposited is reduced to improve the surface uniformity of the element isolation film remaining in the trench and at the same time the edge portion of the element active region defined by the trench is protected from excessive polishing.

Such a concavo-convex pad nitride film pattern is formed by forming a nitride film with a buffer oxide film on a substrate to a predetermined thickness, applying a photoresist on the nitride film, and then leaving the photoresist only in the active region, A photoresist pattern having a larger edge portion than the central portion is formed by exposure and development using an exposure mask which completely blocks the light and exposes only a part of the thickness of the central portion of the active region of the device, and then the pad nitride film is etched by anisotropic etching Thereby forming the above-described pad nitride film pattern. That is, by forming the photoresist pattern so that the cross-sectional profile of the photoresist pattern is irregular, by forming the photoresist pattern so as to have a different transmittance so as to selectively pass the light through the photoresist mask, and then etching the pad nitride film using the photoresist pattern, To produce a pattern.

Therefore, in the present invention, since the upper surface step of the gap-filling insulating material between the active region and the isolation region can be reduced, uniform flatness of the isolation film made of the insulating material remaining after CMP can be realized, Since the pad nitride film pattern at the corner of the active region is thicker than the other regions, excessive polishing of the active region substrate located below the pad nitride film pattern is prevented.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

2A to 2F are process sectional views showing a device isolation method of a semiconductor device according to the present invention.

Referring to FIG. 2A, a buffer oxide film 21 is formed on a semiconductor substrate 20 made of silicon by a thermal oxidation method, and a chemical vapor deposition (hereinafter referred to as CVD) Silicon nitride is deposited to form the pad nitride film 22. At this time, the buffer oxide film 21 is formed to mitigate the stress generated between the silicon nitride and the silicon of the substrate, and the buffer oxide film 21 can be formed by using a thermal oxidation method and a chemical vapor deposition method together. In addition, the pad nitride film 22 is used for etch blocking during CMP on an insulating material layer which will be a device isolation film.

Then, a photoresist is applied on the pad nitride film 22, and then exposure is performed using an exposure mask 24 defining a trench formation region to be a device isolation region to selectively expose a predetermined portion of the applied photoresist . At this time, the exposure mask 24 is formed of a transparent material such as quartz and is formed of a first mask 240 for completely transmitting light, and a second active layer 240 for defining a device active region, And a third mask 242 for covering the edge of the second mask 241 and covering the edge of the second mask 241. That is, the first mask 240 defines a full exposure area W, the third mask 242 defines a light shielding area N, and the second mask 241 defines an incomplete light transmitting area H, .

As a result of exposure of the photoresist 23 using the exposure mask 24, the first photoresist 232 and the second photoresist 230 are exposed.

That is, the first photoresists 231 and 232 that are completely exposed are removed in the developing process, but the unexposed second photoresist remains on the pad nitride film 22 to define the active region of the device.

However, since the transmissivity of the center portion of the active region of the exposure mask 24 is low, the remaining photoresist in the active region of the device is located at the bottom of the unexposed second photoresist 230, (231).

Referring to FIG. 2B, the exposed photoresist is developed to remove the exposed first photoresist, leaving only the unexposed second photoresist 230 on the pad nitride film 22.

Therefore, the cross-sectional profile of the remaining second photoresist 230 has a convex-concave shape with a concave shape at the center portion and a convex shape at the edge portion.

Referring to FIG. 2C, anisotropic etching such as dry etching using the second photoresist as an etching mask is performed on the exposed pad nitride film to remove a nitride film in a portion not protected by the second photoresist 233, A pad nitride film pattern 220 made of a nitride film is formed. At this time, the buffer oxide film 21 is used as an etch stop layer.

As a result of the etching, the second photoresist is thinner than the edge, so that part of the second photoresist is removed during etching, so that part of the pad nitride film covering the active region is also etched, And the central portion of the second photoresist 233 is completely removed.

Referring to FIG. 2D, the remaining second photoresist is removed to completely expose the upper surface of the pad nitride film pattern 220 defining the active region of the device. At this time, the second photoresist may be used as a part of the etching mask and removed after formation of the trench.

Then, the element isolation region of the exposed semiconductor substrate, which is not protected by the pad nitride film pattern 220, is etched to a predetermined depth to form a trench serving as an element isolation region. The trenches are formed by anisotropically etching the buffer oxide film and the substrate using Reactive Ion Etching (RIE) or plasma etching. Accordingly, a portion of the substrate 200 corresponding to the lower portion of the pad nitride film pattern 220 becomes a device active region without forming a trench.

The oxide layer (not shown) is formed on the exposed trench surface in order to heal exposed portions of the substrate 200 damaged during the formation of the trench T2 and to reduce the stress between the insulating material and the substrate before depositing the insulating material for trench filling. Can be formed.

Referring to FIG. 2E, an insulating material layer 25 serving as an element isolating film is formed on the exposed pad nitride film 220 including the trench to a thickness enough to fill the trench. At this time, the insulating material layer 25 is formed by depositing an HDP oxide film (high density plasma oxide) or the like.

At this time, the upper surface of the insulating material layer 25 has different steps in the active region and isolation regions. That is, the device isolation region has a step difference of 'd2', but has a step difference of 'd1' in the device active region, which is attributable to the concavo-convex shape of the pad nitride film pattern 220. Therefore, the recessed portion B of the insulating material layer 25 located on the recessed portion above the pad nitride film pattern 220 of the active region serves to prevent a decrease in flatness due to a step with the element isolation region at the time of CMP do.

The reference numeral 'P' indicates the thickness to be removed by polishing in the subsequent CMP process.

In order to increase the density of the insulating material layer 25 to be a device isolation film, the substrate 200 may be subjected to a densification by annealing or the like.

Referring to FIG. 2F, the insulating material layer is planarized to expose the surface of the pad nitride film pattern 211 while leaving only the insulating material layer in the trench. At this time, the planarization process proceeds by chemical mechanical polishing (CMP), which partially removes the thickness of the pad nitride film pattern, thereby securing the planarization of the entire substrate. At this time, even if the CMP is excessively polished, since the pad nitride film pattern is formed thick in the portion E of the substrate 200 corresponding to the edge of the active region, it is protected from excessive polishing to improve the reliability of the device.

Although not shown, the remaining pad nitride film pattern is removed to expose the surface of the buffer oxide film. At this time, the removal of the pad nitride film pattern is performed by using hot H ₃ PO ₄ .

Then, the buffer oxide film is removed by wet etching using a hydrofluoric acid (HF) solution to expose the surface of the device active region.

Then, an oxide film (not shown) is grown on the active region of the exposed substrate 200 by a thermal oxidation process so as to be used as an ion implantation buffer film for adjusting a threshold voltage of the active region, The threshold voltage of the active region is adjusted by conducting ion implantation for adjusting the threshold voltage with a conductive impurity ion.

Referring to the next, an oxide film used as an ion implantation buffer film is removed by wet etching to form a semiconductor device including a gate and the like.

Thus, the device isolation film made of a planarized and remaining insulating material layer is completed, and the device isolation region and the active region are isolated.

Then, although not shown, a conductive layer such as doped polysilicon is formed on a substrate and then patterned to manufacture a device such as a gate.

Therefore, the present invention can reduce the upper surface level difference of the gap-filling insulating material between the active region and the isolation region, so that uniform flatness of the isolation film made of the insulating material remaining after CMP can be realized, Since the pad nitride film pattern at the corner of the active region of the device is formed thicker than the other regions, it is advantageous to prevent the excessive polishing of the active region substrate located below the pad nitride film pattern.

Claims (5)

A first step of forming a hard mask covering the active region on the semiconductor substrate and having a thicker edge than the central region, A second step of removing the exposed substrate not protected by the hard mask to a predetermined depth to form a trench defining an isolation region, A third step of forming an insulating material layer on the substrate including the hard mask to a thickness enough to fill the trench, Performing a chemical mechanical polishing on the insulating material layer so as to expose the central portion of the hard mask, thereby leaving only the insulating material layer in the trench; And removing the hard mask. The method according to claim 1, In the first step, Sequentially forming a buffer layer and a pad layer on the substrate, Forming a photoresist pattern on the pad layer, the photoresist pattern covering only the active region of the device and having an edge portion thicker than a center portion; Removing the pad layer of the portion not protected by the photoresist pattern by anisotropic etching to expose the buffer layer; And removing the photoresist pattern. The method of claim 2, Wherein the buffer layer is formed of an oxide film and the pad layer is formed of a nitride film. The method of claim 2, Wherein the step of forming the photoresist pattern comprises: Applying a photoresist on the pad layer, Exposing the photoresist using an exposure mask for completely projecting the element isolation region, shielding a peripheral portion of the element active region and incompletely projecting a central portion of the active region, And developing the exposed photoresist. ≪ Desc / Clms Page number 19 > The method according to claim 1, Wherein the element isolation region is formed so that the element active region is larger than the element isolation region.