KR100338948B1 - 반도체 장치의 분리구조 형성방법 - Google Patents
반도체 장치의 분리구조 형성방법 Download PDFInfo
- Publication number
- KR100338948B1 KR100338948B1 KR1019990057487A KR19990057487A KR100338948B1 KR 100338948 B1 KR100338948 B1 KR 100338948B1 KR 1019990057487 A KR1019990057487 A KR 1019990057487A KR 19990057487 A KR19990057487 A KR 19990057487A KR 100338948 B1 KR100338948 B1 KR 100338948B1
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- trench
- oxide film
- exposed
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (1)
- 기판의 상부에 위치하는 패드산화막과 질화막이 적층된 하드마스크를 이용하여 기판의 일부를 건식식각하여 얕은 트랜치를 형성하는 트랜치 형성단계와; 상기 구조의 상부전면에 포토레지스트를 도포하고, 노광 및 현상하여 상기 트랜치 양측의 질화막의 일부를 노출시키는 패턴을 형성하는 라운드패턴 형성단계와; 상기 포토레지스트 패턴을 식각마스크로 사용하는 식각공정으로 상기 노출된 질화막과 그 하부의 패드산화막을 제거하여, 상기 트랜치의 상부측면인 기판의 첨점부를 노출시키는 첨점부 노출단계와; 상기 포토레지스트 패턴을 제거하고 열산화공정을 통해 상기 트랜치의 측면 및 저면과, 상기 기판의 첨점부를 포함한 상부영역에 산화막을 형성하는 열산화막 형성단계와; 상기 열산화막을 식각하여 노출된 기판의 첨점부를 둥글게 형성한 후, 산화막을 증착하고, 그 산화막을 질화막이 노출될때까지 평탄화하는 단계와; 상기 노출된 질화막과 하부의 패드산화막을 식각하여 상기 트랜치 내에 위치하는 분리구조를 형성하는 첨점부 연마 및 분리구조 형성단계로 이루어진 것을 특징으로 하는 반도체 장치의 분리구조 형성방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990057487A KR100338948B1 (ko) | 1999-12-14 | 1999-12-14 | 반도체 장치의 분리구조 형성방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990057487A KR100338948B1 (ko) | 1999-12-14 | 1999-12-14 | 반도체 장치의 분리구조 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010056068A KR20010056068A (ko) | 2001-07-04 |
KR100338948B1 true KR100338948B1 (ko) | 2002-05-31 |
Family
ID=19625670
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019990057487A Expired - Fee Related KR100338948B1 (ko) | 1999-12-14 | 1999-12-14 | 반도체 장치의 분리구조 형성방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100338948B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20040021371A (ko) * | 2002-09-04 | 2004-03-10 | 아남반도체 주식회사 | 반도체 소자의 셀로우 트렌치 분리막 형성 방법 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5712185A (en) * | 1996-04-23 | 1998-01-27 | United Microelectronics | Method for forming shallow trench isolation |
-
1999
- 1999-12-14 KR KR1019990057487A patent/KR100338948B1/ko not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5712185A (en) * | 1996-04-23 | 1998-01-27 | United Microelectronics | Method for forming shallow trench isolation |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20040021371A (ko) * | 2002-09-04 | 2004-03-10 | 아남반도체 주식회사 | 반도체 소자의 셀로우 트렌치 분리막 형성 방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20010056068A (ko) | 2001-07-04 |
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