KR100331261B1 - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR100331261B1 KR100331261B1 KR1019980062538A KR19980062538A KR100331261B1 KR 100331261 B1 KR100331261 B1 KR 100331261B1 KR 1019980062538 A KR1019980062538 A KR 1019980062538A KR 19980062538 A KR19980062538 A KR 19980062538A KR 100331261 B1 KR100331261 B1 KR 100331261B1
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- semiconductor device
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- nitride film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 18
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010936 titanium Substances 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 12
- 230000001590 oxidative effect Effects 0.000 claims abstract description 7
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 239000011259 mixed solution Substances 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 21
- 238000000034 method Methods 0.000 abstract description 8
- 239000003989 dielectric material Substances 0.000 abstract description 3
- 238000005137 deposition process Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-NJFSPNSNSA-N silicon-30 atom Chemical compound [30Si] XUIMIQQOPSSXEZ-NJFSPNSNSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 21
- 238000003860 storage Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- NMJKIRUDPFBRHW-UHFFFAOYSA-N titanium Chemical compound [Ti].[Ti] NMJKIRUDPFBRHW-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체장치의 커패시터를 형성함에 있어서 티타늄알루미늄질화막을 증착하여 패터닝한 후 그 표면을 산화시켜 고유전체인 알루미늄산화물층을 형성시켜 커패시터를 형성하는 반도체장치의 제조 방법에 관한 것으로, 하부절연층이 형성된 반도체기판의 접합층(10)을 노출시키는 콘택홀(40)을 형성하는 단계와, 도핑된 다결정실리콘(30)을 증착하여 콘택홀(40)을 충진시키는 단계와, 콘택홀(40)이 충진된 결과물 전면에 티타늄층(50)을 증착하고 열처리를 통하여 다결정실리콘(30) 상부에 티타늄실리사이드(60)를 형성하는 단계와, 실리사이드화되지 않는 티타늄층(50)을 제거하여 다결정실리콘(30) 상부에만 티타늄실리사이드층(60)을 남기는 단계와, 결과물 전면에 티타늄알루미늄질화막(70)을 증착하여 패터닝하는 단계와, 패터닝된 결과물을 산화분위기에서 열처리하여 티타늄알루미늄질화막(70)의 표면에 알루미늄산화막(80)을 형성시키는 단계와, 알루미늄산화막(80) 상부에 상부전극(90)을 형성하는 단계를 포함하여 이루어짐으로써 증착과정없이 100%의 단차피복성을 얻을 수 있어 공정의 안정성을 확보할 뿐만아니라 높은 유전율로 소자의 성능을 향상시킬 수 있다는 이점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a capacitor is formed by depositing and patterning a titanium aluminum nitride film and then oxidizing its surface to form an aluminum oxide layer as a high dielectric material. Forming a contact hole 40 exposing the bonding layer 10 of the formed semiconductor substrate, filling the contact hole 40 by depositing the doped polysilicon 30, and contact hole 40; Depositing a titanium layer 50 on the entire surface of the resultant, and forming a titanium silicide 60 on the polycrystalline silicon 30 through heat treatment, and removing the unsilicided titanium layer 50 from the polycrystalline silicon ( 30) leaving the titanium silicide layer 60 only on the upper part, depositing and patterning the titanium aluminum nitride film 70 on the entire surface of the resultant, and oxidizing the patterned resultant. Forming an aluminum oxide film 80 on the surface of the titanium aluminum nitride film 70 by heat treatment in a crisis, and forming an upper electrode 90 on the aluminum oxide film 80, thereby eliminating the deposition process. It is possible to obtain the step coverage of, which not only ensures the stability of the process but also improves the performance of the device with a high dielectric constant.
Description
본 발명은 반도체장치의 제조 방법에 관한 것으로서, 보다 상세하게는 반도체장치의 커패시터를 형성함에 있어서 티타늄알루미늄질화막을 증착하여 패터닝한 후 그 표면을 산화시켜 고유전체인 알루미늄산화물층을 형성시켜 커패시터를 형성하는 반도체장치의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, in forming a capacitor of a semiconductor device, depositing and patterning a titanium aluminum nitride film, and then oxidizing the surface to form an aluminum oxide layer as a high dielectric material to form a capacitor. It relates to a method for manufacturing a semiconductor device.
일반적으로, 반도체장치의 종류에는 여러 가지가 있으며, 이 반도체장치 내에 형성되는 트랜지스터 및 캐패시터등을 구성시키는 방법에는 다양한 제조기술이 사용되고 있으며 특히, 개패시터의 경우에는 적은 면적에도 불구하고 정전용량이 증가되어야 한다. 따라서 이러한 문제점들을 해결하기 위해 적은 면적에서도 표면적을 최대로 할 수 있는 구조를 연구하게 된다.In general, there are many kinds of semiconductor devices, and various manufacturing techniques are used to configure transistors, capacitors, and the like formed in the semiconductor device. In particular, in the case of a capacitor, capacitance increases despite a small area. Should be. Therefore, in order to solve these problems, the structure that can maximize the surface area in a small area is studied.
현재 반도체 소자는 고집적화가 이루어질수록 캐패시터의 면적은 급격하게 감소되고 있기 때문에 기억소자의 동작에 필요한 전하 즉, 단위 면적에 확보되는 캐패시턴스를 더욱 증가시켜야만 한다.At present, since the area of the capacitor is rapidly decreasing as the semiconductor device is highly integrated, the charge required for the operation of the memory device, that is, the capacitance secured in the unit area, must be further increased.
한편, 메모리 셀에 사용되는 캐패시터의 기본 구조는 전하저장전극용 하부 전극, 유전막 및 플레이트(plate)용 상부전극으로 구성된다. 이러한 구조를 가지는 캐패시터는 작은 면적 내에서 보다 큰 고정전용량을 얻기 위해서 첫째 얇은 유전막 두께를 확보하거나, 둘째 3차원적인 캐패시터의 구조를 통해서 유효 면적을 증가시키거나, 셋째 유전율이 높은 물질을 사용하여 유전막을 형성하는 등의 몇 가지 조건이 만족되어야만 한다.Meanwhile, the basic structure of a capacitor used in a memory cell is composed of a lower electrode for a charge storage electrode, a dielectric film, and an upper electrode for a plate. Capacitors with this structure can be used to secure the first thin dielectric film thickness, to increase the effective area through the structure of three-dimensional capacitors, or to use materials with high dielectric constants in order to obtain a larger fixed capacitance in a small area. Several conditions must be met, such as forming a dielectric film.
도1은 일반적으로 사용되고 있는 캐패시터의 구조를 나타낸 단면도로서 (a)는 핀구조의 캐패시터를 나타낸 단면도이고 (b)는 실린더구조의 캐패시터를 나타낸 단면도이다.1 is a cross-sectional view showing the structure of a capacitor generally used, (a) is a cross-sectional view showing a capacitor of the fin structure (b) is a cross-sectional view showing a capacitor of the cylinder structure.
위와 같이 캐패시터의 구조의 변형은 동일한 크기내에서 넓은 단면적을 갖을 수 있도록 하기 위한 것이다.The deformation of the structure of the capacitor as described above is intended to have a large cross-sectional area within the same size.
위의 핀구조의 전하저장전극은 후속공정에 토폴로지를 크게주지 않는 장점이 있는 반면, 실린더구조에 비해 공정이 복잡한 단점을 가지고 있어 최근에는 실린더구조로 전하저장전극을 형성하는 추세다.The above fin structured charge storage electrode has the advantage of not giving a large topology to a subsequent process, while the process has a complicated disadvantage compared to the cylinder structure, and in recent years, the charge storage electrode has a trend of forming a cylinder structure.
그러나 실린더구조의 전하저장전극은 반도체장치가 고집적화됨에 따라 정전용량의 확보를 위해 보다 높은 토폴로지가 요구되고 있으며, 브리지페일의 가능성도 높아지고 있다는 문제점이 있다.However, the cylinder-type charge storage electrode has a problem that as the semiconductor device is highly integrated, a higher topology is required for securing the capacitance, and the possibility of bridge fail is also increased.
따라서, 정전용량을 확보하기 위해 유전율이 큰 Ta2O5 를 사용하려는 노력이 한참 진행중이다. 그러나 본 발명에서는 Ta2O5보다 유전율이 큰 알루미늄산화물(Al2O3)이 있으나 박막의 대표적인 형성방법인 스퍼터링 및 CVD로 양질의 Al2O3 박막을 3차원 구조를 갖는 고단차의 하부전극에 형성하는데 어려움이 있어 실제 소자에 적용하지 못하는 문제점이 있다.Therefore, efforts are being made to use Ta2O5 having a high dielectric constant to secure capacitance. However, in the present invention, although there is aluminum oxide (Al2O3) having a higher dielectric constant than Ta2O5, it is difficult to form a high quality Al2O3 thin film on a high stepped lower electrode having a three-dimensional structure by sputtering and CVD, which is a typical method of forming a thin film. There is a problem that cannot be applied.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 고유전체인 치밀하고 균일한 Al2O3박막을 TiAlN막의 표면을 산화시켜 하부전극에 형성함으로써 정전용량이 풍부한 커패시터를 제조할 수 있도록 한 반도체장치의 제조 방법을 제공함에 있다.The present invention was created to solve the above problems, and an object of the present invention is to form a capacitor having a high capacitance by forming a dense and uniform Al 2 O 3 thin film on the lower electrode by oxidizing the surface of the TiAlN film. The present invention provides a method for manufacturing a semiconductor device.
도1은 일반적으로 사용되고 있는 캐패시터의 구조를 나타낸 단면도이다.1 is a cross-sectional view showing the structure of a capacitor generally used.
도 2내지 도9는 본 발명에 의한 반도체장치의 커패시터 제조 방법을 설명하기 위한 단면도들이다.2 to 9 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 접합층 20 : 하부절연층10: bonding layer 20: lower insulating layer
30 : 다결정실리콘 40 : 콘택홀30: polysilicon 40: contact hole
50 : 티타늄층 60 : 티타늄실리사이드층50: titanium layer 60: titanium silicide layer
70 : 티타늄알루미늄질화막 80 : 알루미늄산화막70 titanium titanium nitride film 80 aluminum oxide film
90 : 상부전극90: upper electrode
상기와 같은 목적을 실현하기 위한 본 발명은 하부절연층이 형성된 반도체기판의 접합층을 노출시키는 콘택홀을 형성하는 단계와, 도핑된 다결정실리콘을 증착하여 콘택홀을 충진시키는 단계와, 콘택홀이 충진된 결과물 전면에 티타늄층을 증착하고 열처리를 통하여 다결정실리콘 상부에 티타늄실리사이드층를 형성하는 단계와, 실리사이드화하지 않는 티타늄층을 제거하여 다결정실리콘 상부에만 타타늄실리사이드층을 남기는 단계와, 티타늄알루미늄질화막을 증착하여 패터닝하는 단계와, 패터닝된 결과물을 산화분위기에서 열처리하여 티타늄알루미늄질화막의 표면에 알루미늄산화막을 형성시키는 단계와, 알루미늄산화막 상부에 상부전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is to form a contact hole for exposing the bonding layer of the semiconductor substrate on which the lower insulating layer is formed, the step of filling the contact hole by depositing the doped polycrystalline silicon, Depositing a titanium layer on the entire surface of the filled product and forming a titanium silicide layer on the polycrystalline silicon through heat treatment; And depositing a patterned pattern, heat treating the patterned result in an oxidizing atmosphere to form an aluminum oxide film on the surface of the titanium aluminum nitride film, and forming an upper electrode on the aluminum oxide film.
위와 같이 이루어진 본 발명의 작용을 설명하면 다음과 같다.Referring to the operation of the present invention made as described above are as follows.
단차에 관계없이 균일한 두께로 형성되는 티타늄알루미늄질화막의 표면을 산화시켜 고유전체인 알루미늄산화막을 형성함으로써 커패시터의 유전체로 사용함으로써 정전용량이 풍부한 커패시터를 제조할 수 있도록 한다.By oxidizing the surface of the titanium aluminum nitride film formed to a uniform thickness irrespective of the step difference to form a high-k dielectric aluminum oxide film can be used as a dielectric of the capacitor to produce a capacitor rich in capacitance.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도 2내지 도9는 본 발명에 의한 반도체장치의 커패시터 제조 방법을 설명하기 위한 단면도들이다.2 to 9 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 2와 같이 하부절연층이 형성된 반도체기판의 접합층(10)을 노출시키는 콘택홀(40)을 형성한 후 도핑된 다결정실리콘(30)을 증착하여 콘택홀(40)을 충진시킨다.As shown in FIG. 2, after forming the contact hole 40 exposing the bonding layer 10 of the semiconductor substrate on which the lower insulating layer is formed, the doped polysilicon 30 is deposited to fill the contact hole 40.
그리고 도 3과 같이 도 2의 전면에 티타늄층(50)을 100∼1000Å의 두께로 증착한 후 600∼800℃의 온도에서 질소 또는 아르곤 분위기에서 열처리하여 도 4와 같이 다결정실리콘(30)의 티타늄실리사이드층(60)를 형성한다.As shown in FIG. 3, the titanium layer 50 is deposited on the entire surface of FIG. 2 to a thickness of 100 to 1000 kPa, and then heat-treated in nitrogen or argon at a temperature of 600 to 800 ° C. to form titanium of the polysilicon 30 as shown in FIG. 4. The silicide layer 60 is formed.
그런다음 도 5와 같이 실리사이드화되지 않는 티타늄층(50)을 NH4OH / H2O2 / H2O의 혼합용액을 사용하여 제거하여 다결정실리콘(30) 상부에만 티타늄실리사이드층(60)를 남긴다.Then, the silicided titanium layer 50 is removed using a mixed solution of NH 4 OH / H 2 O 2 / H 2 O as shown in FIG. 5, leaving the titanium silicide layer 60 only on the polysilicon 30.
그리고 도 6과 같이 Ti : Al의 조성비를 9:1∼2:8로 하여 티타늄알루미늄질화막(70)을 증착한 후 도 7과 같이 티타늄알루미늄질화막(70)을 패터닝한 다음 도 8과 같이 O2나 N2O나 O3의 분위기에서 500∼1000℃에서 열처리하여 티타늄알루미늄질화막(70)의 표면에 30∼500Å 두께의 알루미늄산화막(80)을 형성시킨다.As shown in FIG. 6, the titanium aluminum nitride film 70 is deposited using a Ti: Al ratio of 9: 1 to 2: 8, and the titanium aluminum nitride film 70 is patterned as shown in FIG. 7. The aluminum oxide film 80 having a thickness of 30 to 500 Å is formed on the surface of the titanium aluminum nitride film 70 by heat treatment at 500 to 1000 ° C. in an N 2 O or O 3 atmosphere.
그런다음 도 9와 같이 알루미늄산화막(80) 위로 TiCl4와 NH3를 이용하여 CVD 방법으로 티타늄질화막을 100∼500Å의 두께로 상부전극(90)을 형성하여 커패시터를 형성하게 된다.Then, as illustrated in FIG. 9, the titanium nitride film is formed on the aluminum oxide film 80 by using a TiCl 4 and NH 3 to form a capacitor by forming an upper electrode 90 with a thickness of 100 to 500 kW.
상기한 바와 같이 본 발명은 커패시터의 하부전극으로 티타늄알루미늄질화막을 증착한 후 패터닝하여 그 표면을 산화시켜 고유전체인 알루미늄산화막을 형성함으로써 증착과정없이 100%의 단차피복성을 얻을 수 있어 공정의 안정성의 확보가 용이할 뿐만아니라 증착에 의하여 형성된 알루미늄산화막에 비하여 유전체로서이 특성이 우수하여 소자의 성능을 향상시킬 수 있다는 이점이 있다.As described above, the present invention deposits a titanium aluminum nitride film as a lower electrode of the capacitor, and then patterns and oxidizes the surface thereof to form an aluminum oxide film, which is a high dielectric material, thereby obtaining 100% step coverage without deposition. In addition, it is easy to secure and has the advantage that the characteristics of the device can be improved as the dielectric is superior to the aluminum oxide film formed by deposition.
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| US5231306A (en) * | 1992-01-31 | 1993-07-27 | Micron Technology, Inc. | Titanium/aluminum/nitrogen material for semiconductor devices |
| KR19980053082A (en) * | 1996-12-26 | 1998-09-25 | 김영환 | Capacitor Manufacturing Method of Semiconductor Device |
| KR19980085034A (en) * | 1997-05-27 | 1998-12-05 | 윤종용 | Lower electrode of semiconductor device by nitriding metal silicide and method of manufacturing capacitor including same |
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| US5231306A (en) * | 1992-01-31 | 1993-07-27 | Micron Technology, Inc. | Titanium/aluminum/nitrogen material for semiconductor devices |
| KR19980053082A (en) * | 1996-12-26 | 1998-09-25 | 김영환 | Capacitor Manufacturing Method of Semiconductor Device |
| KR19980085034A (en) * | 1997-05-27 | 1998-12-05 | 윤종용 | Lower electrode of semiconductor device by nitriding metal silicide and method of manufacturing capacitor including same |
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