KR100265333B1 - Manufacturing method of high dielectric capacitor of semiconductor device - Google Patents
Manufacturing method of high dielectric capacitor of semiconductor device Download PDFInfo
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- KR100265333B1 KR100265333B1 KR1019970077926A KR19970077926A KR100265333B1 KR 100265333 B1 KR100265333 B1 KR 100265333B1 KR 1019970077926 A KR1019970077926 A KR 1019970077926A KR 19970077926 A KR19970077926 A KR 19970077926A KR 100265333 B1 KR100265333 B1 KR 100265333B1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000010408 film Substances 0.000 claims abstract description 65
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 238000009832 plasma treatment Methods 0.000 claims abstract description 6
- 239000010936 titanium Substances 0.000 claims description 17
- 229910052719 titanium Inorganic materials 0.000 claims description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- 229910002367 SrTiO Inorganic materials 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 8
- 239000001301 oxygen Substances 0.000 abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 230000008021 deposition Effects 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 238000002425 crystallisation Methods 0.000 abstract description 3
- 230000008025 crystallization Effects 0.000 abstract description 3
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- -1 titanium oxide nitride Chemical class 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000003405 preventing effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/694—Electrodes comprising noble metals or noble metal oxides
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Abstract
본 발명은 반도체 제조 분야에 관한 것으로, 특히 차세대 초고집적 DRAM 및 FeRAM에 적용되는 고유전체 캐패시터 및 그 제조방법에 관한 것이며, 확산 방지막을 포함한 하부 전극의 열적 안정성 및 내산화성을 확보하는 반도체 장치의 고유전체 캐패시터 제조방법을 제공하는데 그 목적이 있다. 본 발명은 반도체 소자의 고유전체 캐패시터 공정중 하부전극으로서 백금(Pt)막을 증착한 후 플라즈마 처리를 통하여 원형 구조의 결정질을 비정질화시키면, 고유전체 박막의 고온 증착 및 후속 열처리시의 산소 분위기에서도 산소의 확산 경로를 차단할 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a high dielectric capacitor and a method of manufacturing the same, which are applied to next-generation ultra-high density DRAM and FeRAM, and inherent in semiconductor devices to secure thermal stability and oxidation resistance of a lower electrode including a diffusion barrier. It is an object of the present invention to provide a whole capacitor manufacturing method. According to the present invention, when a platinum (Pt) film is deposited as a lower electrode during a high-k dielectric capacitor process of a semiconductor device and the crystallization of a crystalline structure of a circular structure is performed through a plasma treatment, the oxygen may be removed even in an oxygen atmosphere during high temperature deposition and subsequent heat treatment of a high-k dielectric thin film. It is a technology that can block the diffusion path of.
Description
본 발명은 반도체 제조 분야에 관한 것으로, 특히 차세대 초고집적 DRAM 및 FeRAM에 적용되는 고유전체 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE
DRAM을 비롯한 반도체 메모리 장치의 고집적화에 따라 반도체 장치의 리프레시(refresh) 특성 등의 동작 특성이 큰 문제로 부각되고 있다. 이에 따라 동작 특성을 확보하기 위하여 충분한 캐패시터의 정전용량을 확보하는 기술에 대한 많은 연구·개발이 진행되고 있다.Background Art With the high integration of semiconductor memory devices including DRAM, operating characteristics such as refresh characteristics of semiconductor devices have become a big problem. Accordingly, many researches and developments have been made on a technology for securing a capacitance of a capacitor sufficient to secure operating characteristics.
종래의 일반적인 캐패시터는 그의 동작 특성 확보에 충분한 정전용량을 제공하기 위하여 하부전극을 3차원 구조화하거나, 유전체 두께를 감소시키는 방법을 사용하여 왔다. 그러나, 반도체 장치의 고집적화에 따라 그 적용 한계에 직면하게 되었다.Conventional general capacitors have used a method of three-dimensional structuring the lower electrode or reducing the dielectric thickness to provide sufficient capacitance to secure its operating characteristics. However, high integration of semiconductor devices has led to application limitations.
이에 따라, FeRAM 및 향후 차세대 반도체 메모리 장치의 캐패시터의 유전막으로서 SrTiO3(이하, STO), (Ba,Sr)TiO3(이하, BST라 함), Pb(Zr,Ti)O3(이하, PZT라 함) 등의 고유전체 박막을 사용하는 고유전체 캐패시터에 대한 연구·개발이 진행되고 있다.As a result, SrTiO 3 (hereinafter referred to as STO), (Ba, Sr) TiO 3 (hereinafter referred to as BST), and Pb (Zr, Ti) O 3 (hereinafter referred to as PZT) as dielectric films for capacitors in FeRAM and next-generation semiconductor memory devices. Research and development of high-k dielectric capacitors using high-k dielectric thin films are being conducted.
이러한 고유전체 캐패시터의 하부전극 재료로서 백금(Pt)이 유력시되고 있다. 이 경우 백금 하부전극과 기판(예를 들어, 폴리실리콘 콘택 플러그)간의 상호 확산을 방지하기 위하여 확산 방지막을 사용하는데, 하부전극 확산 방지막으로는 티타늄질화막(TiN막)이 주로 사용되고 있다. 그러나, TiN막이 고온의 고유전체 박막 증착 공정 및 결정화를 위한 열처리 공정시의 산소 분위기에서 쉽게 산화되어 TiO2막을 형성함으로써 고유전체 캐패시터의 물성을 크게 저하시키는 문제점이 있었다. 이는 Pt막의 결정립계(grain boundary) 또는 원주형 계면(columnar boundary)을 통하여 유입되는 산소에 그 원인이 있다.Platinum (Pt) is a predominant force as a lower electrode material of such a high dielectric capacitor. In this case, a diffusion barrier layer is used to prevent mutual diffusion between the platinum lower electrode and the substrate (for example, polysilicon contact plug). A titanium nitride layer (TiN layer) is mainly used as the diffusion barrier for the lower electrode. However, there is a problem that the TiN film is easily oxidized in an oxygen atmosphere during the high temperature high dielectric film deposition process and the heat treatment process for crystallization to form a TiO 2 film, thereby greatly deteriorating the physical properties of the high dielectric capacitor. This is due to the oxygen introduced through the grain boundary or columnar boundary of the Pt film.
따라서, 기가(giga) DRAM급 반도체 소자에서 요구되는 캐패시터의 유전체 특성 및 전기적 특성을 얻기 위해서는 고유전체 박막의 고온 증착 및 열처리 공정이 필수적이기 때문에 확산 방지막을 포함한 하부전극의 열적 안정성 및 내산화성을 확보하는 기술의 개발이 시급한 실정이다.Therefore, in order to obtain dielectric and electrical characteristics of a capacitor required for a giga DRAM-class semiconductor device, high temperature deposition and heat treatment of a high-k dielectric thin film are essential, thereby securing thermal stability and oxidation resistance of a lower electrode including a diffusion barrier. The development of technology is urgently needed.
본 발명은 확산 방지막을 포함한 하부전극의 열적 안정성 및 내산화성을 확보하는 반도체 장치의 고유전체 캐패시터 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a high dielectric capacitor of a semiconductor device which secures thermal stability and oxidation resistance of a lower electrode including a diffusion barrier.
도 1 내지 도 7은 본 발명의 바람직한 일실시예에 따른 캐패시터 제조 공정 단면도.1 to 7 is a cross-sectional view of a capacitor manufacturing process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : 실리콘 기판 2 : 층간절연막1
3 : 콘택 플러그 4 : 티타늄막(Ti막)3: contact plug 4: titanium film (Ti film)
5 : 티타늄질화막(TiN막) 6 : 티타늄실리사이드막(TiSix막)5: titanium nitride film (TiN film) 6: titanium silicide film (TiSi x film)
7 : 티타늄산화질화막(TiNO막) 8 : 백금막(Pt막)7: titanium oxide nitride film (TiNO film) 8: platinum film (Pt film)
8a : 비정질화된 백금막 9 : BST8a: amorphous platinum film 9: BST
10 : 이산화이리듐막(IrO2)10: iridium dioxide film (IrO 2 )
본 발명은 반도체 소자의 고유전체 캐패시터 공정중 하부전극으로서 백금(Pt)막을 증착한 후 플라즈마 처리를 통하여 원형 구조의 결정질을 비정질화시키면, 고유전체 박막의 고온 증착 및 후속 열처리시의 산소 분위기에서도 산소의 확산 경로를 차단할 수 있는 기술이다.According to the present invention, when a platinum (Pt) film is deposited as a lower electrode during a high-k dielectric capacitor process of a semiconductor device and the crystallization of a crystalline structure of a circular structure is performed through a plasma treatment, the oxygen may be removed even in an oxygen atmosphere during high temperature deposition and subsequent heat treatment of a high-k dielectric thin film. It is a technology that can block the diffusion path of.
상술한 본 발명의 기술적 원리로부터 제공되는 반도체 장치의 고유전체 캐패시터 제조방법은 소정의 하부 구조가 형성된 반도체 기판 상에 전기적으로 콘택되는 장벽 금속막을 형성하는 제1 단계; 상기 장벽 금속막 상부에 하부전극으로서 백금막을 형성하는 제2 단계; 상기 백금막에 Ar 가스 또는 N2가스를 사용하여 플라즈마 처리를 실시하여 상기 백금막의 표면 부분에 비정질층을 형성하는 제3 단계; 상기 백금막 상부에 고유전체 박막을 형성하는 제4 단계; 및 상기 고유전체 박막 상부에 상부전극을 형성하는 제5 단계를 포함하여 이루어진다.A method of manufacturing a high dielectric capacitor of a semiconductor device provided from the above-described technical principles of the present invention includes: a first step of forming a barrier metal film electrically contacted on a semiconductor substrate on which a predetermined substructure is formed; Forming a platinum film as a lower electrode on the barrier metal film; Performing a plasma treatment on the platinum film using Ar gas or N 2 gas to form an amorphous layer on a surface portion of the platinum film; Forming a high dielectric thin film on the platinum film; And a fifth step of forming an upper electrode on the high dielectric thin film.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 소개한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
첨부된 도면 도 1 내지 도 7은 본 발명의 바람직한 일실시예에 따른 강유전체 캐패시터 제조 공정도를 도시한 것으로, 이하 그 공정을 살펴본다.1 to 7 illustrate a process diagram of manufacturing a ferroelectric capacitor according to an exemplary embodiment of the present invention. Hereinafter, the process will be described.
우선, 도 1에 도시된 바와 같이 소정의 하부층 공정을 마친 실리콘 기판(1) 상에 층간절연막(2)을 형성하고, 이를 선택 식각하여 콘택홀을 형성한다. 계속하여, 화학기상증착법을 사용하여 500Å 내지 3000Å 두께의 폴리실리콘막을 증착하고, 이를 에치백하여 콘택 플러그(3)를 형성한다.First, as shown in FIG. 1, an interlayer
다음으로, 도 2에 도시된 바와 같이 전체구조 상부에 100Å 내지 1000Å 두께의 티타늄막(Ti막)(4) 및 200Å내지 2000Å 두께의 티타늄질화막(TiN막)(5)을 차례로 증착한다. 이때, 티타늄막(4) 및 티타늄질화막(5)은 각각 접합층(glue layer) 및 확산 방지막으로서 증착된 것이다.Next, as shown in FIG. 2, a titanium film (Ti film) 4 having a thickness of 100 kPa to 1000 kPa and a titanium nitride film (TiN film) 5 having a thickness of 200 kPa to 2000 kPa are sequentially deposited on the entire structure. At this time, the
이어서, 도 3에 도시된 바와 같이 티타늄질화막(5)의 확산 방지 특성을 향상시키기 위하여 산소 분위기의 고온에서 급속 열처리(RTA)를 실시하여 티타늄질화막(5) 표면에 티타늄산화질화막(TiNO막)(7)을 형성한다. 이러한 고온 열처리시 콘택 플러그(3)의 실리콘(Si)과 티타늄막(4)의 티타늄(Ti)이 반응하여 그 계면에서 티타늄실리사이드막(TiSix막)(6)이 형성된다.Next, as shown in FIG. 3, rapid thermal annealing (RTA) is performed at a high temperature in an oxygen atmosphere in order to improve the diffusion preventing property of the
계속하여, 도 4에 도시된 바와 같이 전체구조 상부에 하부전극으로서 백금막(Pt막)(8)을 500Å 내지 5000Å 두께로 증착한다.Subsequently, as shown in FIG. 4, a platinum film (Pt film) 8 is deposited to a thickness of 500 kV to 5000 kV as a lower electrode on the entire structure.
이어서, 도 5에 도시된 바와 같이 Ar 가스 및 N2가스 분위기에서 1 내지 3㎾의 고주파(RF) 전원을 사용하여 1분 내지 5분 동안 플라즈마(plasma) 처리를 실시하여 원주형 구조의 백금막(8) 표면 부분의 결정 구조를 파괴하여 비정질 구조를 가지는 백금막(8a)으로 상전이 시킨다.Subsequently, as shown in FIG. 5, the plasma film is subjected to plasma treatment for 1 to 5 minutes by using a high frequency (RF) power source of 1 to 3 GHz in an Ar gas and an N 2 gas atmosphere. (8) The crystal structure of the surface portion is destroyed and transferred to the
다음으로, 도 6에 도시된 바와 같이 사진 및 식각 공정을 진행하여 하부전극을 디파인한다. 이때, 티타늄막(4)까지 패터닝 되도록 한다.Next, as shown in FIG. 6, the lower electrode is defined by performing a photo and etching process. At this time, the
이후, 도 7에 도시된 바와 같이 하부전극이 형성된 전체구조 상에 300Å 내지 2000Å 두께의 BST(9)를 형성하고, 그 상부에 500Å 내지 2000Å 두께의 이산화이리듐막(IrO2막)(10)을 화학기상증착법으로 증착한다. 이후, 캐패시터 패터닝 공정을 수행할 수 있다.Subsequently, as shown in FIG. 7, a
상술한 일실시예에 따라 형성된 캐패시터는 표면처리를 거친 그 하부전극이 향상된 열적 안정성 및 내산화성을 가지게 되어 고온 산화 분위기에서의 BST 증착 및 열처리 공정이 가능하므로, 전기적으로 신뢰도가 높은 캐패시터를 제조할 수 있다.The capacitor formed according to the above-described embodiment has a thermally treated lower electrode that has improved thermal stability and oxidation resistance, so that the BST deposition and heat treatment process in a high temperature oxidizing atmosphere is possible, thereby producing a highly reliable capacitor. Can be.
상기한 일실시예에서는 고유전체 박막 및 상부전극을 각각 BST 및 이산화이리듐막으로 사용하고, 장벽 금속으로 Ti/TiN을 사용하는 것을 예로 하여 설명하였으나, 본 발명은 다른 물질을 적용할 수 있다.In the above-described embodiment, the high dielectric thin film and the upper electrode are used as the BST and the iridium dioxide film, respectively, and Ti / TiN is used as the barrier metal. However, the present invention can be applied to other materials.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
이상에서와 같이 본 발명을 실시하면 고유전체 캐패시터의 하부전극의 열적 안정성 및 내산화성이 증가하여 고온 산소 분위기에서의 고유전체 증착 공정이 가능해져 기가 DRAM급 반도체 장치에서 요구되는 캐패시터의 유전 특성 및 전기적 특성을 조기에 확보할 수 있으며, 전기적으로 우수한 특성을 갖는 캐패시터의 제조가 가능하다.As described above, according to the present invention, the thermal stability and the oxidation resistance of the lower electrode of the high dielectric capacitor are increased to enable the deposition of the high dielectric material in a high temperature oxygen atmosphere, and thus the dielectric characteristics and electrical characteristics of the capacitor required in a giga DRAM-class semiconductor device. It is possible to secure the characteristics early, and to manufacture a capacitor having excellent electrical characteristics.
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