KR100318461B1 - Semiconductor device isolation method - Google Patents
Semiconductor device isolation method Download PDFInfo
- Publication number
- KR100318461B1 KR100318461B1 KR1019980042792A KR19980042792A KR100318461B1 KR 100318461 B1 KR100318461 B1 KR 100318461B1 KR 1019980042792 A KR1019980042792 A KR 1019980042792A KR 19980042792 A KR19980042792 A KR 19980042792A KR 100318461 B1 KR100318461 B1 KR 100318461B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- amorphous silicon
- forming
- pad nitride
- oxide film
- Prior art date
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 73
- 150000004767 nitrides Chemical class 0.000 claims abstract description 55
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 48
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 21
- 238000000926 separation method Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 87
- 238000000151 deposition Methods 0.000 claims description 16
- 230000008021 deposition Effects 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 2
- 238000004381 surface treatment Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000004140 cleaning Methods 0.000 claims 1
- 238000007740 vapor deposition Methods 0.000 claims 1
- 230000031700 light absorption Effects 0.000 abstract description 19
- 239000010408 film Substances 0.000 description 129
- 230000003647 oxidation Effects 0.000 description 15
- 238000007254 oxidation reaction Methods 0.000 description 15
- 238000001312 dry etching Methods 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000002835 absorbance Methods 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
Abstract
비정질실리콘을 광흡수막으로 사용함으로써 비정질실리콘의 높은 광흡수율 특성에 의해 250Å이하의 얇은 두께로 하부 기판의 미세한 두께변화와 무관하게 균일한 패턴을 얻어 웨이퍼상에 제작된 모든 소자가 균일한 특성을 가질 수 있도록 하기 위하여실리콘기판상에 패드산화막, 패드질화막을 차례로 형성하는 단계, 상기 패드질화막상에 비정질실리콘막을 50Å∼300Å의 두께로 형성하는 단계, 상기 비정질실리콘막상에 소정의 감광막패턴을 형성하는 단계, 상기 감광막패턴을 마스크로 이용하여 상기 비정질실리콘막, 상기 패드질화막 및 상기 패드산화막을 식각하여 상기 실리콘기판의 소자분리영역을 노출시키는 단계, 및 상기 노출된 실리콘기판을 식각하여 트렌치를 형성하는 단계를 포함하여 구성되는 반도체소자의 분리방법을 제공한다.By using amorphous silicon as a light absorption film, it is possible to obtain a uniform pattern irrespective of the small thickness change of the lower substrate with a thin thickness of less than 250Å by the high light absorption characteristic of amorphous silicon. Forming a pad oxide film and a pad nitride film on a silicon substrate in order to have a thickness; forming an amorphous silicon film on the pad nitride film in a thickness of 50 kPa to 300 kPa, and forming a predetermined photoresist pattern on the amorphous silicon film. Exposing the device isolation region of the silicon substrate by etching the amorphous silicon layer, the pad nitride layer, and the pad oxide layer using the photoresist pattern as a mask, and etching the exposed silicon substrate to form a trench It provides a separation method of a semiconductor device comprising a step.
Description
본 발명은 반도체소자의 분리방법에 관한 것으로, 특히 비정질실리콘을 광흡수막으로 이용하는 소자분리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for separating semiconductor devices, and more particularly to a device separation method using amorphous silicon as a light absorption film.
반도체 제조공정에서는 고집적화의 요구가 증가됨에 따라 최소 선폭이 점차줄어들고 있으며, 이에 맞추어 노광공정에서 사용하는 노광파장도 또한 점차 짧아져서 최소선폭 0.2㎛을 형성하기 위해서 248nm파장을 갖는 KrF 엑시머레이저(excimer laser)를 광원으로 이용하고 있다.In the semiconductor manufacturing process, as the demand for high integration increases, the minimum line width is gradually decreasing. Accordingly, the exposure wavelength used in the exposure process is also gradually shortened so that the KrF excimer laser having a 248 nm wavelength to form a minimum line width of 0.2 μm is used. ) Is used as the light source.
현재, LOCOS(Local Oxidation of Silicon)혹은 STI(Shallow Trench Isolation)공정을 사용하는 소자분리(lsolation)기술에서, 능동소자가 형성될 부분은 열산화를 방지하기 위하여 패드질화막/산화막의 적층구조를 사용하고 있다. 소자분리공정은 패턴이 없는 실리콘 웨이퍼상에 처음 진행하는 단계로서 실리콘과 질화막 사이의 스트레스를 조절하기 위한 패드산화막을 수십 Å증착하고 이위에 수백 Å이상의 질화막을 CVD법으로 증착한다. 증착된 질화막과 산화막의 두께는 웨이퍼 내에서 수십∼수백Å의 두께 차이를 갖는데, 248nm이하의 단파장을 이용한 노광공정에서는 이러한 두께차이가 감광막으로 재반사되는 반사광의 세기 차이를 유발시켜, 현상되는 감광막 패턴 크기 변화가 생기게 한다. 이렇게 되면, 질화막/산화막 두께 차이에 의해 웨이퍼상 각각 다른 크기의 능동 소자 영역이 형성되어 소자 신뢰성이 저하되기 때문에, 일정한 능동소자영역을 형성하기 위해서는 노광 빛을 조절할 수 있는 박막이 감광막과 패드 질화막 사이에 필요하게 된다. 반도체 공정에서 노광 빛을 조절할 수 있는 물질로는 실리콘 산질화막을 들 수 있는데, 248nm에서의 굴절율과 흡수율은 그 조성에 따라 굴절율과 흡수율이 달라지는데 각각 1.7∼2.1과 0.1∼1.5의 범위내에서 다결정 실리콘이나 금속성 배선물질 위에 반사저지막으로 사용하고 있다. 또한, 실리콘 산질화막은 소자분리공정에서의 균일한 감광막 패턴을 형성하기 위한 광흡수막으로 이용하여 어느 정도 반사율 변화를 감소시키지만, 이 경우 두께가 300Å이상 1000Å정도 두꺼워야 한다. 또한 소자분리 패턴형성 및 건식식각후, 건식식각에 노출되어 손상된 수십 Å정도의 실리콘 벽면 및 바닥 표면 보상 및 제거공정을 진행하고 소자분리산화막을 열산화막 공정 혹은 고밀도 플라즈마 CVD를 이용한 산화막 증착등으로 채우게 된다. 이러한 고온 열공정을 통하여 산질화막의 조성이 바뀌고 물성이 변성되기 때문에, 패드질화막을 제거하기 전에 질화막 위에 남아 있는 실리콘 산질화막을 건식이나 BOE(Buffered Oxide Etchant)혹은 인산을 사용한 습식식각에 제거하기가 용이하지 않아 효과적인 소자분리에 지장을 주고 있다.Currently, in device isolation technology using LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) process, the part where active device is to be formed uses a stack structure of pad nitride film / oxide film to prevent thermal oxidation. Doing. The device isolation process is the first step on a silicon wafer without a pattern, and a dozens of pad oxide films are deposited to control the stress between the silicon and nitride films, and several hundreds or more of nitride films are deposited by CVD. The thicknesses of the deposited nitride film and the oxide film have a thickness difference of several tens to several hundred micrometers in the wafer. In an exposure process using a short wavelength of 248 nm or less, such a thickness difference causes a difference in intensity of reflected light reflected back to the photosensitive film. This causes a pattern size change. In this case, active device regions of different sizes are formed on the wafer due to the difference in the thickness of the nitride film and the oxide film, so that the reliability of the device is lowered. It is necessary. Silicon oxynitride film is a material that can control the exposure light in the semiconductor process. The refractive index and the absorbance at 248 nm vary depending on the composition of the polycrystalline silicon in the range of 1.7 to 2.1 and 0.1 to 1.5, respectively. It is also used as a reflection blocking film on metallic wiring materials. In addition, the silicon oxynitride film is used as a light absorption film for forming a uniform photoresist pattern in the device isolation process to reduce the change in reflectance to some extent, but in this case, the thickness should be at least 300 GPa and 1000 GPa. In addition, after the isolation pattern formation and dry etching, the process of compensating and removing dozens of silicon wall and bottom surface damaged by exposure to dry etching is performed and the device isolation oxide is filled by thermal oxide process or oxide deposition using high density plasma CVD. do. Since the composition of the oxynitride film is changed and the physical properties are modified through the high temperature thermal process, it is difficult to remove the silicon oxynitride film remaining on the nitride film by dry or wet etching using BOE or phosphoric acid before removing the pad nitride film. As it is not easy, it interferes with effective device separation.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 비정질실리콘을 광흡수막으로 이용하여 트렌치 소자분리를 행함으로써 비정질실리콘의 높은 광흡수율 특성에 의해 하부 기판의 미세한 두께변화와 무관하게 균일한 패턴을 얻어 웨이퍼상의 모든 소자가 균일한 특성을 가질 수 있도록 하는 반도체소자의 분리방법을 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and by using trench isolation using amorphous silicon as a light absorption film, a uniform pattern is obtained regardless of the minute thickness change of the lower substrate by the high light absorption characteristic of amorphous silicon. It is an object of the present invention to provide a method of separating a semiconductor device such that all devices on the wafer can have uniform characteristics.
도 1은 하부실리콘질화막이 두께변화에 의한 감광막의 반사도 변화를 나타낸 그래프,1 is a graph showing a change in reflectivity of the photoresist film due to the thickness change of the lower silicon nitride film;
도 2a 내지 도 2i는 본 발명에 의한 반도체소자의 분리방법을 도시한 공정순서도.2A to 2I are process flowcharts showing a method of separating a semiconductor device according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11.패드산화막 12.패드질화막11.Pad oxide film 12.Pad nitride film
13.비정질실리콘막 14.감광막패턴13.Amorphous silicon film 14.Photoresist pattern
15.마스크 16.산화된 비정질실리콘막15.Mask 16.Oxidized Amorphous Silicon Film
17.희생 산화막 18.실리콘산화막17.Sacrifice oxide 18.Silicone oxide
상기 목적을 달성하기 위한 본 발명의 반도체소자 분리방법은 실리콘기판상에 패드산화막, 패드질화막을 차례로 형성하는 단계, 상기 패드질화막상에 비정질실리콘막을 50Å∼300Å의 두께로 형성하는 단계, 상기 비정질실리콘막상에 소정의감광막패턴을 형성하는 단계, 상기 감광막패턴을 마스크로 이용하여 상기 비정질실리콘막, 상기 패드질화막 및 상기 패드산화막을 식각하여 상기 실리콘기판의 소자분리영역을 노출시키는 단계, 및 상기 노출된 실리콘기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계를 포함함을 특징으로 한다.The semiconductor device separation method of the present invention for achieving the above object is a step of sequentially forming a pad oxide film, a pad nitride film on a silicon substrate, forming an amorphous silicon film to a thickness of 50 ~ 300 두께 on the pad nitride film, the amorphous silicon Forming a predetermined photoresist pattern on a film, etching the amorphous silicon film, the pad nitride film, and the pad oxide film using the photoresist pattern as a mask to expose a device isolation region of the silicon substrate; and And etching the silicon substrate to a predetermined depth to form a trench.
본 발명에서는 STI소자분리공정에서 광흡수막을 노광빛에 대한 높은 흡수계수를 갖는 비정질 실리콘으로 형성함으로써 하부 실리콘 질화막의 두께의 변화에 무관하게 일정한 반사율을 나타나어 패턴 형성을 균일하게 하며, 기존 광흡수율(K)이 0.5∼1.0인 실리콘 산질화막을 광흡수 박막으로 사용한 경우 두께가 300Å∼1000Å이상을 사용해왔던 것과는 달리 50∼300Å의 얇은 두께로 균일한 크기의 감광막 패턴 형성할 수 있다. 도 1에 광흡수막(비정질실리콘, 산질화막)을 사용한 경우와 사용하지 않은 경우, 패드 질화막 두께에 따라 감광막으로 재반사되는 노광빛의 반사율을 보여준다. 패드 질화막과 감광막 사이에 실리콘 산질화막을 사용한 경우와 비정질실리콘을 사용한 경우의 두 개의 곡선이 보여지는데, 질화막 두께에 따라 반사율 변화가 적은 것이 균일한 패턴을 형성시킨다.In the present invention, in the STI device separation process, the light absorption film is formed of amorphous silicon having a high absorption coefficient for exposure light, thereby exhibiting a constant reflectance irrespective of the change in the thickness of the lower silicon nitride film, thereby making the pattern formation uniform, and providing an existing light absorption rate. In the case where the silicon oxynitride film having a (K) of 0.5 to 1.0 is used as the light absorption thin film, a photoresist pattern having a uniform size can be formed with a thin thickness of 50 to 300 kW, unlike the case where the thickness is 300 to 1000 mW or more. FIG. 1 shows the reflectance of the exposure light that is reflected back to the photosensitive film depending on the thickness of the pad nitride film when the light absorbing film (amorphous silicon, oxynitride film) is used or not. Two curves are shown between the pad nitride film and the photoresist film when the silicon oxynitride film is used and when the amorphous silicon is used. A small reflectance change according to the thickness of the nitride film forms a uniform pattern.
이러한 감광막 패턴을 이용하여 패드 질화막/산화막을 건식식각하고 난 다음 감광막을 제거하여 비정질실리콘층이 드러난 상태에서 실리콘 트렌치 식각을 수행하게 되면 비정질실리콘과 결정성 실리콘 기판은 같은 실리콘 물성을 갖고 있기 때문에 수천 Å의 실리콘 기판이 식각되는 동안 질화막 위에 존재하는 비정질실리콘층을 완전히 제거할 수 있다. 또한, 실리콘 트렌치 식각시 감광막이 계속 남아 있어 실리콘 트렌치 패턴 식각 후 질화막 위에 비정질실리콘층이 남아 있다 하더라도, 고온 (≥1000℃) 열산화(Sacrificial Oxidation)공정에 의해 건식 식각시 손상되었던 실리콘 벽면 및 바닥 표면을 보상 및 제거해 주는데, 이때 광흡수막으로 사용된 비정질 실리콘막 또한 산화된다. 비정질실리콘의 열산화 속도는 결정성 실리콘의 산화속도와 비슷하거나 약간 빠르므로, 남아있던 300Å이하의 얇은 비정질실리콘층의 물성은 충분히 산화막으로 전환되어 후속 APCVD 혹은 고밀도 플라즈마(High Density Plasma)CVD법으로 증착된 산화막과 비슷한 산화된 비정질층은 BOE 혹은 HF처리할 때 완전히 제거되어 패드 질화막의 인산 습식 식각시의 장애물이 없어지게 된다. 소자 분리 공정에서 비정질실리콘층을 광흡수막으로 사용하게 되면, 실리콘 단일 조성 막이므로 MOS트랜지스터에서 오동작을 유발하는 불순물의 유입이 없으며, 기존 실리콘 산질화막을 광흡수막으로 사용하였을 때와는 달리 후속 실리콘 트렌치 식각공정에서 제거되거나 고온 열산화공정에서 산화막으로 바뀌기 때문에 광흡수막을 제거하는 별도의 공정 단계가 필요없게 된다.When the pad nitride film / oxide film is dry-etched using this photoresist pattern and then the photoresist film is removed and the silicon trench is etched while the amorphous silicon layer is exposed, the amorphous silicon and the crystalline silicon substrate have the same silicon properties. While the silicon substrate is etched, it is possible to completely remove the amorphous silicon layer present on the nitride film. In addition, even though the photoresist film remains during the silicon trench etching, even though an amorphous silicon layer remains on the nitride film after the silicon trench pattern etching, the silicon wall and the floor which were damaged during the dry etching by the high temperature (≥1000 ° C) thermal oxidation process The surface is compensated for and removed, wherein the amorphous silicon film used as the light absorption film is also oxidized. Since the thermal oxidation rate of amorphous silicon is similar to or slightly faster than the oxidation rate of crystalline silicon, the remaining physical properties of the thin amorphous silicon layer of 300 Å or less are sufficiently converted to an oxide film, which is then followed by APCVD or High Density Plasma CVD. The oxidized amorphous layer, similar to the deposited oxide layer, is completely removed during BOE or HF treatment, eliminating obstacles in the wet etching of the pad nitride layer. When the amorphous silicon layer is used as the light absorption film in the device isolation process, there is no inflow of impurities causing malfunction in the MOS transistor since it is a single silicon film, and unlike the case where the conventional silicon oxynitride film is used as the light absorption film, The removal of the light absorbing film is unnecessary because the silicon trench is removed in the etching process or converted into an oxide film in the high temperature thermal oxidation process.
본 발명의 일실시예에 따라 256M DRAM급 이상의 반도체소자를 STI공정에 의해 소자 분리하는 방법을 도 2a 내지 도 2f를 참조하여 다음에 설명한다.A method of isolating a semiconductor device of 256 M DRAM or more according to an embodiment of the present invention by an STI process will be described next with reference to FIGS. 2A to 2F.
먼저, 도 2a와 같이 실리콘기판(10)상에 실리콘과 질화막 사이의 응력을 최소화하기 위한 100Å이하의 패드 산화막(11)을 형성하고, 이위에 1000Å이상의 패드 질화막(12)을 증착한다. 일반적으로 패드산화막(11)은 열산화공정으로 형성하고, 패드질화막(12)은 CVD공정으로 형성한다. 패드질화막(12)위에 높은 광흡수계수(K)를 갖는 광흡수막으로 250Å이하의 얇은 두께를 갖는 비정질실리콘막(13)을 증착한다. 비정질실리콘막(13)의 증착은 CVD(Chemical VaporDeposition)이나 PECVD(Plasma-Enhanced CVD)로 진행한다. CVD로 비정질실리콘막을 증착하는 경우, 후속 열산화공정에서 산화될 것을 고려하여 가급적이면 얇게 증착하고, PECVD로 증착하는 경우 트렌치 건식식각공정에서 감광막 대신 하드마스크(hard mask)역할을 하는 것을 고려할 때 증착 두께는 하부의 질화막으로 노광빛이 투과하지 못하는 50∼500Å정도로 한다. 본 실시예에서는 PECVD로 비정질실리콘막을 증착하는 방법을 기술한다. 비정질실리콘막(13)을 증착하기 이전에 하부막 표면에 존재하는 불순물 제거 및 하부막과의 점착력을 높히기 위하여 S2SO4등을 이용한 습식식각이나 Ar(혹은 He, H2등)등의 불활성가스 또는 수소플라즈마를 이용한 인시튜(in-situ)표면 처리과정을 거친다. 이때, 가스 유량은 10-30000sccm, 처리온도는 상온 ∼600℃의 범위에서 진행하며, 반응실의 압력은 0.01-10Torr, 사용전력을 0-10000W로 한다. 비정질실리콘 증착시와 동일한 챔버를 사용하는 경우에는 비정질실리콘 증착온도와 같은 온도에서 공정을 진행한다.First, as shown in FIG. 2A, a pad oxide film 11 of 100 kPa or less is formed on the silicon substrate 10 to minimize stress between silicon and the nitride film, and a pad nitride film 12 of 1000 kPa or more is deposited thereon. In general, the pad oxide film 11 is formed by a thermal oxidation process, and the pad nitride film 12 is formed by a CVD process. An amorphous silicon film 13 having a thin thickness of 250 mW or less is deposited on the pad nitride film 12 as a light absorption film having a high light absorption coefficient K. The deposition of the amorphous silicon film 13 proceeds by chemical vapor deposition (CVD) or plasma-enhanced CVD (PECVD). When depositing the amorphous silicon film by CVD, it is deposited as thin as possible in consideration of being oxidized in the subsequent thermal oxidation process, and when considering the hard mask role instead of the photoresist film in the trench dry etching process by PECVD. The thickness is about 50 to 500 kPa, in which exposure light cannot penetrate the lower nitride film. In this embodiment, a method of depositing an amorphous silicon film by PECVD is described. Wet etching using S 2 SO 4 or inertness such as Ar (or He, H 2, etc.) to remove impurities existing on the surface of the lower layer and increase adhesion to the lower layer before depositing the amorphous silicon layer 13. In-situ surface treatment using gas or hydrogen plasma is performed. At this time, the gas flow rate is 10-30000sccm, the processing temperature is in the range of room temperature ~ 600 ℃, the pressure of the reaction chamber is 0.01-10Torr, the power consumption is 0-10000W. In the case of using the same chamber as in amorphous silicon deposition, the process is performed at the same temperature as the amorphous silicon deposition temperature.
비정질실리콘 증착시 SiH4나 Si2H6등을 실리콘원 기체로 사용하고, 경우에 따라서 두께균일도를 향상시키거나 증착속도를 감소시키기 위하여 Ar기체 혹은 He기체, 수소기체를 희석시키며, 고주파 전력은 0∼10000w, 증착 입력은 0.01∼10Torr, 기판온도는 상온 ∼600℃의 범위에서 증착공정을 행한다. 플라즈마 발생용 주파수는 13.56MHz를 사용한다 증착 조건에 따라 실리콘의 비정질화가 좌우되며, 이에 따라 노광 파장(본 발명의 예는 248nm)에서의 굴절율이 바뀌게 된다.In case of amorphous silicon deposition, SiH 4 or Si 2 H 6 is used as the silicon source gas, and in order to improve the thickness uniformity or to reduce the deposition rate, dilute Ar gas, He gas, and hydrogen gas. The deposition process is performed in the range of 0 to 10000 watts, deposition input of 0.01 to 10 Torr, and substrate temperature of room temperature to 600 占 폚. The plasma generation frequency is 13.56 MHz. The amorphous condition of the silicon depends on the deposition conditions, and thus the refractive index at the exposure wavelength (the example of the present invention is 248 nm) is changed.
다음에 도 2b와 같이 DUV감광막을 비정질실리콘막(13)상에 도포한 후, 마스크(15)를 이용한 DUV(Deep Ultraviolet)(248nm) 노광공정을 행하여 도 2c와 같이 소자분리를 위한 감광막 패턴(14)을 형성한다. 노광공정에서는 DUV 감광막이 광흡수가 어느 정도 있기 때문에 감광막 두께가 얇을수록 0.2㎛이하의 작은 선폭 패터닝이 잘된다. 따라서 상기 감광막은 5000Å이하로 형성하는 것이 바람직하다.Next, as shown in FIG. 2B, the DUV photoresist film is applied onto the amorphous silicon film 13, and then a DUV (Deep Ultraviolet) (248 nm) exposure process using the mask 15 is performed. 14). In the exposure process, since the DUV photoresist film has a certain degree of light absorption, the thinner the photoresist film thickness, the smaller the line width pattern of 0.2 µm or less. Therefore, it is preferable to form the photosensitive film below 5000 kPa.
이어서 도 2d에 나타낸 바와 같이 상기 감광막 패턴(14)을 마스크로 이용하여 패드질화막(12)상부의 얇은 비정질실리콘막(13)을 반응성 플라즈마 건식 식각가스(Cl2+Ar) 혹은 Ar(He)등과 같은 불활성가스를 이용한 비반응성 플라즈마를 이용한 물리적 건식 식각방법에 의해 선택적으로 제거하고, 계속해서 패드질화막(12) 및 패드산화막(11)을 식각한다.Subsequently, as shown in FIG. 2D, the thin amorphous silicon film 13 on the pad nitride film 12 is formed with a reactive plasma dry etching gas (Cl 2 + Ar) or Ar (He) using the photosensitive film pattern 14 as a mask. The pad nitride film 12 and the pad oxide film 11 are then selectively removed by a physical dry etching method using a non-reactive plasma using the same inert gas.
다음에 도 2e와 같이 실리콘기판(10)에 깊이 2000Å이상의 트렌치를 형성하기 위해서 실리콘 건식식각가스인 Cl2혹은 Cl2+Ar등으로 실리콘 기판을 식각해 낸다. 실리콘 트렌치 식각시에는 상기 감광막패턴(14)을 식각장벽으로 사용할 수도 있고, 광흡수막으로 이용된 비정질실리콘막(13)을 트렌치 식각시 함께 제거하기 위하여 감광막패턴(14)을 제거한 후, 비정질실리콘막(13)을 식각장벽으로 사용하여 트렌치 식각을 행할 수도 있다.Next, as shown in FIG. 2E, the silicon substrate is etched with Cl 2 or Cl 2 + Ar, which is a silicon dry etching gas, in order to form a trench having a depth of 2000 μm or more in the silicon substrate 10. When the silicon trench is etched, the photoresist pattern 14 may be used as an etch barrier, and after removing the photoresist pattern 14 to remove the amorphous silicon layer 13 used as the light absorption layer during the trench etching, the amorphous silicon is removed. Trench etching may be performed using the film 13 as an etching barrier.
이어서 도 2f와 같이 트렌치 식각시 활성화된 이온들에 의해 손상된 단결정 실리콘 벽면 및 바닥표면을 보상하기 위해 O2혹은 O2+H2O를 반응가스로 한 희생 산화막(Sacrificial Oxidation)(17)을 약 150Å씩 2회 이상 형성 및 제거시키는 공정을 진행한다. 이러한 열산화 공정은 위와 같이 실리콘 단결정 표면에 존재하는 결점등을 제거하기도 하지만, 실리콘 식각시 생긴 각진 모서리 부분을 둥굴게 만들어, 완성된 MOS소자에 전기를 인가할 때 트렌치의 모난 부분에 전계(Electrical Field)가 집중되는 문제를 완화할 수 있기 때문에 STI공정에서는 필수적인 공정이다. 실리콘기판(10)의 트렌치 식각 후 광흡수막으로 사용된 비정질실리콘막(13)이 남아 있는 경우에는 비정질실리콘막(13)이 상기 열산화공정이 진행되는 동안 산화되어 산화된 비정질실리콘막(16)으로 변성되게 된다. 따라서 트렌치 매립을 위해 후속공정에서 증착될 고밀도 프라스마 CVD에 의한 실리콘산화막과 같은 물리적 화학적 특성을 가져 BOE공정이나 CMP공정시 쉽게 제거되게 된다. 이와 같이 트렌치표면 보상을 위한 열산화공정시 남아 있는 비정질실리콘막(13)이 완전히 산화막으로 변화하도록 하기 위해 트렌치 실리콘이 산화되는 두께보다 비정질실리콘막(13)의 증착두께를 얇게 형성하는 것이 중요하다.Subsequently, a sacrificial oxide (17) using O 2 or O 2 + H 2 O as a reaction gas was used to compensate for the single crystal silicon wall and the bottom surface damaged by the ions activated during the trench etching as shown in FIG. 2F. The process of forming and removing two or more times is carried out. This thermal oxidation process removes defects on the surface of the silicon single crystal as described above, but rounds off the corners of the silicon etched surface, which is applied to the angular portion of the trench when electricity is applied to the finished MOS device. This is an essential process in the STI process because it can alleviate the problem of concentrated field. In the case where the amorphous silicon film 13 used as the light absorption film remains after the trench etching of the silicon substrate 10, the amorphous silicon film 13 is oxidized and oxidized during the thermal oxidation process. ) Will be denatured. Therefore, it has physical and chemical properties such as silicon oxide film by high density plasma CVD to be deposited in a subsequent process for trench filling and is easily removed during BOE process or CMP process. As such, in order to completely change the amorphous silicon film 13 remaining in the thermal oxidation process for the trench surface compensation, it is important to form a thinner deposition thickness of the amorphous silicon film 13 than the thickness of the trench silicon is oxidized. .
다음에 도 2g에 나타낸 바와 같이 O3-TEOS USG(Undoped Slica Glass) 혹은 고밀도 플라즈마 CVD에 의한 산화막(18)을 기판 전면에 형성하여 상기 형성된 실리콘 트렌치를 보이드(void)없이 매립한다.Next, as shown in FIG. 2G, an oxide film 18 formed by O 3 -TEOS USG (Undoped Slica Glass) or high-density plasma CVD is formed on the entire surface of the substrate to fill the formed silicon trench without voids.
이어서 도 2h와 같이 패드질화막(12)위에 증착된 산화막(18)을 패드질화막(12)이 노출될때까지 CMP공정으로 연마하여 제거한다. 산화된 비정질실리콘막(16), 즉 실리콘산화막은 고밀도 플라즈마로 증착된 실리콘계 산화막(18)과 유사한 속도로 연마할 수 있다. CMP공정이 끝난 후 CMP연마 불균일도에 의해 도 2i와 같이 패드질화막(12)위에 산화된 비정질실리콘막(16)이 남아 있는 경우에는 패드질화막(12) 바로 위까지 습식식각으로 남아 있는 산화막을 제거할 수 있다.Subsequently, as illustrated in FIG. 2H, the oxide film 18 deposited on the pad nitride film 12 is removed by polishing by a CMP process until the pad nitride film 12 is exposed. The oxidized amorphous silicon film 16, i.e., the silicon oxide film, can be polished at a similar speed as the silicon-based oxide film 18 deposited by the high density plasma. After the CMP process is finished, when the amorphous silicon film 16 oxidized on the pad nitride film 12 remains due to the CMP polishing nonuniformity, the oxide film remaining by wet etching to the pad nitride film 12 is removed. can do.
기존의 반사저지용 박막으로 널리 알려진 실리콘 산질화막을 본 발명의 비정질실리콘 대신에 STI공정에 사용하는 경우, 실리콘 산질화막의 조성상 산화막, 질화막, 무정형 실리콘의 중간 특성을 갖고 있기 때문에 실리콘 산질화막으로 트렌치를 채우게 되면 도 2g와 같이 패드질화막(12)위에 산화막과 산질화막의 두 층이 남게 되므로, BOE등과 같은 산화막 습식 식각 후 산질화막을 제거하는 공정을 거쳐야 인산에서 질화막을 제거할 수 있다. 그러나, BOE에서의 산화막과 산질화막 사이의 식각 선택비, 인산에서의 산질화막과 패드질화막 사이의 식각선택비가 모호해서 각각의 습식 식각 시간을 설정하는데 어려움이 많았다.In the case of using the silicon oxynitride film, which is widely known as a thin film for reflection blocking, in the STI process instead of the amorphous silicon of the present invention, since the silicon oxynitride film has an intermediate characteristic of an oxide film, a nitride film, and an amorphous silicon, it is a trench as a silicon oxynitride film. When the N is filled, two layers of an oxide film and an oxynitride film are left on the pad nitride film 12 as shown in FIG. 2G. Thus, the nitride film may be removed from phosphoric acid only after the wet etching of the oxide film such as BOE is performed. However, the etch selectivity between the oxide film and the oxynitride film in the BOE and the etch selectivity between the oxynitride film and the pad nitride film in phosphoric acid are ambiguous, which makes it difficult to set the respective wet etching times.
그러나 STI소자 분리공정중 본 발명에서 광흡수막으로 제안하는 비정질실리콘의 경우에는, 광흡수막으로 한 층의 박막이 DUV감광막과 패드질화막 사이에 삽입되었지만, 박막의 두께가 얇아 0.2㎛이하의 최소 선폭을 갖는 실리콘 트렌치 식각시의 애스펙트비(aspect ratio)를 줄일수 있고, 패턴 노광공정 이후 패드질화막 제거공정 사이 각 공정의 정확한 조절로 광흡수 박막을 제거하는 추가 공정없이 안정적인 소자 분리를 할수 있게 된다.However, in the case of the amorphous silicon proposed by the present invention as the light absorbing film during the STI device separation process, a thin film of the light absorbing film was inserted between the DUV photosensitive film and the pad nitride film. The aspect ratio of the silicon trench with the line width can be reduced, and the device can be stably separated without the additional process of removing the light absorbing thin film by precise control of each process between the pad nitride film removal process after the pattern exposure process. .
본 발명은 LOCOS를 이용한 소자분리공정에도 적용이 가능하다. 이 경우에는 실리콘기판상에 패드산화막과 패드질화막, 비정질실리콘층을 차례로 형성한 후, 이 위에 소자분리영역 패터닝을 위한 감광막패턴을 형성하고, 이 감광막패턴을 마스크로 하여 비정질실리콘층과 패드질화막 및 패드산화막을 식각하여 소자분리영역을 정의한다. 이어서 감광막패턴과 비정질실리콘층을 제거한 후, 필드산화공정을 행하여 소자분리막을 형성한다. 이때, 비정질실리콘층을 제거하지 않은채 필드산화공정을 진행하여 필드산화공정시 비정질실리콘층도 함께 산화되도록 한 후, BOE나 HF등의 산화막 식각용액으로 패드질화막위에 존재하는 산화된 비정질실리콘을 제거할 수도 있다.The present invention can be applied to a device isolation process using LOCOS. In this case, a pad oxide film, a pad nitride film, and an amorphous silicon layer are sequentially formed on a silicon substrate, and then a photoresist pattern for patterning device isolation regions is formed thereon, and the amorphous silicon layer and the pad nitride film are formed using the photoresist pattern as a mask. The device oxide is defined by etching the pad oxide film. Subsequently, after removing the photoresist pattern and the amorphous silicon layer, a field oxidation process is performed to form an element isolation film. At this time, the field oxidation process is performed without removing the amorphous silicon layer so that the amorphous silicon layer is also oxidized during the field oxidation process, and then the oxidized amorphous silicon present on the pad nitride layer is removed with an oxide etching solution such as BOE or HF. You may.
본 발명에서는 패드질화막상에 비정질실리콘을 광흡수막으로 사용한다. 이에 따라 비정질실리콘의 높은 광흡수율 특성에 의해 250Å이하의 얇은 두께로 하부 기판의 미세한 두께변화와 무관하게 균일한 패턴을 얻을 수 있어 웨이퍼상에 제작된 모든 소자가 균일한 특성을 가질 수 있게 된다. 또한, 노광공정을 위해 삽입된 비정질실리콘 광흡수막은 두께가 얇기 때문에, 트렌치 식각시 제거되거나, 식각공정시 손상된 실리콘 벽면 및 바닥의 표면 보상을 위한 산화공정시 자체적으로 산화되어 후속 고밀도 프라스마 CVD를 이용하여 증착된 실리콘 산화막과 같은 물리적 화학적 특성을 가져 BOE공정이나 CMP공정시 쉽게 제거되므로 별도의 제거 공정이 필요없게 된다.In the present invention, amorphous silicon is used as the light absorption film on the pad nitride film. Accordingly, the high light absorption characteristic of the amorphous silicon allows a uniform pattern to be obtained regardless of the small thickness variation of the lower substrate with a thin thickness of 250 Å or less, so that all devices fabricated on the wafer can have uniform characteristics. In addition, since the amorphous silicon light absorbing film inserted for the exposure process is thin, it is removed during the trench etching, or oxidized itself during the oxidation process to compensate for the damaged silicon wall and the bottom surface during the etching process, thereby performing subsequent high density plasma CVD. It has the same physical and chemical properties as the silicon oxide film deposited using it, so it is easily removed during the BOE process or the CMP process, so there is no need for a separate removal process.
Claims (21)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980042792A KR100318461B1 (en) | 1998-10-13 | 1998-10-13 | Semiconductor device isolation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980042792A KR100318461B1 (en) | 1998-10-13 | 1998-10-13 | Semiconductor device isolation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000025635A KR20000025635A (en) | 2000-05-06 |
| KR100318461B1 true KR100318461B1 (en) | 2002-02-19 |
Family
ID=19553893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980042792A KR100318461B1 (en) | 1998-10-13 | 1998-10-13 | Semiconductor device isolation method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100318461B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100733693B1 (en) * | 2001-12-29 | 2007-06-28 | 매그나칩 반도체 유한회사 | Device Separator Formation Method of Semiconductor Device |
| US12188583B2 (en) | 2019-04-15 | 2025-01-07 | Toshiba Energy Systems & Solutions Corporation | Charged particle accelerator and method for building charged particle accelerator |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100634267B1 (en) * | 2000-09-20 | 2006-10-16 | 삼성전자주식회사 | Method of forming device isolation region in semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62285442A (en) * | 1986-06-03 | 1987-12-11 | Fujitsu Ltd | Manufacture of semiconductor device |
| US5192706A (en) * | 1990-08-30 | 1993-03-09 | Texas Instruments Incorporated | Method for semiconductor isolation |
| JPH0883795A (en) * | 1994-07-13 | 1996-03-26 | Nippon Telegr & Teleph Corp <Ntt> | Method for forming element isolation region |
| KR970077481A (en) * | 1996-05-07 | 1997-12-12 | 양승택 | Method for isolating local oxide film (LOCOS) with multilayer amorphous silicon |
| KR19980077551A (en) * | 1997-04-21 | 1998-11-16 | 김영환 | Device isolation insulating film formation method of semiconductor device |
| KR19980084300A (en) * | 1997-05-22 | 1998-12-05 | 윤종용 | Device isolation film formation method using a reflection suppression film |
-
1998
- 1998-10-13 KR KR1019980042792A patent/KR100318461B1/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62285442A (en) * | 1986-06-03 | 1987-12-11 | Fujitsu Ltd | Manufacture of semiconductor device |
| US5192706A (en) * | 1990-08-30 | 1993-03-09 | Texas Instruments Incorporated | Method for semiconductor isolation |
| JPH0883795A (en) * | 1994-07-13 | 1996-03-26 | Nippon Telegr & Teleph Corp <Ntt> | Method for forming element isolation region |
| KR970077481A (en) * | 1996-05-07 | 1997-12-12 | 양승택 | Method for isolating local oxide film (LOCOS) with multilayer amorphous silicon |
| KR19980077551A (en) * | 1997-04-21 | 1998-11-16 | 김영환 | Device isolation insulating film formation method of semiconductor device |
| KR19980084300A (en) * | 1997-05-22 | 1998-12-05 | 윤종용 | Device isolation film formation method using a reflection suppression film |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100733693B1 (en) * | 2001-12-29 | 2007-06-28 | 매그나칩 반도체 유한회사 | Device Separator Formation Method of Semiconductor Device |
| US12188583B2 (en) | 2019-04-15 | 2025-01-07 | Toshiba Energy Systems & Solutions Corporation | Charged particle accelerator and method for building charged particle accelerator |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000025635A (en) | 2000-05-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6174590B1 (en) | Isolation using an antireflective coating | |
| US7125783B2 (en) | Dielectric anti-reflective coating surface treatment to prevent defect generation in associated wet clean | |
| US7368390B2 (en) | Photolithographic patterning process using a carbon hard mask layer of diamond-like hardness produced by a plasma-enhanced deposition process | |
| US6784094B2 (en) | Anti-reflective coatings and methods for forming and using same | |
| US5488246A (en) | Semiconductor device and method of manufacturing the same | |
| KR20040049739A (en) | Method of forming isolation layer for semiconductor device | |
| KR20060130680A (en) | How to form trench isolation regions | |
| US6444588B1 (en) | Anti-reflective coatings and methods regarding same | |
| US20210180183A1 (en) | Atomic layer deposition on optical structures | |
| TW202109618A (en) | Patterning method for semiconductor devices | |
| US6194286B1 (en) | Method of etching thermally grown oxide substantially selectively relative to deposited oxide | |
| US6509271B1 (en) | Manufacturing method of semiconductor device | |
| US20040175900A1 (en) | Manufacturing method of shallow trench isolation | |
| KR100318461B1 (en) | Semiconductor device isolation method | |
| US6140206A (en) | Method to form shallow trench isolation structures | |
| US20070290292A1 (en) | Use of teos oxides in integrated circuit fabrication processes | |
| KR100301530B1 (en) | Mehtod for forming inter layer insulting film in the semiconductor device | |
| KR100253589B1 (en) | Method of forming fine pattern of semiconductor device | |
| KR100321174B1 (en) | Method of forming isolation layer in semiconductor device | |
| US20050148193A1 (en) | Photolithographic method for forming a structure in a semiconductor substrate | |
| KR100503344B1 (en) | Method for manufacturing a shallow trench isolation layer of the semiconductor device | |
| US7981800B1 (en) | Shallow trench isolation structures and methods for forming the same | |
| US7067390B2 (en) | Method for forming isolation layer of semiconductor device | |
| US6143664A (en) | Method of planarizing a structure having an interpoly layer | |
| KR19990000067A (en) | Method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19981013 |
|
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19990504 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19981013 Comment text: Patent Application |
|
| PG1501 | Laying open of application | ||
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20010329 Patent event code: PE09021S01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20011009 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20011210 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20011211 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20041119 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20051116 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20061122 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20071120 Start annual number: 7 End annual number: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20081125 Start annual number: 8 End annual number: 8 |
|
| PR1001 | Payment of annual fee |
Payment date: 20091126 Start annual number: 9 End annual number: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20101125 Year of fee payment: 10 |
|
| PR1001 | Payment of annual fee |
Payment date: 20101125 Start annual number: 10 End annual number: 10 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |