KR100303448B1 - a liquid crystal display and a manufacturing method thereof - Google Patents

Abstract

In a thin film transistor substrate for a liquid crystal display device having a pixel electrode and a common electrode on a substrate according to the present invention, a gate line is formed on an insulating substrate in a horizontal direction, the data line intersects the gate line in a vertical direction, and The gate lines are insulated from each other by the three-layer film pattern of the gate insulating film and the semiconductor layer and the doped semiconductor layer. A drain electrode is formed in the pixel region surrounded by the gate line and the data line. The drain electrode overlaps the gate line and the three-layer film pattern, and the pixel electrode line extends therefrom. A plurality of parallel pixel electrodes extending from the pixel electrode line are formed in the pixel area, and a plurality of common electrodes are formed so as to be alternately arranged side by side with the pixel electrode. In addition, the protective insulating film, the doped semiconductor layer, the semiconductor layer, and the gate insulating film are removed in the pixel region. As described above, in the present invention, the pixel electrode and the common electrode are formed on the same substrate surface, and all the insulating film components thereon are removed, thereby eliminating the main cause of residual DC components.

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same, and more particularly, to a thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same in which a common electrode and a pixel electrode are formed on one substrate.

In general, a liquid crystal display device has a structure in which a liquid crystal is injected between two substrates, and the amount of light transmitted is controlled by adjusting the intensity of the electric field applied thereto.

In a liquid crystal display device in which both a common electrode and a pixel electrode are formed on a thin film transistor substrate, when a voltage is applied, an electric field is formed in a horizontal direction with respect to the substrate, and the liquid crystal molecules are in a plane parallel to the substrate according to the horizontal electric field. Because of the rotation, the refractive index of the liquid crystal observed macroscopically is smaller than that of other display devices, so that the contrast ratio is improved and the viewing angle is widened. However, since a plurality of opaque common electrodes and pixel electrodes are disposed in the pixel region, the aperture ratio is relatively higher than that of the twisted nematic liquid crystal display device having the common and pixel electrodes transparent to the upper substrate and the lower thin film transistor substrate, respectively. There is a disadvantage of being lowered.

Next, a thin film transistor substrate for a liquid crystal display according to the related art will be described with reference to FIG. 1.

1 is a cross-sectional view schematically illustrating an electrode arrangement in a thin film transistor substrate for a liquid crystal display according to a related art.

As illustrated in FIG. 1, a common electrode 20 to which a common voltage is applied is formed on an insulating substrate 10, and a gate insulating film is formed of a silicon oxide film or a silicon nitride film on the common electrode 20. 30 is formed, and the pixel electrode 40 is formed on the opaque metal on it. In this case, the pixel electrodes 40 are arranged at regular intervals in parallel with the common electrode 20. In addition, a protective insulating film 50 is formed on the pixel electrode 40 by a silicon nitride film (SiNx) or the like.

As described above, in the structure in which the common electrode 20 and the pixel electrode 40 are formed on different layers through the gate insulating film 30, the pixel electrode 20 and the pixel electrode 40 are formed on the same layer. In comparison, a relatively high driving voltage is required to operate the two electrodes 20 and 40. Also, in the structure in which the protective insulating film 50 is covered on the pixel electrode 40, a relatively high driving voltage is required as compared with the structure in which the protective insulating film 50 is not covered.

As a structure for lowering the driving voltage value, a MITSUBISHI paper published in '98 SID shows a structure in which a common electrode and a pixel electrode are formed on the same layer, that is, a protective insulating film, and an insulating film does not exist on the electrode.

Next, referring to the graph of FIG. 2, the relationship between the driving voltage according to the thickness of the protective insulating layer formed on the pixel electrode 40, the distance between the pixel electrode 40 and the common electrode 20, and the aperture ratio will be described below. It demonstrates as follows.

FIG. 2 is a graph schematically showing a relationship between a driving voltage, an electrode gap, and an opening ratio according to a thickness of a silicon nitride film existing on an electrode, wherein the thickness of the silicon nitride film is 900 nm (a), 300 nm (b), and 0, respectively. The case of nm (c) is shown as an example.

As shown in FIG. 2, if the distance d _b between the common electrode 20 and the pixel electrode 40 is the same, the driving voltage V _b required when the thickness of the silicon nitride film is 300 nm (b). Is less than the driving voltage (V _a ) required in the case of 900 nm (a), and the driving voltage (V c) required in the case where the silicon nitride film does not exist ( _c ) is even smaller than this.

On the contrary, when the display device is to be driven using the same driving voltage V _b , the thinner the thickness of the silicon nitride film, the distance between the two electrodes 20 and 40 d _a <d _b <d _c. ) Can be designed to be wide, and accordingly, a relatively small number of electrodes 20 and 40 can be disposed in one pixel area to drive the display device.

At this time, it can be seen that as the distance between the two electrodes 20 and 40 increases, the aperture ratio A / R increases closer to linear. As a result, the light transmittance is increased.

In addition, as the thickness of the protective insulating layer decreases, the amount of light absorbed by the protective insulating layer decreases, so that the light transmittance tends to increase. In addition, as the thickness of the protective insulating film decreases, a direct current (DC) component remaining in the protective insulating film decreases, and thus, an afterimage problem tends to decrease.

On the other hand, the thin film transistor substrate for a conventional liquid crystal display device is generally formed using six masks. That is, a mask is required in each of the steps of forming the gate wiring and the common wiring, the semiconductor pattern, the source and drain electrodes, the data lines and the pixel electrodes, the contact hole formation, and the protective insulating film. Therefore, the number of masks is large and the manufacturing process is complicated.

An object of the present invention is to provide a thin film transistor substrate for a liquid crystal display device in which the aperture ratio is improved.

Another object of the present invention is to provide a thin film transistor substrate for a liquid crystal display device in which a DC component is reduced to remove afterimages.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate for a liquid crystal display device, in which the number of masks is reduced and the process is simplified.

1 is a cross-sectional view showing an electrode arrangement of a thin film transistor substrate for a liquid crystal display according to the related art.

2 is a graph schematically showing a relationship between a driving voltage, an electrode gap, and an opening ratio according to a thickness of an insulating layer existing on an electrode;

3 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3,

FIG. 5 is a cross-sectional view taken along line VV ′ of FIG. 3.

FIG. 6 is a cross-sectional view taken along line VI-VI ′ of FIG. 3;

7A to 9D are plan views and cross-sectional views illustrating a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention in a process sequence.

In order to solve this problem, in the present invention, the pixel electrode and the common electrode are formed on the surface of the insulating substrate, and the gate insulating film and the protective insulating film are removed on the two electrodes.

In the thin film transistor substrate for a liquid crystal display according to the embodiment of the present invention, a plurality of gate lines and data lines are formed on the insulating substrate in the horizontal and vertical directions, respectively, and these are the three-layer film patterns of the gate insulating film, the semiconductor layer, and the doped semiconductor layer. Insulated by and intersecting. A drain electrode overlaps the gate line via a three-layer film pattern, and a plurality of pixel electrodes extend from the drain electrode, and the pixel electrodes are parallel to each other on the substrate surface in the pixel region where the data line and the gate line cross each other. Formed. In addition, a plurality of common electrodes are formed on the substrate surface in the pixel region so as to be alternately arranged in parallel with the pixel electrode.

Here, the protective insulating film may cover the data line, the channel portion from the data line to the drain electrode, and the drain electrode, and in this case, the protective insulating film is preferably removed from the common electrode and the pixel electrode inside the pixel region.

In addition, the data line, the drain electrode, and the pixel electrode may be formed as a double layer structure of the lower chromium layer and the upper aluminum alloy layer, and the gate line and the common electrode may also be formed as a double layer structure of the lower metal layer and the upper aluminum layer. have. At this time, it is preferable that the upper aluminum film of the common electrode and the upper aluminum alloy film of the pixel electrode are removed in the pixel region.

In the method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, a first metal film is deposited on an insulating substrate, and patterned to form first wirings such as a gate line and a plurality of common electrodes, and then a gate thereon. A three-layer film of an insulating film, a semiconductor layer, and a doped semiconductor layer is deposited. Thereafter, the third layer is patterned to form a first three layer pattern to surround the gate line and the common electrode, a second metal layer is deposited thereon, and then patterned to form a second layer including a data line, a drain electrode, and a plurality of pixel electrodes. Form the wiring. Next, the doped semiconductor layer exposed out of the second wiring is removed. A protective insulating film is deposited thereon, and the protective insulating film of the remaining portions except the upper portion of the channel portion and the drain electrode between the data line and the data line and the drain electrode is etched and removed.

When etching the protective insulating film, it is preferable to remove the semiconductor layer and the gate insulating film on the common electrode.

The first metal layer may be formed as a double layer by continuously depositing a lower metal layer and an upper aluminum layer, and the second metal layer may be formed as a double layer by continuously depositing a lower metal layer and an aluminum alloy layer. The aluminum film and the upper aluminum alloy film of the pixel electrode are preferably removed.

In addition, the first metal layer and the second metal layer may be patterned, respectively, to form a gate pad and a data pad respectively connected to the ends of the gate line and the data line. In this case, after forming the second three-layer film pattern on the gate pad and removing the doped semiconductor layer of the second three-layer film pattern after forming the data pad, the protective insulating film, the semiconductor layer of the second three-layer film pattern and the gate insulating film May be etched to form contact holes exposing the gate pad and the data pad, respectively. Thereafter, it is preferable to remove the upper aluminum film of the gate pad and the upper aluminum alloy film of the data pad exposed through the contact hole.

Next, a thin film transistor substrate for a liquid crystal display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art may easily implement the present invention.

First, a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, in which a pixel electrode and a common electrode are formed on one substrate, will be described with reference to FIGS. 3 to 6.

3 is a layout view of a TFT substrate for a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 4 is a cross-sectional view taken along line IV-IV 'of FIG. 3, and FIG. 5 is a cross-sectional view taken along line VV ′ of FIG. 3. 6 is a cross-sectional view taken along line VI-VI ′ of FIG. 3, in which a common electrode and a pixel electrode are formed on an insulating substrate, and a gate insulating film and a protective insulating film over the two electrodes are removed.

3 to 6, the gate wirings 110, 111, 112; 150, 151, and 152 having a double layer structure of a lower aluminum layer Al and an upper chromium layer Cr on the insulating substrate 10. ) And common wirings 120, 121, 122, 130, 131, and 132; 140, 141, and 142 are formed. The gate wirings are formed at the ends of the plurality of gate lines 110, 111, 112, and the gate lines 110, 111, 112 formed in the horizontal direction, and receive gate signals 150, 151, 152. Consists of In addition, the common wiring may include the first common electrode lines 120, 121, and 122 formed on the insulating substrate 10 in parallel with the gate lines 110, 111, and 112 between two adjacent gate lines 110, 111, and 112. A plurality of common electrodes 130, 131, and 132 connecting the second and second common electrode lines 140, 141, and 142, and the first and second common electrode lines 120, 121, 122; 140, 141, and 142 in a vertical direction. Etc.

The gate insulating layer 30 on the gate wirings 110, 111, 112; 150, 151, 152 and the common wirings 120, 121, 122; 130, 131, 132; 140, 141, and 142, respectively. A three-layer film pattern including a semiconductor layer 200 such as an amorphous silicon film and a contact layer 210 such as a doped amorphous silicon film is formed. This three-layer film pattern has a structure covering the edges of the gate wirings 110, 111, 112; 150, 151, 152 and the common wirings 120, 121, 122; 130, 131, 132; 140, 141, and 142. . However, the three-layered film patterns 30, 200, and 210, and the first and second common electrode lines 120 are disposed in each of the plurality of pixel regions partitioned in the row direction between two adjacent gate lines 110 and above some gate lines. , The upper aluminum layers 122 and 142 of the 140, the upper aluminum layer 132 of the common electrode 130, and the upper aluminum layer 132 of the upper portion of the gate line 110 are removed to form a lower portion of the gate line 110. The chromium film 111, the lower chromium films 121 and 141 of the first and second common electrode lines 120 and 140, and the lower chromium film 131 of the common electrodes 130 and 210, and the insulating substrate 10. The face is exposed. In addition, the contact layer 210 is removed from the gate pad 150, and the semiconductor layer 200 and a part of the upper aluminum layer 152 of the gate pad are removed.

In addition, a plurality of data lines 310, 311, and 312 are formed in the vertical direction outside the pixel area, and the three-layer film pattern 20 is formed with the gate line 110 and the first and second common electrode lines 120 and 140. , 200, 210). At the end of each data line 310, data pads 360, 361 and 362 for applying a data signal are formed. Data lines such as data lines 310, 311, and 312 and data pads 360, 361, and 362 are formed of a double layer of lower chromium layers 311 and 361 and upper aluminum-neodymium layers 312 and 362. .

Near the intersection of the data line 310 and the gate line 110, drain electrodes 320, 321, and 322 having a double layer structure of chromium film / aluminum film are formed to face a part of the data line 310. The drain electrode 320 overlaps the gate line 110 via a three-layer film pattern of the gate insulating film 20, the semiconductor layer 200, and the contact layer 210, and the data line 310 and the drain electrode. The contact layer 210 of the portion not covered by the 320 is removed.

The first pixel electrode lines 330, 331, and 332 extend from the drain electrode 320, and overlap the first common electrode lines 120, 121, and 122 through the three layer film patterns 20, 200, and 210. It is. Second pixel electrode lines 350, 351, and 352 are formed on the opposite side of the first pixel electrode lines 330, 331, and 332 to be parallel to the first pixel electrode lines 330, 331, and 332. The second pixel electrode lines 350, 351, and 352 overlap with the second common electrode line 140 through the three layer film patterns 20, 200, and 210. In addition, a plurality of pixel electrodes 340, 341, and 342 connecting the first and second pixel electrode lines 330 and 350 in the vertical direction are formed on the insulating substrate 10 and alternately arranged with the common electrode 130. It is. Here, the first and second pixel electrode lines 330 and 350 and the upper aluminum-neodymium films 332, 352, and 342 of the pixel electrode 340 that are positioned inside the pixel region are removed.

In addition, the protective insulating film 50 is covered with an outer portion of the pixel region surrounded by the gate line 110 and the data line 310. That is, the protective insulating layer 50 is formed in a net shape so as to cover the data line 310, the thin film transistor unit on which the drain electrode 320 is formed, and a boundary portion between two adjacent pixels. 5 and 6, the contact hole C1 exposing the lower chrome film 151 of the gate pad 150 may include the protective insulating film 50, the upper aluminum film 152, and the semiconductor layer 200. ), A contact hole C2 exposing the lower chromium layer 361 of the data pad 360 is formed in the passivation layer 50 and the upper aluminum-neodymium layer 362.

As such, in the thin film transistor substrate for the liquid crystal display according to the exemplary embodiment of the present invention, the pixel electrode 340 and the common electrode 130 are directly formed on the surface of the insulating substrate 10, and the upper gate insulating layer 30 The protective insulating film 50 is all removed. Therefore, the main cause of residual DC component is eliminated, and the afterimage problem is solved.

In addition, as mentioned with reference to the insulating film thickness and the driving relationship of the protective insulating film 50 and the like in FIG. 2, the case where the protective insulating film 50 is not present on the pixel electrode 340 and the common electrode 130 is relative. Since a small driving voltage is required, the gap between the electrodes 130 and 340 can be widened, thereby increasing the aperture ratio.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having such an electrode structure will be described below with reference to FIGS. 7A to 9D.

7A to 9D are plan views and cross-sectional views illustrating a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention in a process sequence.

First, as shown in FIGS. 7A to 7C, the chromium film Cr and the aluminum film Al are deposited at about 500 kPa and 25,000 kPa, respectively, and are etched using a first mask to form gate lines 110, 111, and 112. And gate wirings of the gate pads 150, 151, and 152, the first common electrode lines 120, 121, and 122, the second common electrode lines 140, 141, and 142, and the common electrodes 130, 131, and 132. The common wiring is formed.

Next, as shown in FIGS. 8A to 8C, the silicon nitride film (SiN _x ), the amorphous silicon film (a-si), and the doped amorphous silicon film (n ⁺ a-si) are respectively 500 ns, 2,000 ns, and 4,500. Successive depositions are performed to form three-layer films of the gate insulating film 20, the semiconductor layer 200, and the contact layer 210, and are etched using a second mask to etch the gate wirings 110 and 150 and the common wiring 120. , 130 and 140 to form a three-layer film pattern to cover the edge completely.

Next, as shown in FIGS. 9A to 9D, the chromium film Cr and the aluminum-neodymium film AlNd are deposited at about 500 mW and 2,500 mW, respectively, and are etched using a third mask to etch the gate line 110. And data such as data lines 310, 311, and 312 in the vertical direction crossing the first and second common electrode lines 120 and 140, and data pads 360, 361, and 362 connected to ends of the data lines 310. First and second pixel electrode lines 330, 331, 332; 350, 351, and 352 overlapping the wiring and drain electrodes 320, 321, and 322, and the first and second common electrode lines 120 and 140, respectively. Pixel electrode wirings such as a plurality of pixel electrodes 340, 341, and 342 alternately arranged in parallel with the electrode 130 are formed. Next, the contact layer 210 exposed to the outside of the data lines 310 and 360 and the pixel electrode lines 330, 340, and 350 is removed.

Finally, a silicon nitride film is deposited to about 2,000 Å and etched using a fourth mask, and the upper portion of the gate line 110, the data line 310, and the gate line 110 except for the portion where the channel portion of the thin film transistor is to be formed. The protective insulating layer 50 is removed from the gate area 150 and the data pad 360 in the enclosed pixel area. In this step, the semiconductor layer 200 and the gate insulating film 20 are simultaneously removed in the same pattern as the protective insulating film 50 pattern. Thereafter, the upper aluminum layers 122, 132, and 142 of the common wirings 120, 130, and 140 exposed to the outside, and the upper aluminum-neodymium layers 332, 342, and 352 of the pixel electrode wirings 330, 340, and 350. Remove it. At this time, the upper aluminum film 152 of the gate pad 150 and the upper aluminum-neodymium film 362 of the data pad 360 are also removed. Through these steps, the wiring and electrode structures of the thin film transistor substrate for the liquid crystal display device as shown in FIGS. 3 to 6 are completed.

As described above, in the method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, the three-layer film patterns 20, 200, and 210 are formed to surround the gate wirings 110 and 150 and the common wirings 120, 130, and 140. ), And the protective insulating film 50 is patterned so that the inside of the pixel region is removed, and then the semiconductor layer 200, the gate insulating film 20, and the common electrode 130 exposed to the outside by using the protective insulating film 50 pattern. Since the upper aluminum film 132 and the upper aluminum-neodymium film 342 of the pixel electrode 340 are removed, the common electrode 130 and the pixel electrode 340 are formed on the same insulating substrate as the upper layer. The wiring structure in which the gate insulating film 20 and the protective insulating film 500 do not exist can be formed using only four masks.

As described above, in the present invention, since the protective insulating film does not exist on the electrode, the DC component is reduced and the afterimage is removed, and the electrode gap can be widened under the same driving voltage, thereby improving the aperture ratio. In addition, since such an electrode and a wiring structure can be formed using four masks, there is an effect of simplifying the process.

Claims (14)

Insulation board, A plurality of gate lines formed in the horizontal direction on the substrate, A plurality of data lines formed in a vertical direction and insulated from and intersecting with the gate lines by a three-layer film pattern of a gate insulating film and a semiconductor layer and a doped semiconductor layer, A plurality of pixel regions in which the gate lines and the data lines cross each other, A drain electrode overlapping the gate line via the three layer pattern; A plurality of pixel electrodes formed in parallel with each other on the substrate surface in the pixel region and extending from the drain electrode, and A plurality of common electrodes formed on the substrate surface in the pixel region and alternately arranged side by side with the pixel electrode; Thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, And a protective insulating layer covering the data line, the portion from the data line to the drain electrode, and the drain electrode, and a protective insulating layer disposed on the common electrode in the pixel region and on the pixel electrode. Thin film transistor substrate. In claim 2, The data line, the drain electrode, and the pixel electrode have a double layer structure of a lower metal layer and an upper aluminum alloy layer, and the upper aluminum alloy layer of the pixel electrode is removed in the pixel region. Transistor substrate. In claim 3, The lower metal film is a thin film transistor substrate for a liquid crystal display device formed of a chromium film. In claim 2, The gate line and the common electrode have a double layer structure of a lower metal layer and an upper aluminum layer, and the upper aluminum layer of the common electrode is removed in the pixel area. Depositing a first metal film on the insulating substrate, Patterning the first metal layer to form a first wiring including a gate line and a plurality of common electrodes; Continuously depositing a three-layer film of a gate insulating film, a semiconductor layer, and a doped semiconductor layer on the substrate on which the first wiring is formed; Patterning the three layer layer to form a first three layer pattern surrounding the gate line and the common electrode; Depositing a second metal film, Patterning the second metal film to form a second wiring including a data line, a drain electrode, and a plurality of pixel electrodes; Removing the doped semiconductor layer exposed out of the second wiring; Depositing a protective insulating film, and Etching the protective insulating layer to leave the protective insulating layer on the channel portion between the data line and the data line and the drain electrode and on the drain electrode; Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 6, And removing the semiconductor layer and the gate insulating layer on the common electrode in the etching of the protective insulating layer. In claim 7, The depositing of the first metal film may include depositing a lower metal film and depositing an upper aluminum film. In claim 8, And removing the upper aluminum layer of the common electrode. In claim 6, The depositing of the second metal film may include depositing a lower metal film and depositing an upper aluminum alloy film. In claim 10, And removing the aluminum alloy layer on the pixel electrode. In claim 9, The depositing of the second metal film may include depositing a lower metal film and depositing an upper aluminum alloy film. In claim 12, And removing the aluminum alloy layer on the pixel electrode in the removing of the aluminum layer on the common electrode. In claim 13, Patterning the first metal layer to form a gate pad; Patterning the three layer layer to form a second three layer layer pattern covering the gate pad; Patterning the second metal layer to form a data pad; Removing the doped semiconductor layer of the second three layer pattern; Etching the protective insulating film, the semiconductor layer of the second three-layer film pattern, and the gate insulating film to form first and second contact holes exposing the gate pad and the data pad, respectively; and And removing the upper aluminum layer of the gate pad and the upper aluminum alloy layer of the data pad exposed through the first and second contact holes.