KR100299127B1 - Apparatus and method for dualizing main processor in asynchronous transfer mode exchanger - Google Patents

Abstract

Control duplication of an asynchronous transfer mode switch having a pair of first and second controllers present in a pair capable of operating in an asynchronous transfer mode switch and operating in a standby mode, and a duplication unit for duplication of the first and second controllers. As a method, when one of the controllers is set to an operation mode, the first transceiver and the first memory of the operation mode controller are activated, the second memory and the second transceiver are deactivated, and the first transceiver and the second transceiver of the standby mode controller are activated. Activating the first memory and deactivating the second memory; storing data recorded in the first memory of the operation mode controller in the duplexer; and when data recording is finished in the first memory of the operation mode controller, And storing the data stored in the redundant data buffer in the first memory of the standby mode controller.

Description

PARAMETER REDUCTION APPARATUS AND METHOD OF Asynchronous Transfer Mode Switch {APPARATUS AND METHOD FOR DUALIZING MAIN PROCESSOR IN ASYNCHRONOUS TRANSFER MODE EXCHANGER}

The present invention relates to an asynchronous transfer mode exchange, and more particularly, to an apparatus and a method for increasing the reliability of the main controller in an exchange.

In general, an asynchronous transfer mode exchange performs transmission and reception of packetized data different from that of a general exchange. The packet data is currently defined as 53 bytes. When transmitting and receiving data using the asynchronous transmission mode exchange, a large amount of data can be transmitted and received more quickly, and a user who transmits and receives data can receive a high quality service. Such an asynchronous transmission mode switch is mainly composed of a subscriber unit in charge of an interface with a subscriber station, a trunk unit for a transmission operation, a signal processor for performing specific signal processing, and a central unit for switching. The above-mentioned subscriber part, trunk part, signal processing part and center part are provided with control processors (main processors) for controlling the operation of each part. However, each control unit is composed of only one pair, and does not perform accurate exchange of data with each other. Accordingly, while one processor is running, the other processor cannot perform the operation in the standby mode.

Therefore, when the operation control program is upgraded in the asynchronous transmission mode switch, or when one of the controllers is down due to an error during operation, the controllers of the other side, which are present in pairs, are in standby mode. Since the data exchange was not performed, the operation performed by the controller could not be performed successively. Therefore, if this phenomenon occurs, it will cause great confusion in the asynchronous transmission network, and the user will be interrupted in service. In addition, even if this situation occurs only a few times, the reliability of the asynchronous transfer mode switch is extremely degraded.

It is therefore an object of the present invention to provide an apparatus and method for improving the reliability of an asynchronous transfer mode switch.

Another object of the present invention is to provide an apparatus and method for duplexing a control unit of an asynchronous transfer mode switch.

According to a first aspect for achieving the above object, the present invention is a control unit redundancy apparatus of an asynchronous transmission mode switch, which performs the overall operation of the exchange in the operation mode in the asynchronous transmission mode switch and the control unit in the standby mode. The first and second controllers present as a pair for monitoring the operation of the controller and updating the program; and the data and the storage area recorded when the data is recorded by the controller of the operation mode among the first and second controllers. A redundancy unit for recording and storing the same data in the same area in the standby mode control unit, and a PSI bus bridge for performing communication through a PCI bus between the first and second control units and lower devices. And first and second controllers each have a predetermined memory and are in standby mode in the asynchronous transfer mode switch. A processor which performs different tasks according to an operation mode, a first memory in which data is recorded in an operation mode of the processor or data recorded in an operation mode controller in a standby mode, and a program is updated in a standby mode of the processor A second memory to be used, a first transceiver for converting data recorded in the first memory from the processor, a second transceiver for converting data recorded in the second memory from the processor, and the processor. A transceiver redundancy controller for controlling activation or deactivation of the first and second transceivers according to an operation mode or a standby mode under control of the first and second memories according to an operation mode or a standby mode under control of the processor; Memory redundancy controller to control activation or deactivation The.

According to a second aspect for achieving the above objects, the present invention provides a first and second control unit which exists in a pair capable of operating in an operation mode and a standby mode in an asynchronous transmission mode switch, and the first And a redundancy unit for redundancy of the second control unit. The method of redundancy of the asynchronous transmission mode switch comprising: a first transceiver and a first memory of the operation mode control unit being activated when one of the control units is set to an operation mode; Deactivating a second memory and a second transceiver, activating a first transceiver, a second transceiver, and a first memory of the standby mode controller; and deactivating a second memory; data written to the first memory of the operation mode controller; Storing data in the first memory of the operation mode controller; It characterized by yirueojim the data stored in the redundant data buffer duplicated portion to the step of storing in the first memory of the standby mode controller.

1 is a block diagram of a main control unit redundancy apparatus according to a preferred embodiment of the present invention;

2a to 2d is a flow chart of the operation and control when the control unit redundant according to the present invention,

3 is a timing diagram according to the flow proceeding from step 208 to step 224 of Figure 2 in accordance with an embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a control unit redundancy apparatus according to a preferred embodiment of the present invention.

1, reference numeral 10 denotes a first control unit having a first main control unit, and reference numeral 20 is a second control unit having another control unit (controller for redundancy). 30 is a duplication unit for duplication of the first control unit 10 and the second control unit 20.

First, the configuration of the first control unit 10 will be described. In the following description, the first controller and the other controller are referred to as a first main processor and a second main processor, respectively. The first main processor 11 is located at the subscriber unit, trunk unit, signal processing unit, and central unit of the asynchronous transmission mode switch to control the overall operation of each unit. The first main processor 11 may be configured as a microprocessor, and when configured as a processor of the UltraSPARC-i series of the US SUN, the first main processor 11 may be replaced when a version of the microprocessor is upgraded later. In the present invention, when configured with the UltraSparc-based processor, the first main processor 11 includes a cache memory externally included.

The first main processor 11 is connected to the transceivers 12a and 12b and transmits data to be recorded in the memory to the transceivers 12a and 12b. In the transceivers 12a and 12b illustrated in FIG. 1, three of the transceivers are illustrated as one transceiver. However, the number constituting the transceiver may be changed by a designer. The transceivers 12a and 12b perform data conversion to write data received from the first main processor 11 into memories 13a and 13b. Referring to the conversion of the data, when the first main processor 11 is configured as an UltraSparc processor, data received in 72 bits from the first main processor 11 is converted into 144 bits to be stored in a memory, and the converted data Are written into the respective memories 13a and 13b. As shown in FIG. 1, the transceiver 12a corresponds to the memory 13a, and the transceiver 12b corresponds to the memory 13b and is matched with a bus of 144 bits. The memories 13a and 13b are dual-in-line memory modules (DIMMs) of 168 pins, and one module may be configured to support up to eight modules of 8 to 128 MB. In addition, the first main processor 11 may enable or disable the transceivers 12a and 12b and the memories 13a and 13b according to a case where the first controller 10 is in an operation mode and a standby mode. do. The first main processor 11 generates a control signal according to the enable or disable of the memories and the transceivers, and outputs the control signal to the transceiver duplication controller 14 and the memory duplication controller 15. The transceiver redundancy controller 14 activates one of the transceivers 12a and 12b and deactivates the other transceiver under the control of the first main processor 11. The memory duplication controller 15 controls the activation and deactivation of the memories 13a and 13b by the control of the first main processor 11, and activates one or both of the memories according to the mode of the controller.

The first controller 10 and the second controller 20 have the same configuration, the first main processor 11 corresponds to the second main processor 21, and the memories 13a and 13b correspond to the memories 23a and 23b, respectively. Transceivers 12a and 12b correspond to transceivers 22a and 22b, respectively, and the transceiver duplication controller 14 included in the first control unit corresponds to a transceiver duplication controller 24, and the memory duplication controller 15 corresponds to a memory duplication controller 25, respectively. Accordingly, the first controller 10 and the second controller 20 may perform the same operation, and perform an operation according to the setting of the operation mode or the standby mode inside the asynchronous transmission mode switch.

Next, the configuration of the redundancy unit 30 will be described. The redundant data buffer 32 is connected to the data bus connected from the transceiver 12a to the memory 13a, and is also connected to the data bus connected from the transceiver 22a to the memory 23a. Therefore, the data output from the transceiver 12a to the memory 13a or the data output from the transceiver 22a to the memory 23a are stored in the redundant data buffer 32, and the data stored in the redundant data buffer 32 is stored in the memory of the opposite controller. . In the following description, it is assumed that the first control unit 10 operates in the operation mode and the second control unit 20 operates in the standby mode for convenience of understanding. When data is required to be written to the memory, the first main processor 11 outputs a data write request signal and an address to the memory duplication controller 15. The redundant buffer controller 31 is connected together to a bus from the first main processor 11 to the memory redundant controller 15 and thus receives the write request signal for the data.

The redundant buffer controller 31 controls the redundant address buffer 33 to store the address output from the first main processor 11, and the redundant buffer controller 31 checks the end of the write request signal. Therefore, when the write request signal ends, the redundant buffer controller 31 outputs a write request signal for writing data to the memory 22a to the memory duplication controller 25, and controls the duplication address buffer 33 to control the memory duplication controller 25. A low address is output to designate an address to be written to the memory 23a. Accordingly, the redundant buffer controller 31 controls the redundant data buffer 32 to write the stored data to the memory 23a. The duplication buffer controller 31 deletes the data recorded in the duplication data buffer 32 and the duplication address buffer 33 when copying of the data from the first controller 10 to the second controller 20 ends. The second controller 20 operates in the standby mode, receives upgrade data received by the second main processor 21, and writes the upgrade data to the memory 23b through the transceiver 22b. In the above description, the first control unit 10 is set as the operation mode and the second control unit 20 is described as the standby mode. However, the reverse operation is performed in the same manner.

The first control unit 10 and the second control unit 20 are connected to the PCI bus bridges 41 and 51 via PCI buses, respectively, and each of the PCI bus bridges 41 and 51 is a part and an external part of the asynchronous transfer mode switch. Transmit and receive data received from Accordingly, each of the PCI bus bridges 41 and 51 is connected to a small computer system interface (SCSI) controller 42 and 52 for reading and writing data from a hard disk, respectively. I / O) is connected to controllers 43 and 53. Thus, the SCSI controllers 42 and 53 are connected to one hard disk, and each of the I / O controllers 43 and 53 is connected to a serial communication controller, NVRAM, EPROM, Ethernet, and the like.

2A to 2D are flowcharts of an operation and control when the control unit is redundant according to the present invention, and are connected to each other according to reference numerals A to D.

3 is a timing diagram according to the flow proceeding from step 208 to step 224 of FIG. 2 according to an embodiment of the present invention.

Hereinafter, the data sharing process of the redundant control unit will be described in detail with reference to FIGS. 1 to 3. Also, for convenience of explanation, it is assumed that the first controller 10 operates in the standby mode and the second controller 20 operates in the standby mode, and it is described from the time when the first controller 10 and the second controller 20 are initialized. Let's do it.

When the asynchronous transfer mode switch is initialized, the first main processor 11 and the second main processor 21 respectively check whether their controller is in an operation mode. In FIG. 2, when the first control unit 10 is in the operation mode, it is displayed as the A operation mode, and when the second control unit 20 is the operation mode, it is displayed as the B operation mode. The first main processor 11 and the second main processor 21 proceed to step 202 when the first control unit 10 is in the operation mode, and proceeds to step 240 when the second control unit 20 is in the operation mode. In operation 202, the first main processor 11 controls the transceiver duplication controller 14 and the memory duplication controller 15 to activate the memory 13a and the transceiver 12a, and deactivate the transceiver 12b and the memory 13b. In addition, the second main processor 21 controls the transceiver duplication controller 24 and the memory duplication controller 25 in a standby mode to activate the memories 23a and 23b and the transceiver 22b and to deactivate the transceiver 22a. When the activation and deactivation are terminated, the first main processor 11 proceeds to an operation mode and the second main processor 21 operates in a standby mode. Accordingly, the second main processor 21 may perform other tasks according to the upgrade and the standby mode of the asynchronous transfer mode switch.

The redundant buffer controller 31 proceeds to step 204 in order to share data due to the duplication of the controller, and checks whether a write request signal MEM_RAST_L (Memory Row Address Strobe-Low active) is received from the first main processor 11 in a low state. do. When the test result write request signal MEM_RAST_L is applied in a low state, the redundant buffer controller 31 controls the redundant data buffer 32 and the redundant address buffer 33 to enable reception of data and provides a low value to the redundant address buffer. Record the address data ROW_ADDR and proceed to step 206. The redundant buffer controller 31 stores the row_address data ROW_ADDR applied to the memory replication controller 15 from the first main processor 11 in the replication address buffer 33 in step 206. Referring to FIG. 3, since the write request signal MEM_RAST_L is applied at time T ₁ , the data is written to the redundant data buffer 32 and the redundant address buffer 33 so that data can be written to the low_address until the time T ₂ . The data ROW_ADDR is written to the redundant address buffer 33. In addition, the memory duplication controller 15 applies a write point signal MEM_CAL_L (MemoryColumn Address Strobe_Low) to the memory 13a at a time T ₃ . The write point signal MEM_CAL_L is a signal that determines a point to be actually written to the memory. In step 206, the redundant buffer controller 31 proceeds to step 208 to check whether the write signal MEM_WR_L (Memory Write Enable_Low) is received in a low state. The write signal MEM_WR_L refers to an enable signal for writing to the memory 13A. The redundant buffer controller 31 proceeds to step 210 when the recording signal MEM_WR_L is received in the low state as a result of the check, and proceeds to step 242 when the record signal MEM_WR_L is received in the low state, and records the request stored in the redundant address buffer 33 stored in the step 206. The row_address data ROW_ADDR stored according to the signal MEM_RAST_L is deleted.

Therefore, if the process proceeds from step 208 to step 210, the memory duplication controller 15 stores the signal output from the first main processor 11 in the duplication address buffer 33 to designate the memory 13a. Accordingly, the memory redundancy controller 15 designates a column_address0 COL_ADDR0 (Column Address 0) region as the memory 13a. At this time, the data D01 is stored in the memory 13a through the transceiver 12a. Referring to FIG. 3 again, since the MEM_CAL_L signal is applied from the time point T _{3 to the} time point T ₄ , the data D01 is stored in the memory 13a in the column_address0 COL_ADDR0 (Column Address 0).

When the storage operation is completed, the redundant buffer controller 31 proceeds to step 212 to check whether the write signal MEM_WE_L is output from the first main processor 11 to the memory replication controller 15. The redundant buffer controller 31 proceeds to step 214 when the recording signal MEM_WE_L is output from the first main processor 11 as a result of the check, and proceeds to step 244 when the recording signal MEM_WE_L is not output. First, in step 212 to step 244, the redundant buffer controller 31 outputs the write request signal MEM_RAST_L according to the row_address data ROW_ADDR stored in the redundant address buffer 33 to the memory redundant controller 25 of the second controller 20. do. In operation 246, the redundant buffer controller 31 controls the redundant address buffer 33 and the redundant data buffer 32 to output and write COL_ADDR0 and D01 stored in the redundant address buffer 33 to the memory 23a. When the write operation is completed, the redundant buffer controller 31 proceeds to step 248 to delete the contents stored in the redundant data buffer 32 and the redundant address buffer 33 and proceeds to step 204.

In contrast, when the redundant buffer controller 31 proceeds from step 212 to step 214, the redundant buffer controller 31 stores COL_ADDR1 in the redundant address buffer 33 and stores data D23 in the redundant data buffer 32. Referring to FIG. 3 again, since the recording point signal MEM_CAL_L is applied from the time point T _{6 to the} time point T _7, the COL_ADDR1 data is stored in the redundant address buffer 33, and the data 23 is stored in the redundant data buffer 32. do. When the storing is completed, the redundant buffer controller 31 proceeds to step 216 to check whether the write signal MEM_WR_L is received from the first main processor 11. The redundant buffer controller 31 proceeds to step 218 when the write signal MEM_WR_L is received as a result of the check, and proceeds to step 250 when the write signal MEM_WR_L is not received.

First, in step 216 to 250, the duplicated buffer controller 31 controls the duplication address buffer 33 to output the write request signal MEM_RAST_L according to the row address data ROW_ADDR to the memory 23a, and proceeds to step 252. . The redundant buffer controller 31 outputs and writes the COL_ADDR0 stored in the redundant address buffer 33 and the data D01 stored in the redundant data buffer 32 to the memory 23a in step 252. When the writing of the data D01 is finished, the redundant data buffer controller 31 outputs and writes COL_ADDR1 stored in the redundant buffer 33 and data D23 stored in the redundant data buffer 32 to the memory 23a in step 254. When the storage operation is finished in steps 250 to 254, the redundant buffer controller 31 deletes the contents stored in the redundant data buffer 32 and the redundant address buffer 33 and proceeds to step 204.

In contrast, in step 216 to step 218, the redundant buffer controller 31 stores the COL_ADDR2 output from the first main processor 11 to the memory replication controller 15 in the redundant address buffer 33 and through the transceiver 12a. The data D45 stored in the memory 13a is stored in the redundant data buffer 32. Referring to FIG. 3 again, a signal for controlling the memory duplication controller 15 to output the COL_ADDR signal from the memory duplication controller 15 to the memory 13a from the time point T _{8 to the} time point T ₉ is transmitted to the duplication address buffer 33. Save it. Therefore, the data D45 outputted to the memory 13a through the transceiver 12a until the time points T _{8 to} T ₉ are simultaneously stored in the memory 13a and the redundant data buffer 32. When the storage operation is completed, the redundant buffer controller 31 proceeds to step 220 and checks whether the write signal MEM_WR_L is output from the first main processor 11. The redundant buffer controller 31 proceeds to step 222 when the write signal MEM_WR_L is output, and proceeds to step 260 when the write signal MEM_WR_L is not output.

First, the case proceeds from step 220 to step 260. When the redundant buffer controller 31 proceeds from step 220 to step 260, the redundant buffer controller 31 outputs another write request signal MEM_RAST_L to the memory replication controller 25 in the row_address data ROW_ADDR stored in the redundant address buffer 33 in step 206. The redundant buffer controller 31 outputs and writes the COL_ADDR0 stored in the redundant address buffer 33 and the data D01 stored in the redundant data buffer 32 to the memory 23a in step 262. In addition, the redundant buffer controller 31 outputs COL_ADDR1 and COL_ADDR2 stored in the redundant address buffer 33 to the memory 23a through steps 264 to 266, and outputs data D23 and D45 stored in the redundant data buffer 32 to the memory 23a. Save it. When the storage operation is completed, the redundant buffer controller 31 proceeds to step 268 to delete contents stored in the redundant data buffer 32 and the redundant address buffer 33 and proceeds to step 204.

In contrast, if the redundant buffer controller 31 proceeds from step 220 to step 222, the redundant buffer controller 31 stores the COL_ADDR3 outputted to the memory duplication controller 15 and the data 67 outputted to the memory 13a in the redundant data buffer 32. Referring to FIG. 3 again, since the recording point signal MEM_CAL_L is outputted to the memory 13a from the time point T _{10 to the} time point T ₁₁ , the redundant address buffer 33 stores the COL_ADDR_3 signal at the same time point. The redundant data buffer 32 stores data D67.

When the storage operation is completed, the redundant buffer controller 31 proceeds to step 224 to check whether the write request signal MEM_RAST_L is output from the first main processor 11 in a high state, and if the write request signal MEM_RAST_L is output in a high state, step 226. Proceed to The redundancy buffer controller 31 controls the redundancy address buffer 33 in step 226 to output the write request signal MEM_RAST_L to the memory 23a through the memory redundancy controller 25 according to the row address data ROW_ADDR stored in step 206. do. In addition, the redundant buffer controller 31 outputs the COL_ADDR_L signal stored in the redundant address buffer 33 to the memory replication controller 25 and outputs and writes D01 stored in the redundant data buffer 32 to the memory 23a in step 228. In addition, the redundant buffer controller 31 outputs COL_ADDR1, COL_ADDR2, and COL_ADDR3 stored in the redundant address buffer 33 to the memory redundant controller 25 in steps 230 to 234, and outputs data D23, D45, and D67 stored in the redundant data buffer 32. Output to the memory 23a and write it. In step 204, the duplicated address buffer 33 deletes the addresses and data stored in the duplicated data buffer 32 and the duplicated address buffer 33 when the recording operation is completed through the above steps.

As described above, the control unit of the asynchronous transmission mode switch has an advantage that the control unit can actually operate in the standby mode. Therefore, when the control unit is duplicated, there is an advantage that the exchange can operate normally and perform data upgrade. In addition, when one control unit is abnormal, the control unit of the standby mode immediately executes the operation of the operation mode control unit without successive operation of the operator, thereby providing a continuity of tasks, thereby increasing the reliability of the exchange.

Claims (5)

In an asynchronous transfer mode exchange, First and second controllers which perform an overall operation of the switch in the asynchronous transmission mode switch in an active mode, and monitor the operation of the controller in the standby mode and update a program; A redundancy unit configured to record the recorded data and the storage area when data is recorded by the control unit of the operation mode among the first and second control units, and store the same data in the same area in the standby mode control unit; Each of the first and second controllers and a subsidiary device is provided with a fisheye bus bridge for communicating through a fisheye bus, wherein the first and second controllers, A processor having a predetermined memory and performing different tasks according to a standby mode and an operation mode in the asynchronous transfer mode switch; A first memory that records data in an operation mode of the processor or backs up data recorded in an operation mode controller in a standby mode; A second memory used to update a program in the standby mode of the processor; A first transceiver for converting data recorded in the first memory from the processor; A second transceiver for converting data recorded in the second memory from the processor; A transceiver redundancy controller controlling the activation or deactivation of the first and second transceivers according to an operation mode or a standby mode by the control of the processor; And a memory duplication controller configured to control activation or deactivation of the first and second memories according to an operation mode or a standby mode under the control of the processor. The method of claim 1, wherein the redundancy unit, A redundant data buffer connected in common with the data line connected to the first memory from the first transceiver of the first controller or the second controller; A redundant address buffer commonly connected to an address line connected from the processor of the first controller or the second controller to a memory duplication controller; Receiving a recording signal output from the processor to the memory redundancy controller and controls the data stored in the memory of the operation mode control unit to be stored in the redundant data buffer according to the recording signal, and at the end of the recording signal to the redundant data buffer And a redundant buffer controller for copying the stored data to the memory in the standby mode and controlling the deletion of the data stored in the redundant data buffer. In the asynchronous transmission mode switch, a pair of first and second controllers present in a pair capable of operating in an operation mode and a standby mode, a redundancy unit for redundancy of the first and second control units, and each control unit includes a first And a control unit duplication method of an asynchronous transmission mode switch having a second transceiver and first and second memories, respectively. When one of the controllers is set to an operation mode, the first transceiver and the first memory of the operation mode controller are activated, the second memory and the second transceiver are deactivated, and the first transceiver, the second transceiver, and the first transceiver of the standby mode controller are activated. Activating the first memory and deactivating the second memory; Storing data recorded in the first memory of the operation mode controller in the duplexer; And storing data stored in the redundant data buffer of the redundant unit in the first memory of the standby mode controller when data recording is finished in the first memory of the operation mode controller. Redundancy Method. The method of claim 3, And deleting the data stored in the redundancy unit when the data stored in the redundancy unit is terminated in the first memory of the standby mode control unit. The method of claim 3 or 4, wherein the data stored in the redundancy unit when the operation mode control unit is stored is And data stored in the first memory, an address specifying an area to be stored in the first memory, and a storage request signal for storing.