JPS59133623A - Storage system of bus information log - Google Patents

Abstract

PURPOSE:To make the analysis easy at a trouble detection time, by storing the state on a bus in certain continuous cycles including idle cycles and reading out this stored information to use it for trouble analysis at the trouble detection time. CONSTITUTION:A bus log storage circuit BHR 15 connected to a bus 10 is provided. The circuit 15 incorporates a memory having a certain capacity and stores bit states of an address/data line, a command line, etc. on the bus 10 in the incorporated memory at intervals of every bus cycle time including idle cycles with respect to required information of these lines. Stored contents are rewritten in order from the oldest contents if they exceed a certain quantity of words, and a certain quantity of the latest information is always stored. Information of the data line, the command line, a unit ID line, and a control line are stored in individual words. Consequently, the contents of the circuit 15 are referred to at the time when a trouble is detected to make the analysis easy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a path history information storage method for a data processing system using synchronous paths.

[Technical background of the invention and its problems]

FIG. 1 is a diagram showing the configuration of a data processing system in which a plurality of units are connected via paths.

In the figure, IO is the path and central processing unit (
CPU II), upper storage unit) (MMI2), input/output channels (IOCZ, ?), etc. are connected to transmit and receive information via this path IO.

In the figure, an example of a signal propagating on the path IO is shown in a circle.

There are various signal lines on the path XO, and each unit I1.1
Used for 2*I3 information exchange.

2I is a group of data signal lines, on which data transferred between each unit is carried. When the CPU II accesses the main memory 12f, a cycle for transferring an address and a cycle for transferring data are assigned to the data line 21.

22 is a command line through which commands for instructing operations are transferred between the units IZ and I2°Z3. Reference numeral 23 denotes a sending/receiving unit ID line, which is provided to identify the unit sending data and the unit receiving data. 24 is a control line through which signals for controlling path contention and other things are propagated. 25 is a clock line that defines a pass cycle.

These signal lines are grouped in appropriate units.

It is common to have additional signals for detecting errors such as parity pits.

FIG. 2 is a diagram for explaining an overview of the operation of the synchronous path. On the path Io, each unit 11, Z2 . A line is provided for propagating a synchronization clock commonly used by I3, and a bus cycle is defined at fixed time intervals according to the clock propagated through this line. Each unit ll, 7211
Data transfer between 3 is performed in units of cycles. For example, a case where CPUZI reads the contents of main memory 12 will be explained. In the figure, in the n-th cycle, a memory address and a memory read command are transferred from the CPU II to the main memory I2. When the main memory I2 receives this information, it starts memory access, and when the data is ready, in this figure, the data is transferred from the main memory Z2 to the CPU Z at the (n+3)th cycle.
Data is transferred once.

Next, data storage into the main memory Z2 will be explained. In the figure, from l0CI3 to main memory 12 at the n+5th cycle.
- Transfer memory addresses and memory write commands once. Continuation<? xnIn the 16th cycle, 1(J
Write data is transferred from CIB to main memory Z2.

In a synchronous path that operates in the above manner.

When a problem occurs due to path operation, the path history used for analysis includes not only the history of cycles in which the path actually transfers information, but also cycles that are considered to be insignificant as bus cycles. It may be helpful to analyze whether or not the status is truly empty because it remains as a history.

[Purpose of the invention]

The present invention has been made based on the above-mentioned circumstances.
Provides a path history information storage method that facilitates analysis when a failure is detected by storing the status of consecutive cycles on the bus, including idle cycles, in a history information storage device that stores the operating status on the path. The purpose is to

[Key points of invention]

The present invention provides a data processing system in which a plurality of units are connected via a synchronous bus with a path history information storage device that stores the path status of continuous constant cycles, including idle cycles, and analyzes the data processing system when a failure occurs. This is to help when

Further, by adding a register output whose value is updated in the cycle in which the empty state of the path is detected as the information to be stored in this storage device, it is possible to omit storing the path information itself in the empty cycle.

[Embodiments of the invention]

The present invention will be explained below using FIG. 3 and subsequent figures.

Explain in detail. FIG. 3 is a block diagram showing a configuration example of a data processing system to which the present invention is adopted.

In the figure, CPUZI, main memory unit 12゜'r, oc
xs is connected via path IQ as in FIG.

The difference from FIG. 1 is that a path history storage circuit (BHH75) is further connected to the path IO. The path history storage circuit Z5 has a certain amount of memory, and stores information about necessary information lines such as data lines and command lines on the path 10 at each pass cycle time, including idle cycles. The bit status is stored in the internal memory.

When the memory exceeds a certain amount of words, it is possible to always store a certain amount of the latest information by rewriting the words in the oldest order. FIG. 4 shows an example of the contents of each storage word.

Each lard has a data line, command line unit)
Information on the ID line and control line is stored.

FIG. 5 is a block diagram showing another embodiment of the present invention.

In the figure, 51 and 52 are history memories in which path history information is stored, similar to the embodiment shown in FIG. 55 is a history address counter (AC) that specifies the address of the memory 51.52, and the data is added to the history memory 51.5.
21-Updated every time it is written.

The counter 56 is cleared or counted up under the control of control cycle #1151, which will be described later. The output of the counter 66 is a history memo along with path information! It is configured to be stored in I52.

The control circuit 57 monitors the path control line CBC) (-
C on path I0 - When it is detected that significant information is being transferred, the bus information and the contents of the counter 56 are stored in the history memories 51 and 52 (word write WVV), and the contents of the address counter 556 are updated ( +1). At this time, the counter 56 is simultaneously initialized to "0". (C
LR) In a pass cycle in which the control circuit 57 does not detect significant information on the path IO, data is written to the history memory 61 or 52, or an update number to the address counter 55 is not output, but instead the counter 56 is output. A control signal (+1') instructing to count up is output.

FIG. 6 illustrates how the embodiment shown in FIG. 5 stores the history when the pass cycle is used and buried as shown in FIG. 2C.

Information about pass cycle n is stored in word k. The word F k + 1 += stores the information of pass cycle -n+3 which transfers significant information next to pass cycle n (the value "2" is stored as the content of the second counter 56). This means that there were two empty cycles before pass cycle n+3.

As can be seen, by using the counter 56, it is possible to omit storing the contents of the bus information in idle cycles.

For example, if the counter 56 is made up of 3 bits, the counter 57 can obtain eight states from 0# to 7#. If eight consecutive empty cycles occur in path 10, the counter 56 returns to the initial value "0#," and in this state, it may become unclear whether the number of empty cycles i was 8 or not. This can be prevented. In order to
The control circuit 5F also monitors the contents of the counter 56, and when the value of the counter 56 reaches a constant value 1, for example @7#, the counter 56 is configured not to be updated even in an idle cycle thereafter. As a result, Kara ν! The content of 56 has a value of 0 to 6.
It is possible to make it possible to indicate that there were 0 to 6 empty cycles, respectively, and to indicate that there were 7 or more empty cycles by using a binary value of "7".

〔Effect of the invention〕

As described above, according to the present invention, when a failure is detected, analysis is facilitated by referring to the contents of the path history information storage device, and furthermore, when a path idle is detected in this storage device, the value is updated. By also supplying the counter output, it is possible to omit storing the bus information itself in idle cycles.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a general data processing device, FIG. 2 is a diagram showing an environment in which a path cycle is used to explain the outline of the operation of a synchronous path, and FIG. 3 is a diagram showing an implementation of the present invention. Figure 4 shows an example of the path history storage circuit shown in Figure 3:
FIG. 5 is a diagram showing an example of each storage word stored in a built-in memory, and FIG. 5 is a diagram showing another embodiment of the present invention. FIG. 6 illustrates how history is stored according to the present invention in the pass cycle operating environment shown in FIG. 15...Path history storage circuit (Bl(R), 51, 5
21.・History memory, 55...Address counter, 5
6...Counter, 52...Control circuit.

Claims (2)

[Claims] (1) In a data processing system in which a plurality of units are connected via a synchronous path, a means is provided for storing the path state of continuous constant cycles including idle cycles, and when a failure is detected, the stored information This path information history storage method is characterized by a continuous flow of path information and is used for failure analysis. (2) history storage means for storing information on the path; Idle detection means for detecting whether or not a path is in an idle state; cycle I in which the idle detection means detects path idle; register means corresponding to which a value of 1 is updated; and the idle detection means detects a path usage state. The path information according to claim 1, characterized in that the state on the path and the contents of the register means are stored in the history storage means in correspondence with the cycle in which the path information is stored, and the contents of the register means are initialized. History storage method.