KR100286972B1 - Receive buffer control apparatus of processor communication controller board assembly and the method thereof - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Electronic exchanger

2. The technical problem to be solved by the invention

This is to solve the problem of setting the receiving address as the starting address of the new receiving buffer each time a new message is received in the receiving buffer of the inter-processor communication control circuit pack (PCCA) in the conventional electronic switching system.

3. Summary of Solution to Invention

A direct memory access control unit which stores a received message at a receiving address of a receiving buffer identifier in the valid multiple receiving buffer identification unit 120 as an input of a receiving message and sets the receiving buffer identifier to be used as a valid receiving buffer identifier next time. 110); A multi-receive buffer identification unit 120 which presets the start address of the reception buffer in each of the reception buffer unit 130 under the control of the direct memory access control unit 110; The reception buffer 130 receives a message from the multiple reception buffer identification unit 120 and temporarily stores the message.

4. Important uses of the invention

This is applied to the reception buffer management of inter-processor communication control circuit pack in all electronic switch.

Description

Receiving buffer control device and communication method of communication control circuit pack

In general, an electronic switch is a device that replaces most of the electromechanical devices constituting the exchanger with electronic parts, and performs an exchange connection function, a charge and maintenance operation function between the sender and the receiver.

A conventional Receive Buffer (hereinafter referred to as "RxBuf") device of a Processor Communication Controller Board Assembly (hereinafter, referred to as "PCCA") is shown in the accompanying drawings. When the received message is input, the direct memory access control unit 10 stores the received message in the receiving address of the receiving buffer identification unit 20 and sets the receiving address of the receiving buffer identification unit 20 as the starting address of the receiving buffer. ; A reception buffer identification unit 20 for setting a start address of a reception buffer under the control of the direct memory access control unit 10 and transmitting a message to the reception buffer unit 30; The reception buffer 30 is configured to receive and temporarily store a message from the reception buffer identification unit 20.

Referring to the accompanying drawings, the operation of the conventional electronic switchboard PCCA receiving buffer device configured as described above is as follows.

First, the reception buffer RxBuf to be received first is set to a reception standby state, and a reception address of the reception buffer identification unit 20 is set as a start address of the reception buffer. When the message is received from the IPC node by the direct memory access control unit 10, the direct memory access control unit 10 stores the received message in the data address of the receiving buffer identification unit 20. do. Thereafter, the direct memory access control unit 10 sets a reception completion mark in the reception buffer RxBuf of the reception buffer unit 30 where reception has been completed.

The direct memory access control unit 10 sets the start address of the next reception buffer RxBuf of the reception buffer unit 30 to the reception address of the reception buffer identification unit 20, and switches to a message reception possible state.

Then, when the next message is received, the direct memory access control unit 10 repeats the above-described process of temporarily storing the message in the reception buffer unit 30 to receive the message.

However, in the above-described message receiving method of the inter-processor communication control circuit pack, the receiving buffer management is required by the direct memory access controller to set the receiving address of the receiving buffer identification unit as the starting address of the new receiving buffer each time a new message is received. There is a problem that the reception performance is deteriorated due to an increase in overhead.

Therefore, the present invention has been proposed to solve the problems that occur when using the PCCA receive buffer in the general electronic switch as described above, the object of the present invention is to use the number of receive buffer identifiers in the receiving buffer management over The present invention provides a receiving buffer control apparatus and method for an all-electronic switch PCCA to reduce head and improve reception performance.

The apparatus for achieving the object of the present invention, by receiving the received message as an input, stores the received message at the receiving address of the receiving buffer identifier in the valid multiple receiving buffer identification unit and the next receiving buffer identifier to be used as a valid receiving buffer identifier A direct memory access control unit for setting; A multiple reception buffer identification unit presetting a start address of a reception buffer (RxBuf) in each reception buffer unit for each reception buffer identifier under the control of the direct memory access control unit; It consists of a receiving buffer for temporarily receiving a message from the multiple receiving buffer identification unit.

According to an aspect of the present invention, there is provided a method comprising: a first step of storing a received message at a reception address of a currently valid reception buffer identifier when a message is received in a message reception standby state; Setting a receiving buffer identifier to be used next after the first step as a valid receiving buffer identifier; A third step of setting a reception completion marker in the reception buffer in which the message reception is completed is performed.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

1 is a block diagram of a receiving buffer controller of a communication processor circuit pack in a conventional all-electronic exchange.

2 is a block diagram of a receiving buffer control apparatus for an interprocessor communication control circuit pack in an electronic switching system according to the present invention;

3 is a flowchart illustrating a receiving buffer control method of an interprocessor communication control circuit pack in an all-electronic exchange according to the present invention.

<Explanation of symbols for main parts of drawing>

110: direct memory access control unit 120: multiple reception buffer identification unit

130: receiving buffer unit

Fig. 2 is a block diagram of a receiving buffer device of an all-electronic switch PCCA to which the present invention is applied.

As shown, the direct memory for storing the received message at the receiving address of the receiving buffer identifier in the valid multiple receiving buffer identification unit 120 by setting the receiving message as an input and setting the receiving buffer identifier to be used as a valid receiving buffer identifier next time. An access control unit 110; A multi-receive buffer identification unit 120 which presets a start address of a receive buffer (RxBuf) in each receive buffer unit 130 with respect to each receive buffer identifier under the control of the direct memory access control unit 110; It consists of a receiving buffer 130 for temporarily receiving a message from the multiple receiving buffer identification unit 120.

3 is a flowchart illustrating a method for improving a reception buffer of the all-electronic exchange PCCA according to the present invention.

As shown therein, a first step (ST1) (ST2) of storing the received message at the reception address of the currently valid reception buffer identifier when the message is received in the message reception standby state; A second step ST3 of setting a reception buffer identifier to be used next time after the first step ST1 and ST2 as a valid reception buffer identifier; A third step (ST4) of setting a reception completion marker in the reception buffer in which the message reception is completed.

Referring to the accompanying drawings, the operation of the PCCA receiving buffer improvement method according to the present invention made as described above is as follows.

First, when a message is received from the IPC node in the direct memory access control unit 110, the direct memory access control unit 110 receives the message received in the data address of the currently valid receiving buffer identifier among the multiple receiving buffer identification units 120. Send it. Then, the reception address of the multiple reception buffer identification unit 120 stores the message in the corresponding RxBuf of the reception buffer 130.

The direct memory access control unit 110 sets the reception buffer identifier in the multiple reception buffer identification unit 120 to be used as a valid reception buffer identifier.

Then, the main processor of the host sets the reception completion mark to the reception buffer in which reception is completed by using the direct memory access control unit 110.

In addition, when a new message is received from the IPC node, the message is temporarily stored in the same manner as in the process of setting the reception completion mark in the received buffer in the direct memory access control unit 110.

Here, the multiple reception buffer identification unit 120 implements using a quad intergated communication controller (MC68360) with a built-in serial communication controller to preset each reception buffer start address for each reception buffer identifier.

As described in detail above, the present invention defines a multi-receive buffer identification unit as the number of receive buffers in the PCCA of the electronic switching center, and assigns each receive buffer identifier to each corresponding receive buffer when receiving a message. By reducing the overhead of setting the receiving address every time, the reception performance of the inter-processor communication control circuit pack is increased.

In addition, the amount of software processing is reduced, so that the host's main processor can perform other tasks during that time, thereby increasing the utilization efficiency of the main processor.

The present invention uses the number of receive buffers in the communication control circuit pack between all electronic switch processors to reduce the overhead of receiving buffer management and improve the reception performance. It is to provide a control device and a method thereof.

Claims (2)

In the receiving buffer control apparatus of the communication control circuit pack between all electronic switch processor, A direct memory access control unit which stores a received message at a receiving address of a receiving buffer identifier in the valid multiple receiving buffer identification unit 120 as an input of a receiving message and sets it as a receiving buffer identifier requiring a receiving buffer identifier to be used next time. 110); A multi-receive buffer identification unit 120 which presets a start address of a receive buffer in each receive buffer unit 130 with respect to each receive buffer identifier under the control of the direct memory access control unit 110; Receiving buffer control device of the communication control circuit pack between all the electronic exchanger processor, characterized in that consisting of a receiving buffer 130 for receiving and receiving a message from the multiple receiving buffer identification unit (120). In the receiving buffer control apparatus of the all electronic switching processor inter-processor communication control circuit pack, a first step (ST1) (ST2) of storing the received message at the receiving address of the currently valid receiving buffer identifier when the message is received in the message receiving standby state. Wow; A second step ST3 of setting a reception buffer identifier to be used next time after the first step ST1 and ST2 as a valid reception buffer identifier; And a third step (ST4) of setting a reception completion mark in the reception buffer in which the message reception is completed.

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